This study presents a new interleaved three-level zero-voltage switching (ZVS) converter for high-voltage and high-current applications. Two circuit cells are operated with interleaved pulse-width modulation in the proposed converter to reduce the current ripple at the input and output sides, as well as to decrease the current rating of output inductors for high-load-current applications. Each circuit cell includes one half-bridge converter and one three-level converter at the primary side. At the secondary side, the transformer windings of two converters are connected in series to reduce the size of the output inductor or switching current in the output capacitor. Based on the three-level circuit topology, the voltage stress of power switches is clamped at V_in /2. Thus, MOSFETs with 500 V voltage rating can be used at 800 V input voltage converters. The output capacitance of the power switch and the leakage inductance (or external inductance) are resonant at the transition interval. Therefore, power switches can be turned on under ZVS. Finally, experiments verify the effectiveness of the proposed converter. High-efficiency DC/DC converters have been studied as power units in the mature stage of the telecommunication systems, server systems, data storage systems, medical instruments, and cloud power units. For three-phase power factor correction (PFC) converters, DC bus voltage may be equal to or greater than 500 V to 800V. Thus, MOSFETs with 500 or 650 V voltage stress cannot be used for DC/DC converters at the mature stage. Although high-voltage MOSFETs can be used in DC/DC converters, such as those with 900 V voltage stress, these units are expensive, and the high turn-on resistance of MOSFETs will reduce circuit efficiency. Three-level or multi-level converters/inverters [1] - [4] have been established by using low-voltage switch devices for high-voltage applications, such as reactive power compensators and high-power motor drives. For modern switching converters, high-efficiency converters are required to reduce circuit size and weight. Therefore, power losses should be reduced to meet this requirement. Soft-switching techniques [5] - [10] with duty cycle control have been developed in three-level converters to reduce the switching losses on power semiconductors. The output capacitance of power switches and the leakage inductance of transformers are resonant at the transition interval to achieve zero voltage switching (ZVS) on power switches. Three-level converters with variable frequency control [11] - [14] have been proposed to enhance circuit efficiency further. If the operating switching frequency is less than the series resonant frequency, the rectifier diodes at the secondary side can be turned off under zero current switching. However, the output ripple current of a three-level resonant converter is larger than that of a conventional three-level PWM converter. Therefore, high output capacitance is necessary for use at the output side. A new three-level converter is presented for high-inputvoltage applications. The proposed converter includes two circuit cells, which are operated by an interleaved pulse-width modulation (PWM) to reduce the output ripple current and decrease the current stress of passive and active power components. Each circuit cell includes a half-bridge circuit and a three-level PWM circuit. In the proposed three-level converter, the voltage stress of power switches is limited to V_in /2. To reduce the ripple current on the output inductors or capacitor, the transformer secondary windings of two PWM circuits are connected in series at the low-voltage side to decrease the output inductor voltage variation. The flying capacitors are used in each circuit cell to balance input split capacitor voltages. Based on the resonant behavior of the output capacitances of MOSFETs and resonant inductance at the transition interval, all power switches can be turned on under ZVS. Finally, experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter. Figs. 1 (a) and 1 (b) show the circuit configurations of the conventional half-bridge and full-bridge converters with 400V input voltage for normal single-phase switching mode power supplies for server power or data storage power units. In Fig. 1 (b), the phase-shift PWM scheme is adopted to regulate output voltage and achieve ZVS for all power switches within the desired load range. Normally, the ZVS condition of power switches at the leading leg is easier to be achieved than the power switches at the lagging leg. For three-phase switching mode power converters, the DC bus after the three-phase power factor corrector is normally controlled at 750 V to 800 V. To use MOSFETs instead of IGBTs for high switching operation, a three-level converter is given in Fig. 1 (c). Two clamped diodes and one flying capacitor are adopted to reduce the voltage stress of power switches at V_in /2 and to balance two input capacitor voltages. Two voltage levels, namely, V_in /(2n) and 0, are observed at the rectified voltage v_rect . If the voltage variation across the output inductor is decreased, the current ripple on the output inductor can be decreased. Thus, one more half-bridge converter can be added to the conventional three-level DC converter to reduce the current ripple at output side. Fig. 2 (a) shows the circuit configuration of the proposed three-level converter. The proposed converter includes a conventional three-level converter [ Fig. 1 (c)] and a half-bridge converter [ Fig. 1 (a)] to reduce the voltage variation on the output inductor. The input voltage V_in is obtained from a three-phase AC/DC converter with PFC. C₁ and C₂ are input as split capacitances to obtain the equal voltages V_C1 = V_C2 = V_in /2. S₁ - S₄ are power MOSFETs with V_in /2 voltage stress. The average voltages of flying capacitors are V_Cf1 = V_Cf2 = V_in /4. C_r1 - C_r4 are the output capacitances of S₁ - S₄ , respectively. L_r1 and L_r2 are resonant inductances. L_o is the output inductance. D₁ and D₂ are rectifier diodes. T₁ and T₂ are the isolated transformers. C_o and R_o denote output capacitance and load resistance, respectively. In the proposed circuit, a three-level converter and a half-bridge converter are used to achieve ZVS turn-on for all switches and to reduce the output inductance or output capacitance. Components C_f1 , C_f2 , S₃ , S₄ , T₂ , and L_r2 are operated as an uncontrolled half-bridge converter with 50% duty cycle. Two voltage levels, V_in /4 and - V_in /4, are generated on v_ac . Components C₁ , C₂ , D_a , D_b , C_f1 , C_f2 , S₁ - S₄ , L_r1 , and T₁ are operated as the conventional three-level converter. Three voltage levels, namely, V_in /2, 0, and - V_in /2, are generated on v_ab . Two voltage levels, V_in /(2 n₁ )+ V_in /(4 n₂ ) and V_in /(4 n₂ ), can be observed on the rectified voltage v_rect . Thus, low ripple current or switching current on the output inductor can be achieved because of the low voltage across the output inductor. The output capacitances of S₁ - S₄ and the resonant inductance (or transformer leakage inductance) are resonant at the transition interval. Therefore, S₁ - S₄ can be turned on under ZVS. To reduce the current ripple further at the input and output sides, as well as to reduce the current rating of output inductor for high load current application, an interleaved three-level converter is shown in Fig. 2 (b). The interleaved PWM scheme is adopted to generate eight gate signals of S₁ - S₄ . The input and output ripple currents of two converters can partially cancel each other. Therefore, the input and output capacitances and output inductances can be reduced. The system analysis of the proposed converter is based on the following assumptions: (1) V_Cf1 = V_Cf2 = V_Cf3 = V_Cf4 = V_in /4; (2) V_C1 = V_C2 = V_C3 = V_C4 = V_in /2; (3) C_r1 = C_r2 =…= C_r7 = C_r8 = C_r ; (4) S₁ - S₈ , D₁ - D₄ , and D_a - D_d are ideal; (5) turn ratio of T₁ and T₃ is n ₁ = n ₃ = n and that of T₂ and T₄ is n ₂ = n ₄ = n /2; and (6) the energy stored in the resonant inductances is greater than that stored in the resonant capacitances, such that the ZVS turn-on of all switches can be achieved. Based on the on/off states of S₁ - S₈ , D_a - D_d , and D₁ - D₄ , 10 operation modes exist in each three-level converter during one switching cycle. The key waveforms of each three-level converter during one switching cycle are given in Fig. 3 . Fig. 4 shows the key waveforms of the proposed interleaved three-level converter. Two output inductor currents partially cancelled each other. Two three-level converters have the same operation modes. Thus, only the operation modes of converter 1 are discussed to simplify the system analysis. Three-level converter 1 has 10 operation modes ( Fig. 5 ). Prior to t₀ , S₁ , S₂ D₁ , and D₂ are conducting. Inductor currents i_Lr1 and i_Lr2 are increasing. Mode 1 [t₀≤t＜t₁, Fig. 5(a)] : At t₀ , i_D2 is decreased to zero current, such that D₂ is off. S₁ and S₂ are still turned on, such that v_ab = V_in /2, v_ac = v_Cf1 = V_in /4, v_rect1 ≈ V_in /(2 n₁ )+ V_in /(4 n₂ )= V_in / n , and v_Lo1 = V_in / n - V_o ＞0. The output inductor current i_Lo1 and the primary currents i_Lr1 and i_Lr2 increase in this mode. Power is transferred from input voltage source V_in /2 to output load R_o . Mode 2 [t₁≤t＜t₂, Fig. 5(b)] : At t₁ , S₁ is turned off. Given that i_Lr1 ＞0 and i_Lr2 ＞0, C_r1 and C_r4 are charged and discharged in this mode. If the energy stored in L_r1 and L_o1 is greater than the energy stored in C_r1 and C_r4 , then C_r4 can be discharged to zero voltage. The ZVS turn-on condition of S₄ can be expressed as This mode ends at t₂ when v_Cr1 = V_in /2 and v_Cr4 = 0 . Mode 3 [t₂≤t＜t₃, Fig. 5(c)] : At t₂ , v_Cr1 = V_in /2, v_Cr4 = 0 , and D_a are conducting. Capacitor voltage v_C2 = v_Cf1 + v_Cf2 = V_in /2. Given that i_Lr1 ＞0, the anti-parallel diode of S₄ is conducting. Thus, S₄ can be turned on at this moment to achieve ZVS. In this mode, the primary side voltage v_ab =0 and v_ac = v_Cf1 = V_in /4, and the secondary side voltage v_rect1 = V_in /(2 n ). The output inductor voltage v_Lo1 = V_in /(2 n )- V_o ＜0, such that that the output inductor current i_Lo1 decreases in this mode. Mode 4 [t₃≤t＜t₄, Fig. 5(d)] : At t₃ , S₂ is turned off. Given that i_Lr1 ＞0 and i_Lr2 ＞0, C_r2 , and C_r3 are charged and discharged, respectively. If the energy stored in L_r1 , L_r2 , and L_o1 is greater than the energy stored in C_r2 and C_r3 , then C_r3 can be discharged to zero voltage. Thus, the ZVS turn-on condition of S₃ can be obtained in (2). Mode 5 [t₄≤t＜t₅, Fig. 5(e)] : At time t₄ , v_Cr2 = V_in /2, and v_Cr3 =0. Given that i_Lr1 ＞0 and i_Lr2 ＞0, the anti-parallel diode of S₃ is conducting. S₃ can be turned on at this moment under ZVS. D₁ and D₂ are conducting to commutate the inductor current i_Lo1 . The secondary side voltage v_rect1 =0, and the inductor current i_Lo1 is decreasing. The primary inductor currents i_Lr1 and i_Lr2 decrease with the slopes - V_in /(2 L_r1 ) and - V_in /(4 L_r2 ), respectively. The slopes of the diode currents i_D1 and i_D2 are given by Based on (3), the relationship of L_r1 and L_r2 can be described as L_r1 =4 L_r2 . At t₅ , i_D1 is decreased to zero current. The current variation on inductor L_r1 is Δ i_Lr1 = i_Lr1 ( t₅ ) - i_Lr1 ( t₄ ) ≈ - I_o /(2 n ) - I_o /(2n) = - I_o / n . The time interval in this mode is given as In this mode, S₃ , S₄ , D₁ , and D₂ are conducting, and the rectified voltage v_rect1 =0. No power is transferred from input voltage source V_in to output load R_o . The duty loss in this mode can be expressed as Mode 6 [t₅≤t＜t₆, Fig. 5(f)] : At t₅ , i_D1 =0. S₃ and S₄ are conducting. The primary side AC voltages v_ab =- V_in /2 and v_ac =- v_Cf2 =- V_in /4, and the output inductor voltage v_Lo1 = V_in / n - V_o ＞0. The primary side inductor currents i_Lr1 and i_L2 both decrease, whereas the output inductor current i_Lo1 increases in this mode. Mode 7 [t₆≤t＜t₇, Fig. 5(g)] : At t₆ , S₄ is turned off. Given that i_Lr1 ＜0 and i_Lr2 ＜0, C_r1 and C_r4 are discharged and charged, respectively. The ZVS turn-on condition of S₁ can be expressed as At t₇ , C_r1 is discharged to zero voltage. Mode 8 [t₇≤t＜t₈, Fig. 5(h)] : At t₇ , v_Cr1 = 0 , and v_Cr4 = V_in /2. Given that i_Lr1 ＜0, the anti-parallel diode of S₁ is conducting. S₁ can be turned on at this moment under ZVS. D_b is conducting, and the AC terminal voltages v_ab =0 and v_ac =- v_Cf2 =- V_in /4. The primary inductor currents i_Lr1 and i_Lr2 are both decreasing. The rectified voltage v_rect1 = V_in /(2 n ), and the output inductor voltage v_Lo1 = V_in /(2 n )- V_o ＜0, such that i_Lo1 decreases in this mode. Mode 9 [t₈≤t＜t₉, Fig. 5(i)] : At t₈ , S₃ is turned off. Given that i_Lr1 ＜0 and i_Lr2 ＜0, C_r2 and C_r3 are discharged and charged, respectively. Similar to (2), the ZVS turn-on condition of S₂ can be obtained as Mode 10 [t₉≤t＜t₀+T_s, Fig. 5(j)] : At t₉ , C_r2 is discharged to zero voltage. Given that i_Lr1 ( t₉ )+ i_Lr2 ( t₉ )＜0, the anti-parallel diode of S₂ is conducting. S₂ can be turned on at this moment under ZVS. D₁ and D₂ are conducting to commutate the load inductor current i_Lo1 . In this mode, S₁ , S₂ , D₁ , and D₂ are conducting. Thus, the rectified voltage v_rect1 =0 and the inductor voltage v_Lo1 =- V_o . No power is transferred from input voltage source V_in to output load R_o . Thus, the duty loss in this mode is given as At t₀ + T_s , i_D2 is decreased to zero current. The circuit operations of the proposed converter in a switching period are then completed. In the above discussions, the charge and discharge times of C_r1 – C_r4 in modes 2, 4, 7, and 9 are significantly less than the other time intervals. Thus, these modes can be neglected in the discussion of circuit characteristics. From modes 3 and 8 in Fig. 5 , the spite capacitor voltages v_C1 – v_C4 can be obtained as v_C1 = v_C2 = v_C3 = v_C4 = V_in /2. Applying the volt-second balance to L_r2 and T₂ in steady state, the average capacitor voltages V_Cf1 – V_Cf4 can be derived as Based on the volt-second balance on output inductors L_o1 and L_o2 , the output voltage V_o can be derived as where V_f is the voltage drop on diodes D₁ . D₄ ; and d is the duty ratio of the AC side voltages v_ab , v_ac , v_de , and v_df . The ripple currents of L_o1 and L_o2 are expressed in (11). where r is the current ripple factor of output inductors. The maximum output inductor currents at steady state are expressed in (12). In modes 1 and 6, the magnetizing ripple currents Δ i_Lm1 -Δ i_Lm4 can be expressed in (13) and (14). where L_m1 = L_m3 , and L_m2 = L_m1 . The average diode currents i_D1,av – i_D4,av and the diode voltage stresses v_D1,stress – v_D4,stress are given in (15) and (16), respectively. If the ripple currents of S₁ - S₈ can be ignored, the root-mean-square ( rms ) currents and the voltage stress of S₁ - S₈ are given in (17)-(19). In mode 2, i_Lr1 ( t₁ ) can be expressed as In mode 4, the inductor currents i_Lr1 ( t₃ ) and i_Lr2 ( t₃ ) can be expressed as Based on (1), (6), and (20), the necessary resonant inductance L_r1 for ZVS turn-on of S₁ and S₄ is expressed in (23). From (2), (7), (21), and (22), the necessary resonant inductance L_r2 for ZVS turn-on of S₂ and S₃ is given in (24). Given that the switch currents i_S5 - i_S8 are similar to i _S1 -i _S4 in steady state, the necessary resonant inductances L_r3 and L_r4 are equal to L_r1 and L_r2 , respectively, to achieve ZVS conditions of S₅ - S₈ . A laboratory prototype shown in Fig. 6 is implemented to verify the effectiveness of the proposed converter. The electrical specifications of the proposed converter are V_in =750 V.800 V, V_o =48 V, I_o =40 A, and f_s =100 k Hz. The resonant inductances in this prototype are L_r1 = L_r3 =48 μ H and L_r2 = L_r4 =12 μ H. The magnetic core TDK EER-40C is used for T₁ - T₄ . The winding turns of T₁ and T₃ a 48:4:4 and the winding turns of T₂ is 30:5:5. The magnetizing inductances L_m1 = L_m3 =2.3 m H and L_m2 = L_m4 = 1.2 m H, and the output inductances L_o1 = L_o2 =1 2 μH . MOSFETs IRFP460 with V_DS =500 V, I_d,rms =20 A are used for switches S₁ - S₈ . The KCU30A30 fast recovery diodes with 300 V voltage rating and 30 A average current are used for D₁ - D₄ . Fast recovery diodes 30ETH06 are adopted for the clamped diodes D_a - D_d . The DC input capacitances C₁ - C₄ are 220 μ F. The flying capacitances C_f1 - C_f4 are 1 μ F. The output capacitance C_o is 4000 μ F. The measured waveforms of the PWM signals of S₁ - S₄ of the first circuit cell at full load are shown in Fig. 7 . Fig. 8 provides the measured gate voltages of S₁ and S₂ in the first circuit cell and those of S₅ and S₆ in the second circuit cell under full load conditions. S₅ and S₆ in the second circuit are clearly phase-shifted by one-fourth of the switching period with respect to S₁ and S₂ in the first circuit. Fig. 9 shows the measured results of the AC side voltages v_ab - v_df and the rectified voltages v_rect1 and v_rect2 at full load. Three voltage levels, V_in /2, 0, and - V_in /2, are generated on AC side voltages v_ab and v_de ; and two voltage levels V_in /4 and - V_in /4 are generated on voltages v_ac and v_df . Three voltage levels, V_in / n , V_in /(2 n ), and 0, are shown at the rectified voltages v_rect1 and v_rect2 . Fig. 10 gives the measured results of gate voltage, drain voltage, and switch current of S₁ at half and full load conditions under 800 V input voltage. Similarly, the measured gate voltage, drain voltage, and switch current of S₂ at 50% and 100% loads are given in Fig. 11 . Figs. 10 and 11 clearly show that S₁ and S₂ are all turned on under ZVS. S₃ and S₄ have the same switch current and voltage waveforms as S₂ and S₁ , respectively. Thus, S₃ and S₄ are also turned on under ZVS from 50% load to full load. Switches S₅ - S₈ in the second circuit cell have the same PWM signals as S₁ - S₄ in the first circuit cell. Thus, S₅ - S₈ are also turned on under ZVS from 50% to 100% load. Fig. 12 shows the measured waveforms of inductor currents i_Lr1 - i_Lr4 at full load. When v_ab is positive, inductor currents i_Lr1 and i_L2 both increase. Moreover, inductor currents i_Lr1 and i_L2 both decrease when v_ab is negative. Inductor currents i_Lr3 and i_Lr4 are phase-shifted by one-fourth of the switching period with respect to i_Lr1 and i_Lr2 . Fig. 13 shows the measured input capacitor voltages v_C1 - v_C4 and the flying capacitor voltages v_Cf1 - v_Cf4 at full load, and V_in =800 V . The average flying capacitor voltages v_Cf1 - v_Cf4 are equal to 200 V, and the average voltages v_C1 - v_C4 are equal to 400 V. The measured diode currents i_D1 - i_D4 at full load are shown in Fig. 14 . Fig. 15 (a) shows the output inductor current at full load without interleaved PWM operation. The measured ripple current is approximately 16 A. Fig. 15 (b) shows the measured output inductor currents i_Lo1 , i_Lo2 and the resultant output current i_Lo1 + i_Lo2 at full load. Two output inductor currents i_Lo1 and i_Lo2 are balanced and phase-shifted by one-half of the switching period. The ripple current on i_Lo1 + i_Lo2 is approximately 6 A in Fig. 15 (b). From Fig. 15 , the resultant output inductor current iLo1+iLo2 with interleaved operation has less current ripple than the output inductor current without interleaved operation. Fig. 16 presents the measured output ripple voltage with and without interleaved PWM operation under full load condition. The proposed converter with interleaved PWM operation has low output ripple voltage. The measured circuit efficiencies at different input voltage and load conditions are shown in Fig. 17 . A new three-level ZVS converter for high-input-voltage applications is presented with the features of ZVS turn-on for all switches from 50% load to full load, low voltage stress of power switches, and low voltage variation on output inductors. Two three-level converters are operated by interleaved PWM scheme to reduce the current rating of active and passive components and decrease the current ripple at the output side. In each converter, the voltage stress of power switches is clamped at V_in /2 by using three-level diode clamped topology. Two flying capacitors are adopted in each circuit cell to balance two input split capacitor voltages. The proposed three-level converter combines one half-bridge PWM converter and one three-level PWM converter to reduce the output inductor voltage variation. Therefore, the switching current in the output capacitor can be reduced compared with the switching capacitor current in the conventional three-level PWM converter. Finally, experiments are provided to verify the effectiveness of the proposed converter. Bor-Ren Lin received his B.S.E.E. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988 and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri-Columbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics and the Journal of Power Electronics. His main research interests include power-factor correction, multilevel converters, active power filters, and soft-switching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of Research Excellence Awards in 2004, 2005, 2007, and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, and the IEEE–Power Electronics and Drive Systems 2009 Conference. Yu-Bin Nian is currently working toward his M.S. in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His research interests include the design and analysis of power-factor correction techniques, switching-mode power supplies, and soft-switching converters.