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Analysis and Implementation of a New Three-Level Converter
Analysis and Implementation of a New Three-Level Converter
Journal of Power Electronics. 2014. May, 14(3): 478-487
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : December 04, 2013
  • Accepted : March 03, 2014
  • Published : May 28, 2014
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About the Authors
Bor-Ren Lin
Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan
linbr@yuntech.edu.tw
Yu-Bin Nian
Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan

Abstract
This study presents a new interleaved three-level zero-voltage switching (ZVS) converter for high-voltage and high-current applications. Two circuit cells are operated with interleaved pulse-width modulation in the proposed converter to reduce the current ripple at the input and output sides, as well as to decrease the current rating of output inductors for high-load-current applications. Each circuit cell includes one half-bridge converter and one three-level converter at the primary side. At the secondary side, the transformer windings of two converters are connected in series to reduce the size of the output inductor or switching current in the output capacitor. Based on the three-level circuit topology, the voltage stress of power switches is clamped at Vin /2. Thus, MOSFETs with 500 V voltage rating can be used at 800 V input voltage converters. The output capacitance of the power switch and the leakage inductance (or external inductance) are resonant at the transition interval. Therefore, power switches can be turned on under ZVS. Finally, experiments verify the effectiveness of the proposed converter.
Keywords
I. INTRODUCTION
High-efficiency DC/DC converters have been studied as power units in the mature stage of the telecommunication systems, server systems, data storage systems, medical instruments, and cloud power units. For three-phase power factor correction (PFC) converters, DC bus voltage may be equal to or greater than 500 V to 800V. Thus, MOSFETs with 500 or 650 V voltage stress cannot be used for DC/DC converters at the mature stage. Although high-voltage MOSFETs can be used in DC/DC converters, such as those with 900 V voltage stress, these units are expensive, and the high turn-on resistance of MOSFETs will reduce circuit efficiency. Three-level or multi-level converters/inverters [1] - [4] have been established by using low-voltage switch devices for high-voltage applications, such as reactive power compensators and high-power motor drives. For modern switching converters, high-efficiency converters are required to reduce circuit size and weight. Therefore, power losses should be reduced to meet this requirement. Soft-switching techniques [5] - [10] with duty cycle control have been developed in three-level converters to reduce the switching losses on power semiconductors. The output capacitance of power switches and the leakage inductance of transformers are resonant at the transition interval to achieve zero voltage switching (ZVS) on power switches. Three-level converters with variable frequency control [11] - [14] have been proposed to enhance circuit efficiency further. If the operating switching frequency is less than the series resonant frequency, the rectifier diodes at the secondary side can be turned off under zero current switching. However, the output ripple current of a three-level resonant converter is larger than that of a conventional three-level PWM converter. Therefore, high output capacitance is necessary for use at the output side.
A new three-level converter is presented for high-inputvoltage applications. The proposed converter includes two circuit cells, which are operated by an interleaved pulse-width modulation (PWM) to reduce the output ripple current and decrease the current stress of passive and active power components. Each circuit cell includes a half-bridge circuit and a three-level PWM circuit. In the proposed three-level converter, the voltage stress of power switches is limited to Vin /2. To reduce the ripple current on the output inductors or capacitor, the transformer secondary windings of two PWM circuits are connected in series at the low-voltage side to decrease the output inductor voltage variation. The flying capacitors are used in each circuit cell to balance input split capacitor voltages. Based on the resonant behavior of the output capacitances of MOSFETs and resonant inductance at the transition interval, all power switches can be turned on under ZVS. Finally, experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.
II. CIRCUIT CONFIGURATION AND OPERATION PRINCIPLE
Figs. 1 (a) and 1 (b) show the circuit configurations of the conventional half-bridge and full-bridge converters with 400V input voltage for normal single-phase switching mode power supplies for server power or data storage power units. In Fig. 1 (b), the phase-shift PWM scheme is adopted to regulate output voltage and achieve ZVS for all power switches within the desired load range. Normally, the ZVS condition of power switches at the leading leg is easier to be achieved than the power switches at the lagging leg. For three-phase switching mode power converters, the DC bus after the three-phase power factor corrector is normally controlled at 750 V to 800 V. To use MOSFETs instead of IGBTs for high switching operation, a three-level converter is given in Fig. 1 (c). Two clamped diodes and one flying capacitor are adopted to reduce the voltage stress of power switches at Vin /2 and to balance two input capacitor voltages. Two voltage levels, namely, Vin /(2n) and 0, are observed at the rectified voltage vrect . If the voltage variation across the output inductor is decreased, the current ripple on the output inductor can be decreased. Thus, one more half-bridge converter can be added to the conventional three-level DC converter to reduce the current ripple at output side. Fig. 2 (a) shows the circuit configuration of the proposed three-level converter. The proposed converter includes a conventional three-level converter [ Fig. 1 (c)] and a half-bridge converter [ Fig. 1 (a)] to reduce the voltage variation on the output inductor. The input voltage Vin is obtained from a three-phase AC/DC converter with PFC. C1 and C2 are input as split capacitances to obtain the equal voltages VC1 = VC2 = Vin /2. S1 - S4 are power MOSFETs with Vin /2 voltage stress. The average voltages of flying capacitors are VCf1 = VCf2 = Vin /4. Cr1 - Cr4 are the output capacitances of S1 - S4 , respectively. Lr1 and Lr2 are resonant inductances. Lo is the output inductance. D1 and D2 are rectifier diodes. T1 and T2 are the isolated transformers. Co and Ro denote output capacitance and load resistance, respectively. In the proposed circuit, a three-level converter and a half-bridge converter are used to achieve ZVS turn-on for all switches and to reduce the output inductance or output capacitance. Components Cf1 , Cf2 , S3 , S4 , T2 , and Lr2 are operated as an uncontrolled half-bridge converter with 50% duty cycle. Two voltage levels, Vin /4 and - Vin /4, are generated on vac . Components C1 , C2 , Da , Db , Cf1 , Cf2 , S1 - S4 , Lr1 , and T1 are operated as the conventional three-level converter. Three voltage levels, namely, Vin /2, 0, and - Vin /2, are generated on vab . Two voltage levels, Vin /(2 n1 )+ Vin /(4 n2 ) and Vin /(4 n2 ), can be observed on the rectified voltage vrect . Thus, low ripple current or switching current on the output inductor can be achieved because of the low voltage across the output inductor. The output capacitances of S1 - S4 and the resonant inductance (or transformer leakage inductance) are resonant at the transition interval. Therefore, S1 - S4 can be turned on under ZVS. To reduce the current ripple further at the input and output sides, as well as to reduce the current rating of output inductor for high load current application, an interleaved three-level converter is shown in Fig. 2 (b). The interleaved PWM scheme is adopted to generate eight gate signals of S1 - S4 . The input and output ripple currents of two converters can partially cancel each other. Therefore, the input and output capacitances and output inductances can be reduced.
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Circuit configurations. (a) Conventional PWM half-bridge converter. (b) Conventional phase-shift full-bridge converter. (c) Conventional three-level converter.
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Circuit configuration. (a) New three-level converter. (b) Adopted interleaved three-level converter.
The system analysis of the proposed converter is based on the following assumptions: (1) VCf1 = VCf2 = VCf3 = VCf4 = Vin /4; (2) VC1 = VC2 = VC3 = VC4 = Vin /2; (3) Cr1 = Cr2 =…= Cr7 = Cr8 = Cr ; (4) S1 - S8 , D1 - D4 , and Da - Dd are ideal; (5) turn ratio of T1 and T3 is n 1 = n 3 = n and that of T2 and T4 is n 2 = n 4 = n /2; and (6) the energy stored in the resonant inductances is greater than that stored in the resonant capacitances, such that the ZVS turn-on of all switches can be achieved. Based on the on/off states of S1 - S8 , Da - Dd , and D1 - D4 , 10 operation modes exist in each three-level converter during one switching cycle. The key waveforms of each three-level converter during one switching cycle are given in Fig. 3 . Fig. 4 shows the key waveforms of the proposed interleaved three-level converter. Two output inductor currents partially cancelled each other. Two three-level converters have the same operation modes. Thus, only the operation modes of converter 1 are discussed to simplify the system analysis. Three-level converter 1 has 10 operation modes ( Fig. 5 ). Prior to t0 , S1 , S2 D1 , and D2 are conducting. Inductor currents iLr1 and iLr2 are increasing.
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Main waveforms of three-level converter 1.
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Key waveforms of the proposed interleaved three-level converter.
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Operation modes of the proposed converter during one switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7. (h) Mode 8. (i) Mode 9. (j) Mode 10.
Mode 1 [t0≤t<t1, Fig. 5(a)] : At t0 , iD2 is decreased to zero current, such that D2 is off. S1 and S2 are still turned on, such that vab = Vin /2, vac = vCf1 = Vin /4, vrect1 Vin /(2 n1 )+ Vin /(4 n2 )= Vin / n , and vLo1 = Vin / n - Vo >0. The output inductor current iLo1 and the primary currents iLr1 and iLr2 increase in this mode. Power is transferred from input voltage source Vin /2 to output load Ro .
Mode 2 [t1≤t<t2, Fig. 5(b)] : At t1 , S1 is turned off. Given that iLr1 >0 and iLr2 >0, Cr1 and Cr4 are charged and discharged in this mode. If the energy stored in Lr1 and Lo1 is greater than the energy stored in Cr1 and Cr4 , then Cr4 can be discharged to zero voltage. The ZVS turn-on condition of S4 can be expressed as
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This mode ends at t2 when vCr1 = Vin /2 and vCr4 = 0 .
Mode 3 [t2≤t<t3, Fig. 5(c)] : At t2 , vCr1 = Vin /2, vCr4 = 0 , and Da are conducting. Capacitor voltage vC2 = vCf1 + vCf2 = Vin /2. Given that iLr1 >0, the anti-parallel diode of S4 is conducting. Thus, S4 can be turned on at this moment to achieve ZVS. In this mode, the primary side voltage vab =0 and vac = vCf1 = Vin /4, and the secondary side voltage vrect1 = Vin /(2 n ). The output inductor voltage vLo1 = Vin /(2 n )- Vo <0, such that that the output inductor current iLo1 decreases in this mode.
Mode 4 [t3≤t<t4, Fig. 5(d)] : At t3 , S2 is turned off. Given that iLr1 >0 and iLr2 >0, Cr2 , and Cr3 are charged and discharged, respectively. If the energy stored in Lr1 , Lr2 , and Lo1 is greater than the energy stored in Cr2 and Cr3 , then Cr3 can be discharged to zero voltage. Thus, the ZVS turn-on condition of S3 can be obtained in (2).
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Mode 5 [t4≤t<t5, Fig. 5(e)] : At time t4 , vCr2 = Vin /2, and vCr3 =0. Given that iLr1 >0 and iLr2 >0, the anti-parallel diode of S3 is conducting. S3 can be turned on at this moment under ZVS. D1 and D2 are conducting to commutate the inductor current iLo1 . The secondary side voltage vrect1 =0, and the inductor current iLo1 is decreasing. The primary inductor currents iLr1 and iLr2 decrease with the slopes - Vin /(2 Lr1 ) and - Vin /(4 Lr2 ), respectively. The slopes of the diode currents iD1 and iD2 are given by
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Based on (3), the relationship of Lr1 and Lr2 can be described as Lr1 =4 Lr2 . At t5 , iD1 is decreased to zero current. The current variation on inductor Lr1 is Δ iLr1 = iLr1 ( t5 ) - iLr1 ( t4 ) ≈ - Io /(2 n ) - Io /(2n) = - Io / n . The time interval in this mode is given as
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In this mode, S3 , S4 , D1 , and D2 are conducting, and the rectified voltage vrect1 =0. No power is transferred from input voltage source Vin to output load Ro . The duty loss in this mode can be expressed as
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Mode 6 [t5≤t<t6, Fig. 5(f)] : At t5 , iD1 =0. S3 and S4 are conducting. The primary side AC voltages vab =- Vin /2 and vac =- vCf2 =- Vin /4, and the output inductor voltage vLo1 = Vin / n - Vo >0. The primary side inductor currents iLr1 and iL2 both decrease, whereas the output inductor current iLo1 increases in this mode.
Mode 7 [t6≤t<t7, Fig. 5(g)] : At t6 , S4 is turned off. Given that iLr1 <0 and iLr2 <0, Cr1 and Cr4 are discharged and charged, respectively. The ZVS turn-on condition of S1 can be expressed as
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At t7 , Cr1 is discharged to zero voltage.
Mode 8 [t7≤t<t8, Fig. 5(h)] : At t7 , vCr1 = 0 , and vCr4 = Vin /2. Given that iLr1 <0, the anti-parallel diode of S1 is conducting. S1 can be turned on at this moment under ZVS. Db is conducting, and the AC terminal voltages vab =0 and vac =- vCf2 =- Vin /4. The primary inductor currents iLr1 and iLr2 are both decreasing. The rectified voltage vrect1 = Vin /(2 n ), and the output inductor voltage vLo1 = Vin /(2 n )- Vo <0, such that iLo1 decreases in this mode.
Mode 9 [t8≤t<t9, Fig. 5(i)] : At t8 , S3 is turned off. Given that iLr1 <0 and iLr2 <0, Cr2 and Cr3 are discharged and charged, respectively. Similar to (2), the ZVS turn-on condition of S2 can be obtained as
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Mode 10 [t9≤t<t0+Ts, Fig. 5(j)] : At t9 , Cr2 is discharged to zero voltage. Given that iLr1 ( t9 )+ iLr2 ( t9 )<0, the anti-parallel diode of S2 is conducting. S2 can be turned on at this moment under ZVS. D1 and D2 are conducting to commutate the load inductor current iLo1 . In this mode, S1 , S2 , D1 , and D2 are conducting. Thus, the rectified voltage vrect1 =0 and the inductor voltage vLo1 =- Vo . No power is transferred from input voltage source Vin to output load Ro . Thus, the duty loss in this mode is given as
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At t0 + Ts , iD2 is decreased to zero current. The circuit operations of the proposed converter in a switching period are then completed.
III. CIRCUIT CHARACTERISTICS
In the above discussions, the charge and discharge times of Cr1 Cr4 in modes 2, 4, 7, and 9 are significantly less than the other time intervals. Thus, these modes can be neglected in the discussion of circuit characteristics. From modes 3 and 8 in Fig. 5 , the spite capacitor voltages vC1 vC4 can be obtained as vC1 = vC2 = vC3 = vC4 = Vin /2. Applying the volt-second balance to Lr2 and T2 in steady state, the average capacitor voltages VCf1 VCf4 can be derived as
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Based on the volt-second balance on output inductors Lo1 and Lo2 , the output voltage Vo can be derived as
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where Vf is the voltage drop on diodes D1 . D4 ; and d is the duty ratio of the AC side voltages vab , vac , vde , and vdf . The ripple currents of Lo1 and Lo2 are expressed in (11).
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where r is the current ripple factor of output inductors. The maximum output inductor currents at steady state are expressed in (12).
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In modes 1 and 6, the magnetizing ripple currents Δ iLm1 iLm4 can be expressed in (13) and (14).
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where Lm1 = Lm3 , and Lm2 = Lm1 . The average diode currents iD1,av iD4,av and the diode voltage stresses vD1,stress vD4,stress are given in (15) and (16), respectively.
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If the ripple currents of S1 - S8 can be ignored, the root-mean-square ( rms ) currents and the voltage stress of S1 - S8 are given in (17)-(19).
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In mode 2, iLr1 ( t1 ) can be expressed as
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In mode 4, the inductor currents iLr1 ( t3 ) and iLr2 ( t3 ) can be expressed as
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Based on (1), (6), and (20), the necessary resonant inductance Lr1 for ZVS turn-on of S1 and S4 is expressed in (23).
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From (2), (7), (21), and (22), the necessary resonant inductance Lr2 for ZVS turn-on of S2 and S3 is given in (24).
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Given that the switch currents iS5 - iS8 are similar to i S1 -i S4 in steady state, the necessary resonant inductances Lr3 and Lr4 are equal to Lr1 and Lr2 , respectively, to achieve ZVS conditions of S5 - S8 .
IV. EXPERIMENTAL RESULTS
A laboratory prototype shown in Fig. 6 is implemented to verify the effectiveness of the proposed converter. The electrical specifications of the proposed converter are Vin =750 V.800 V, Vo =48 V, Io =40 A, and fs =100 k Hz. The resonant inductances in this prototype are Lr1 = Lr3 =48 μ H and Lr2 = Lr4 =12 μ H. The magnetic core TDK EER-40C is used for T1 - T4 . The winding turns of T1 and T3 a 48:4:4 and the winding turns of T2 is 30:5:5. The magnetizing inductances Lm1 = Lm3 =2.3 m H and Lm2 = Lm4 = 1.2 m H, and the output inductances Lo1 = Lo2 =1 2 μH . MOSFETs IRFP460 with VDS =500 V, Id,rms =20 A are used for switches S1 - S8 . The KCU30A30 fast recovery diodes with 300 V voltage rating and 30 A average current are used for D1 - D4 . Fast recovery diodes 30ETH06 are adopted for the clamped diodes Da - Dd . The DC input capacitances C1 - C4 are 220 μ F. The flying capacitances Cf1 - Cf4 are 1 μ F. The output capacitance Co is 4000 μ F. The measured waveforms of the PWM signals of S1 - S4 of the first circuit cell at full load are shown in Fig. 7 . Fig. 8 provides the measured gate voltages of S1 and S2 in the first circuit cell and those of S5 and S6 in the second circuit cell under full load conditions. S5 and S6 in the second circuit are clearly phase-shifted by one-fourth of the switching period with respect to S1 and S2 in the first circuit. Fig. 9 shows the measured results of the AC side voltages vab - vdf and the rectified voltages vrect1 and vrect2 at full load. Three voltage levels, Vin /2, 0, and - Vin /2, are generated on AC side voltages vab and vde ; and two voltage levels Vin /4 and - Vin /4 are generated on voltages vac and vdf . Three voltage levels, Vin / n , Vin /(2 n ), and 0, are shown at the rectified voltages vrect1 and vrect2 . Fig. 10 gives the measured results of gate voltage, drain voltage, and switch current of S1 at half and full load conditions under 800 V input voltage. Similarly, the measured gate voltage, drain voltage, and switch current of S2 at 50% and 100% loads are given in Fig. 11 . Figs. 10 and 11 clearly show that S1 and S2 are all turned on under ZVS. S3 and S4 have the same switch current and voltage waveforms as S2 and S1 , respectively. Thus, S3 and S4 are also turned on under ZVS from 50% load to full load. Switches S5 - S8 in the second circuit cell have the same PWM signals as S1 - S4 in the first circuit cell. Thus, S5 - S8 are also turned on under ZVS from 50% to 100% load. Fig. 12 shows the measured waveforms of inductor currents iLr1 - iLr4 at full load. When vab is positive, inductor currents iLr1 and iL2 both increase. Moreover, inductor currents iLr1 and iL2 both decrease when vab is negative. Inductor currents iLr3 and iLr4 are phase-shifted by one-fourth of the switching period with respect to iLr1 and iLr2 . Fig. 13 shows the measured input capacitor voltages vC1 - vC4 and the flying capacitor voltages vCf1 - vCf4 at full load, and Vin =800 V . The average flying capacitor voltages vCf1 - vCf4 are equal to 200 V, and the average voltages vC1 - vC4 are equal to 400 V. The measured diode currents iD1 - iD4 at full load are shown in Fig. 14 . Fig. 15 (a) shows the output inductor current at full load without interleaved PWM operation. The measured ripple current is approximately 16 A. Fig. 15 (b) shows the measured output inductor currents iLo1 , iLo2 and the resultant output current iLo1 + iLo2 at full load. Two output inductor currents iLo1 and iLo2 are balanced and phase-shifted by one-half of the switching period. The ripple current on iLo1 + iLo2 is approximately 6 A in Fig. 15 (b). From Fig. 15 , the resultant output inductor current iLo1+iLo2 with interleaved operation has less current ripple than the output inductor current without interleaved operation. Fig. 16 presents the measured output ripple voltage with and without interleaved PWM operation under full load condition. The proposed converter with interleaved PWM operation has low output ripple voltage. The measured circuit efficiencies at different input voltage and load conditions are shown in Fig. 17 .
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Photograph of the prototype circuit.
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Measured results of gate voltages of S1-S4 at full load.
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Measured results of gate voltages of S1, S2, S5, and S6 at full load.
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Measured results of the AC side voltages vabvdf and the rectified voltages vrect1 and vrect2 at full load [vabvdf : 500V/div; vrect1, vrect2100 V/div; time 2 μs/div].
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Measured waveforms of gate voltage, drain voltage and switch current of S1 at (a) 50% load and (b) full load.
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Measured waveforms of gate voltage, drain voltage, and switch current of S2 at (a) 50% load and (b) full load.
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Measured waveforms of inductor currents iLr1-iLr4 at full load.
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Measured input capacitor voltages vC1-vC4 and flying capacitor voltages vCf1-vCf4 at full load.
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Measured diode currents iD1-iD4 at full load.
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Measured waveforms of output inductor currents at full load (a) without interleaved operation and (b) with interleaved operation.
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Measured output ripple voltage under full load (a) without interleaved operation and (b) with interleaved operation.
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Measured circuit efficiencies at different input voltage and load conditions.
V. CONCLUSIONS
A new three-level ZVS converter for high-input-voltage applications is presented with the features of ZVS turn-on for all switches from 50% load to full load, low voltage stress of power switches, and low voltage variation on output inductors. Two three-level converters are operated by interleaved PWM scheme to reduce the current rating of active and passive components and decrease the current ripple at the output side. In each converter, the voltage stress of power switches is clamped at Vin /2 by using three-level diode clamped topology. Two flying capacitors are adopted in each circuit cell to balance two input split capacitor voltages. The proposed three-level converter combines one half-bridge PWM converter and one three-level PWM converter to reduce the output inductor voltage variation. Therefore, the switching current in the output capacitor can be reduced compared with the switching capacitor current in the conventional three-level PWM converter. Finally, experiments are provided to verify the effectiveness of the proposed converter.
Acknowledgements
This project is partly supported by the National Science Council of Taiwan under Grant NSC 102-2221-E-224-022-MY3.
BIO
Bor-Ren Lin received his B.S.E.E. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988 and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri-Columbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics and the Journal of Power Electronics. His main research interests include power-factor correction, multilevel converters, active power filters, and soft-switching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of Research Excellence Awards in 2004, 2005, 2007, and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, and the IEEE–Power Electronics and Drive Systems 2009 Conference.
Yu-Bin Nian is currently working toward his M.S. in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His research interests include the design and analysis of power-factor correction techniques, switching-mode power supplies, and soft-switching converters.
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