This study presents a new interleaved threelevel zerovoltage switching (ZVS) converter for highvoltage and highcurrent applications. Two circuit cells are operated with interleaved pulsewidth modulation in the proposed converter to reduce the current ripple at the input and output sides, as well as to decrease the current rating of output inductors for highloadcurrent applications. Each circuit cell includes one halfbridge converter and one threelevel converter at the primary side. At the secondary side, the transformer windings of two converters are connected in series to reduce the size of the output inductor or switching current in the output capacitor. Based on the threelevel circuit topology, the voltage stress of power switches is clamped at
V_{in}
/2. Thus, MOSFETs with 500 V voltage rating can be used at 800 V input voltage converters. The output capacitance of the power switch and the leakage inductance (or external inductance) are resonant at the transition interval. Therefore, power switches can be turned on under ZVS. Finally, experiments verify the effectiveness of the proposed converter.
I. INTRODUCTION
Highefficiency DC/DC converters have been studied as power units in the mature stage of the telecommunication systems, server systems, data storage systems, medical instruments, and cloud power units. For threephase power factor correction (PFC) converters, DC bus voltage may be equal to or greater than 500 V to 800V. Thus, MOSFETs with 500 or 650 V voltage stress cannot be used for DC/DC converters at the mature stage. Although highvoltage MOSFETs can be used in DC/DC converters, such as those with 900 V voltage stress, these units are expensive, and the high turnon resistance of MOSFETs will reduce circuit efficiency. Threelevel or multilevel converters/inverters
[1]

[4]
have been established by using lowvoltage switch devices for highvoltage applications, such as reactive power compensators and highpower motor drives. For modern switching converters, highefficiency converters are required to reduce circuit size and weight. Therefore, power losses should be reduced to meet this requirement. Softswitching techniques
[5]

[10]
with duty cycle control have been developed in threelevel converters to reduce the switching losses on power semiconductors. The output capacitance of power switches and the leakage inductance of transformers are resonant at the transition interval to achieve zero voltage switching (ZVS) on power switches. Threelevel converters with variable frequency control
[11]

[14]
have been proposed to enhance circuit efficiency further. If the operating switching frequency is less than the series resonant frequency, the rectifier diodes at the secondary side can be turned off under zero current switching. However, the output ripple current of a threelevel resonant converter is larger than that of a conventional threelevel PWM converter. Therefore, high output capacitance is necessary for use at the output side.
A new threelevel converter is presented for highinputvoltage applications. The proposed converter includes two circuit cells, which are operated by an interleaved pulsewidth modulation (PWM) to reduce the output ripple current and decrease the current stress of passive and active power components. Each circuit cell includes a halfbridge circuit and a threelevel PWM circuit. In the proposed threelevel converter, the voltage stress of power switches is limited to
V_{in}
/2. To reduce the ripple current on the output inductors or capacitor, the transformer secondary windings of two PWM circuits are connected in series at the lowvoltage side to decrease the output inductor voltage variation. The flying capacitors are used in each circuit cell to balance input split capacitor voltages. Based on the resonant behavior of the output capacitances of MOSFETs and resonant inductance at the transition interval, all power switches can be turned on under ZVS. Finally, experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.
II. CIRCUIT CONFIGURATION AND OPERATION PRINCIPLE
Figs. 1
(a) and
1
(b) show the circuit configurations of the conventional halfbridge and fullbridge converters with 400V input voltage for normal singlephase switching mode power supplies for server power or data storage power units. In
Fig. 1
(b), the phaseshift PWM scheme is adopted to regulate output voltage and achieve ZVS for all power switches within the desired load range. Normally, the ZVS condition of power switches at the leading leg is easier to be achieved than the power switches at the lagging leg. For threephase switching mode power converters, the DC bus after the threephase power factor corrector is normally controlled at 750 V to 800 V. To use MOSFETs instead of IGBTs for high switching operation, a threelevel converter is given in
Fig. 1
(c). Two clamped diodes and one flying capacitor are adopted to reduce the voltage stress of power switches at
V_{in}
/2 and to balance two input capacitor voltages. Two voltage levels, namely,
V_{in}
/(2n) and 0, are observed at the rectified voltage
v_{rect}
. If the voltage variation across the output inductor is decreased, the current ripple on the output inductor can be decreased. Thus, one more halfbridge converter can be added to the conventional threelevel DC converter to reduce the current ripple at output side.
Fig. 2
(a) shows the circuit configuration of the proposed threelevel converter. The proposed converter includes a conventional threelevel converter [
Fig. 1
(c)] and a halfbridge converter [
Fig. 1
(a)] to reduce the voltage variation on the output inductor. The input voltage
V_{in}
is obtained from a threephase AC/DC converter with PFC.
C_{1}
and
C_{2}
are input as split capacitances to obtain the equal voltages
V_{C1}
=
V_{C2}
=
V_{in}
/2.
S_{1}

S_{4}
are power MOSFETs with
V_{in}
/2 voltage stress. The average voltages of flying capacitors are
V_{Cf1}
=
V_{Cf2}
=
V_{in}
/4.
C_{r1}

C_{r4}
are the output capacitances of
S_{1}

S_{4}
, respectively.
L_{r1}
and
L_{r2}
are resonant inductances.
L_{o}
is the output inductance.
D_{1}
and
D_{2}
are rectifier diodes.
T_{1}
and
T_{2}
are the isolated transformers.
C_{o}
and
R_{o}
denote output capacitance and load resistance, respectively. In the proposed circuit, a threelevel converter and a halfbridge converter are used to achieve ZVS turnon for all switches and to reduce the output inductance or output capacitance. Components
C_{f1}
,
C_{f2}
,
S_{3}
,
S_{4}
,
T_{2}
, and
L_{r2}
are operated as an uncontrolled halfbridge converter with 50% duty cycle. Two voltage levels,
V_{in}
/4 and 
V_{in}
/4, are generated on
v_{ac}
. Components
C_{1}
,
C_{2}
,
D_{a}
,
D_{b}
,
C_{f1}
,
C_{f2}
,
S_{1}

S_{4}
,
L_{r1}
, and
T_{1}
are operated as the conventional threelevel converter. Three voltage levels, namely,
V_{in}
/2, 0, and 
V_{in}
/2, are generated on
v_{ab}
. Two voltage levels,
V_{in}
/(2
n_{1}
)+
V_{in}
/(4
n_{2}
) and
V_{in}
/(4
n_{2}
), can be observed on the rectified voltage
v_{rect}
. Thus, low ripple current or switching current on the output inductor can be achieved because of the low voltage across the output inductor. The output capacitances of
S_{1}

S_{4}
and the resonant inductance (or transformer leakage inductance) are resonant at the transition interval. Therefore,
S_{1}

S_{4}
can be turned on under ZVS. To reduce the current ripple further at the input and output sides, as well as to reduce the current rating of output inductor for high load current application, an interleaved threelevel converter is shown in
Fig. 2
(b). The interleaved PWM scheme is adopted to generate eight gate signals of
S_{1}

S_{4}
. The input and output ripple currents of two converters can partially cancel each other. Therefore, the input and output capacitances and output inductances can be reduced.
Circuit configurations. (a) Conventional PWM halfbridge converter. (b) Conventional phaseshift fullbridge converter. (c) Conventional threelevel converter.
Circuit configuration. (a) New threelevel converter. (b) Adopted interleaved threelevel converter.
The system analysis of the proposed converter is based on the following assumptions: (1)
V_{Cf1}
=
V_{Cf2}
=
V_{Cf3}
=
V_{Cf4}
=
V_{in}
/4; (2)
V_{C1}
=
V_{C2}
=
V_{C3}
=
V_{C4}
=
V_{in}
/2; (3)
C_{r1}
=
C_{r2}
=…=
C_{r7}
=
C_{r8}
=
C_{r}
; (4)
S_{1}

S_{8}
,
D_{1}

D_{4}
, and
D_{a}

D_{d}
are ideal; (5) turn ratio of
T_{1}
and
T_{3}
is
n
_{1}
=
n
_{3}
=
n
and that of
T_{2}
and
T_{4}
is
n
_{2}
=
n
_{4}
=
n
/2; and (6) the energy stored in the resonant inductances is greater than that stored in the resonant capacitances, such that the ZVS turnon of all switches can be achieved. Based on the on/off states of
S_{1}

S_{8}
,
D_{a}

D_{d}
, and
D_{1}

D_{4}
, 10 operation modes exist in each threelevel converter during one switching cycle. The key waveforms of each threelevel converter during one switching cycle are given in
Fig. 3
.
Fig. 4
shows the key waveforms of the proposed interleaved threelevel converter. Two output inductor currents partially cancelled each other. Two threelevel converters have the same operation modes. Thus, only the operation modes of converter 1 are discussed to simplify the system analysis. Threelevel converter 1 has 10 operation modes (
Fig. 5
). Prior to
t_{0}
,
S_{1}
,
S_{2}
D_{1}
, and
D_{2}
are conducting. Inductor currents
i_{Lr1}
and
i_{Lr2}
are increasing.
Main waveforms of threelevel converter 1.
Key waveforms of the proposed interleaved threelevel converter.
Operation modes of the proposed converter during one switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7. (h) Mode 8. (i) Mode 9. (j) Mode 10.
Mode 1 [t_{0}≤t＜t_{1}, Fig. 5(a)]
: At
t_{0}
,
i_{D2}
is decreased to zero current, such that
D_{2}
is off.
S_{1}
and
S_{2}
are still turned on, such that
v_{ab}
=
V_{in}
/2,
v_{ac}
=
v_{Cf1}
=
V_{in}
/4,
v_{rect1}
≈
V_{in}
/(2
n_{1}
)+
V_{in}
/(4
n_{2}
)=
V_{in}
/
n
, and
v_{Lo1}
=
V_{in}
/
n

V_{o}
＞0. The output inductor current
i_{Lo1}
and the primary currents
i_{Lr1}
and
i_{Lr2}
increase in this mode. Power is transferred from input voltage source
V_{in}
/2 to output load
R_{o}
.
Mode 2 [t_{1}≤t＜t_{2}, Fig. 5(b)]
: At
t_{1}
,
S_{1}
is turned off. Given that
i_{Lr1}
＞0 and
i_{Lr2}
＞0,
C_{r1}
and
C_{r4}
are charged and discharged in this mode. If the energy stored in
L_{r1}
and
L_{o1}
is greater than the energy stored in
C_{r1}
and
C_{r4}
, then
C_{r4}
can be discharged to zero voltage. The ZVS turnon condition of
S_{4}
can be expressed as
This mode ends at
t_{2}
when
v_{Cr1}
=
V_{in}
/2 and
v_{Cr4}
=
0
.
Mode 3 [t_{2}≤t＜t_{3}, Fig. 5(c)]
: At
t_{2}
,
v_{Cr1}
=
V_{in}
/2,
v_{Cr4}
=
0
, and
D_{a}
are conducting. Capacitor voltage
v_{C2}
=
v_{Cf1}
+
v_{Cf2}
=
V_{in}
/2. Given that
i_{Lr1}
＞0, the antiparallel diode of
S_{4}
is conducting. Thus,
S_{4}
can be turned on at this moment to achieve ZVS. In this mode, the primary side voltage
v_{ab}
=0 and
v_{ac}
=
v_{Cf1}
=
V_{in}
/4, and the secondary side voltage
v_{rect1}
=
V_{in}
/(2
n
). The output inductor voltage
v_{Lo1}
=
V_{in}
/(2
n
)
V_{o}
＜0, such that that the output inductor current
i_{Lo1}
decreases in this mode.
Mode 4 [t_{3}≤t＜t_{4}, Fig. 5(d)]
: At
t_{3}
,
S_{2}
is turned off. Given that
i_{Lr1}
＞0 and
i_{Lr2}
＞0,
C_{r2}
, and
C_{r3}
are charged and discharged, respectively. If the energy stored in
L_{r1}
,
L_{r2}
, and
L_{o1}
is greater than the energy stored in
C_{r2}
and
C_{r3}
, then
C_{r3}
can be discharged to zero voltage. Thus, the ZVS turnon condition of
S_{3}
can be obtained in (2).
Mode 5 [t_{4}≤t＜t_{5}, Fig. 5(e)]
: At time
t_{4}
,
v_{Cr2}
=
V_{in}
/2, and
v_{Cr3}
=0. Given that
i_{Lr1}
＞0 and
i_{Lr2}
＞0, the antiparallel diode of
S_{3}
is conducting.
S_{3}
can be turned on at this moment under ZVS.
D_{1}
and
D_{2}
are conducting to commutate the inductor current
i_{Lo1}
. The secondary side voltage
v_{rect1}
=0, and the inductor current
i_{Lo1}
is decreasing. The primary inductor currents
i_{Lr1}
and
i_{Lr2}
decrease with the slopes 
V_{in}
/(2
L_{r1}
) and 
V_{in}
/(4
L_{r2}
), respectively. The slopes of the diode currents
i_{D1}
and
i_{D2}
are given by
Based on (3), the relationship of
L_{r1}
and
L_{r2}
can be described as
L_{r1}
=4
L_{r2}
. At
t_{5}
,
i_{D1}
is decreased to zero current. The current variation on inductor
L_{r1}
is Δ
i_{Lr1}
=
i_{Lr1}
(
t_{5}
) 
i_{Lr1}
(
t_{4}
) ≈ 
I_{o}
/(2
n
) 
I_{o}
/(2n) = 
I_{o}
/
n
. The time interval in this mode is given as
In this mode,
S_{3}
,
S_{4}
,
D_{1}
, and
D_{2}
are conducting, and the rectified voltage
v_{rect1}
=0. No power is transferred from input voltage source
V_{in}
to output load
R_{o}
. The duty loss in this mode can be expressed as
Mode 6 [t_{5}≤t＜t_{6}, Fig. 5(f)]
: At
t_{5}
,
i_{D1}
=0.
S_{3}
and
S_{4}
are conducting. The primary side AC voltages
v_{ab}
=
V_{in}
/2 and
v_{ac}
=
v_{Cf2}
=
V_{in}
/4, and the output inductor voltage
v_{Lo1}
=
V_{in}
/
n

V_{o}
＞0. The primary side inductor currents
i_{Lr1}
and
i_{L2}
both decrease, whereas the output inductor current
i_{Lo1}
increases in this mode.
Mode 7 [t_{6}≤t＜t_{7}, Fig. 5(g)]
: At
t_{6}
,
S_{4}
is turned off. Given that
i_{Lr1}
＜0 and
i_{Lr2}
＜0,
C_{r1}
and
C_{r4}
are discharged and charged, respectively. The ZVS turnon condition of
S_{1}
can be expressed as
At
t_{7}
,
C_{r1}
is discharged to zero voltage.
Mode 8 [t_{7}≤t＜t_{8}, Fig. 5(h)]
: At
t_{7}
,
v_{Cr1}
=
0
, and
v_{Cr4}
=
V_{in}
/2. Given that
i_{Lr1}
＜0, the antiparallel diode of
S_{1}
is conducting.
S_{1}
can be turned on at this moment under ZVS.
D_{b}
is conducting, and the AC terminal voltages
v_{ab}
=0 and
v_{ac}
=
v_{Cf2}
=
V_{in}
/4. The primary inductor currents
i_{Lr1}
and
i_{Lr2}
are both decreasing. The rectified voltage
v_{rect1}
=
V_{in}
/(2
n
), and the output inductor voltage
v_{Lo1}
=
V_{in}
/(2
n
)
V_{o}
＜0, such that
i_{Lo1}
decreases in this mode.
Mode 9 [t_{8}≤t＜t_{9}, Fig. 5(i)]
: At
t_{8}
,
S_{3}
is turned off. Given that
i_{Lr1}
＜0 and
i_{Lr2}
＜0,
C_{r2}
and
C_{r3}
are discharged and charged, respectively. Similar to (2), the ZVS turnon condition of
S_{2}
can be obtained as
Mode 10 [t_{9}≤t＜t_{0}+T_{s}, Fig. 5(j)]
: At
t_{9}
,
C_{r2}
is discharged to zero voltage. Given that
i_{Lr1}
(
t_{9}
)+
i_{Lr2}
(
t_{9}
)＜0, the antiparallel diode of
S_{2}
is conducting.
S_{2}
can be turned on at this moment under ZVS.
D_{1}
and
D_{2}
are conducting to commutate the load inductor current
i_{Lo1}
. In this mode,
S_{1}
,
S_{2}
,
D_{1}
, and
D_{2}
are conducting. Thus, the rectified voltage
v_{rect1}
=0 and the inductor voltage
v_{Lo1}
=
V_{o}
. No power is transferred from input voltage source
V_{in}
to output load
R_{o}
. Thus, the duty loss in this mode is given as
At
t_{0}
+
T_{s}
,
i_{D2}
is decreased to zero current. The circuit operations of the proposed converter in a switching period are then completed.
III. CIRCUIT CHARACTERISTICS
In the above discussions, the charge and discharge times of
C_{r1}
–
C_{r4}
in modes 2, 4, 7, and 9 are significantly less than the other time intervals. Thus, these modes can be neglected in the discussion of circuit characteristics. From modes 3 and 8 in
Fig. 5
, the spite capacitor voltages
v_{C1}
–
v_{C4}
can be obtained as
v_{C1}
=
v_{C2}
=
v_{C3}
=
v_{C4}
=
V_{in}
/2. Applying the voltsecond balance to
L_{r2}
and
T_{2}
in steady state, the average capacitor voltages
V_{Cf1}
–
V_{Cf4}
can be derived as
Based on the voltsecond balance on output inductors
L_{o1}
and
L_{o2}
, the output voltage
V_{o}
can be derived as
where
V_{f}
is the voltage drop on diodes
D_{1}
.
D_{4}
; and
d
is the duty ratio of the AC side voltages
v_{ab}
,
v_{ac}
,
v_{de}
, and
v_{df}
. The ripple currents of
L_{o1}
and
L_{o2}
are expressed in (11).
where
r
is the current ripple factor of output inductors. The maximum output inductor currents at steady state are expressed in (12).
In modes 1 and 6, the magnetizing ripple currents Δ
i_{Lm1}
Δ
i_{Lm4}
can be expressed in (13) and (14).
where
L_{m1}
=
L_{m3}
, and
L_{m2}
=
L_{m1}
. The average diode currents
i_{D1,av}
–
i_{D4,av}
and the diode voltage stresses
v_{D1,stress}
–
v_{D4,stress}
are given in (15) and (16), respectively.
If the ripple currents of
S_{1}

S_{8}
can be ignored, the rootmeansquare (
rms
) currents and the voltage stress of
S_{1}

S_{8}
are given in (17)(19).
In mode 2,
i_{Lr1}
(
t_{1}
) can be expressed as
In mode 4, the inductor currents
i_{Lr1}
(
t_{3}
) and
i_{Lr2}
(
t_{3}
) can be expressed as
Based on (1), (6), and (20), the necessary resonant inductance
L_{r1}
for ZVS turnon of
S_{1}
and
S_{4}
is expressed in (23).
From (2), (7), (21), and (22), the necessary resonant inductance
L_{r2}
for ZVS turnon of
S_{2}
and
S_{3}
is given in (24).
Given that the switch currents
i_{S5}

i_{S8}
are similar to i
_{S1}
i
_{S4}
in steady state, the necessary resonant inductances
L_{r3}
and
L_{r4}
are equal to
L_{r1}
and
L_{r2}
, respectively, to achieve ZVS conditions of
S_{5}

S_{8}
.
IV. EXPERIMENTAL RESULTS
A laboratory prototype shown in
Fig. 6
is implemented to verify the effectiveness of the proposed converter. The electrical specifications of the proposed converter are
V_{in}
=750 V.800 V,
V_{o}
=48 V,
I_{o}
=40 A, and
f_{s}
=100
k
Hz. The resonant inductances in this prototype are
L_{r1}
=
L_{r3}
=48
μ
H and
L_{r2}
=
L_{r4}
=12
μ
H. The magnetic core TDK EER40C is used for
T_{1}

T_{4}
. The winding turns of
T_{1}
and
T_{3}
a 48:4:4 and the winding turns of
T_{2}
is 30:5:5. The magnetizing inductances
L_{m1}
=
L_{m3}
=2.3
m
H and
L_{m2}
=
L_{m4}
=
1.2
m
H, and the output inductances
L_{o1}
=
L_{o2}
=1 2
μH
. MOSFETs IRFP460 with
V_{DS}
=500 V,
I_{d,rms}
=20 A are used for switches
S_{1}

S_{8}
. The KCU30A30 fast recovery diodes with 300 V voltage rating and 30 A average current are used for
D_{1}

D_{4}
. Fast recovery diodes 30ETH06 are adopted for the clamped diodes
D_{a}

D_{d}
. The DC input capacitances
C_{1}

C_{4}
are 220
μ
F. The flying capacitances
C_{f1}

C_{f4}
are 1
μ
F. The output capacitance
C_{o}
is 4000
μ
F. The measured waveforms of the PWM signals of
S_{1}

S_{4}
of the first circuit cell at full load are shown in
Fig. 7
.
Fig. 8
provides the measured gate voltages of
S_{1}
and
S_{2}
in the first circuit cell and those of
S_{5}
and
S_{6}
in the second circuit cell under full load conditions.
S_{5}
and
S_{6}
in the second circuit are clearly phaseshifted by onefourth of the switching period with respect to
S_{1}
and
S_{2}
in the first circuit.
Fig. 9
shows the measured results of the AC side voltages
v_{ab}

v_{df}
and the rectified voltages
v_{rect1}
and
v_{rect2}
at full load. Three voltage levels,
V_{in}
/2, 0, and 
V_{in}
/2, are generated on AC side voltages
v_{ab}
and
v_{de}
; and two voltage levels
V_{in}
/4 and 
V_{in}
/4 are generated on voltages
v_{ac}
and
v_{df}
. Three voltage levels,
V_{in}
/
n
,
V_{in}
/(2
n
), and 0, are shown at the rectified voltages
v_{rect1}
and
v_{rect2}
.
Fig. 10
gives the measured results of gate voltage, drain voltage, and switch current of
S_{1}
at half and full load conditions under 800 V input voltage. Similarly, the measured gate voltage, drain voltage, and switch current of
S_{2}
at 50% and 100% loads are given in
Fig. 11
.
Figs. 10
and
11
clearly show that
S_{1}
and
S_{2}
are all turned on under ZVS.
S_{3}
and
S_{4}
have the same switch current and voltage waveforms as
S_{2}
and
S_{1}
, respectively. Thus,
S_{3}
and
S_{4}
are also turned on under ZVS from 50% load to full load. Switches
S_{5}

S_{8}
in the second circuit cell have the same PWM signals as
S_{1}

S_{4}
in the first circuit cell. Thus,
S_{5}

S_{8}
are also turned on under ZVS from 50% to 100% load.
Fig. 12
shows the measured waveforms of inductor currents
i_{Lr1}

i_{Lr4}
at full load. When
v_{ab}
is positive, inductor currents
i_{Lr1}
and
i_{L2}
both increase. Moreover, inductor currents
i_{Lr1}
and
i_{L2}
both decrease when
v_{ab}
is negative. Inductor currents
i_{Lr3}
and
i_{Lr4}
are phaseshifted by onefourth of the switching period with respect to
i_{Lr1}
and
i_{Lr2}
.
Fig. 13
shows the measured input capacitor voltages
v_{C1}

v_{C4}
and the flying capacitor voltages
v_{Cf1}

v_{Cf4}
at full load, and
V_{in}
=800
V
. The average flying capacitor voltages
v_{Cf1}

v_{Cf4}
are equal to 200 V, and the average voltages
v_{C1}

v_{C4}
are equal to 400 V. The measured diode currents
i_{D1}

i_{D4}
at full load are shown in
Fig. 14
.
Fig. 15
(a) shows the output inductor current at full load without interleaved PWM operation. The measured ripple current is approximately 16 A.
Fig. 15
(b) shows the measured output inductor currents
i_{Lo1}
,
i_{Lo2}
and the resultant output current
i_{Lo1}
+
i_{Lo2}
at full load. Two output inductor currents
i_{Lo1}
and
i_{Lo2}
are balanced and phaseshifted by onehalf of the switching period. The ripple current on
i_{Lo1}
+
i_{Lo2}
is approximately 6 A in
Fig. 15
(b). From
Fig. 15
, the resultant output inductor current iLo1+iLo2 with interleaved operation has less current ripple than the output inductor current without interleaved operation.
Fig. 16
presents the measured output ripple voltage with and without interleaved PWM operation under full load condition. The proposed converter with interleaved PWM operation has low output ripple voltage. The measured circuit efficiencies at different input voltage and load conditions are shown in
Fig. 17
.
Photograph of the prototype circuit.
Measured results of gate voltages of S_{1}S_{4} at full load.
Measured results of gate voltages of S_{1}, S_{2}, S_{5}, and S_{6} at full load.
Measured results of the AC side voltages v_{ab}–v_{df} and the rectified voltages v_{rect1} and v_{rect2} at full load [v_{ab}–v_{df} : 500V/div; v_{rect1}, v_{rect2}100 V/div; time 2 μs/div].
Measured waveforms of gate voltage, drain voltage and switch current of S_{1} at (a) 50% load and (b) full load.
Measured waveforms of gate voltage, drain voltage, and switch current of S_{2} at (a) 50% load and (b) full load.
Measured waveforms of inductor currents i_{Lr1}i_{Lr4} at full load.
Measured input capacitor voltages v_{C1}v_{C4} and flying capacitor voltages v_{Cf1}v_{Cf4} at full load.
Measured diode currents i_{D1}i_{D4} at full load.
Measured waveforms of output inductor currents at full load (a) without interleaved operation and (b) with interleaved operation.
Measured output ripple voltage under full load (a) without interleaved operation and (b) with interleaved operation.
Measured circuit efficiencies at different input voltage and load conditions.
V. CONCLUSIONS
A new threelevel ZVS converter for highinputvoltage applications is presented with the features of ZVS turnon for all switches from 50% load to full load, low voltage stress of power switches, and low voltage variation on output inductors. Two threelevel converters are operated by interleaved PWM scheme to reduce the current rating of active and passive components and decrease the current ripple at the output side. In each converter, the voltage stress of power switches is clamped at
V_{in}
/2 by using threelevel diode clamped topology. Two flying capacitors are adopted in each circuit cell to balance two input split capacitor voltages. The proposed threelevel converter combines one halfbridge PWM converter and one threelevel PWM converter to reduce the output inductor voltage variation. Therefore, the switching current in the output capacitor can be reduced compared with the switching capacitor current in the conventional threelevel PWM converter. Finally, experiments are provided to verify the effectiveness of the proposed converter.
Acknowledgements
This project is partly supported by the National Science Council of Taiwan under Grant NSC 1022221E224022MY3.
BIO
BorRen Lin received his B.S.E.E. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988 and his M.S. and Ph.D. degrees in Electrical Engineering from the University of MissouriColumbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics and the Journal of Power Electronics. His main research interests include powerfactor correction, multilevel converters, active power filters, and softswitching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of Research Excellence Awards in 2004, 2005, 2007, and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, and the IEEE–Power Electronics and Drive Systems 2009 Conference.
YuBin Nian is currently working toward his M.S. in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His research interests include the design and analysis of powerfactor correction techniques, switchingmode power supplies, and softswitching converters.
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