Pulsewidth modulated (PWM) fullbridge boost converters are used in applications where the output voltage is considerably higher than the input voltage. Zerovoltageswitching (ZVS) is typically implemented in these converters. A new ZVS–PWM fullbridge converter is proposed in this paper. The proposed converter does not have any of the disadvantages associated with other converters of this type, including a complicated auxiliary circuit, increased current stresses in the main power switches, and loaddependent ZVS operation. The operation of the proposed converter, its steadystate characteristics, and its design are explained and examined. The feasibility of the converter is confirmed with results obtained from an experimental prototype.
I. INTRODUCTION
Currentfed PWM fullbridge boost converters, like the one shown in
Fig. 1
, are very attractive in applications where the required output DC voltage is considerably larger than the input voltage. Such applications include medical power supplies and power supplies for electrostatic applications requiring extremely high output voltages , as well as fuel cell and photovoltaic applications where the input voltage is very low. Standard voltagefed PWM fullbridge converters that have a bulk capacitor at the input of the fullbridge are not typically used in these applications because a large turns ratio of the main power transformer is needed and this large ratio exacerbates the nonidealities of the transformer. In particular, leakage inductance and winding capacitance can significantly change the behavior of the converter by generating high voltage and current spikes.
Currentfed PWM fullbridge boost converter.
A PWM fullbridge boost converter can be implemented with either zerovoltage switching (ZVS)
[2]

[13]
or zerocurrent switching (ZCS)
[14]

[20]
depending on the application. ZVS is implemented in applications where the input voltage is high, the input current is low or moderate, and the switch turnon switching losses are dominant. ZCS is implemented in applications where the input current is high and the conduction losses are dominant. The focus of this paper is on ZVSPWM fullbridge boost converters and is based on a study that was performed by the authors
[1]
.
Although the fullbridge boost converter shown in
Fig. 1
is a boost converter and its operation is similar to that of a singleswitch PWM boost converter (either the DC bus is shorted and the current in the input inductor L
_{in}
increases or the diagonally opposed switches are on and the current in L
_{in}
decreases while energy is being transferred to the output), a number of ZVS techniques that can be used in singleswitch boost converters cannot be used in isolated boost fullbridge converters. The reason for this limitation in the applicability of ZVS techniques is the interaction between the output capacitances of the converter switches and the leakage inductance of the main power transformer. Unlike a singleswitch PWM boost converter, the converter in
Fig. 1
does not have a bulk capacitor across the DC bus whenever a switch is turned off. The only bulk capacitor in the circuit is at the secondary side of the converter, far from the converter switches. Unless the circuit in
Fig. 1
is modified, the switches will experience highvoltage overshoots and ringing whenever they are turned off. Such overshoots and ringing cannot be avoided in many ZVS techniques that can be used in singleswitch PWM boost converters.
Despite this limitation, a number of ZVSPWM currentfed boost fullbridge converters have been proposed. At present, these converters elicit considerable attention because of their use in various industrial applications, such as those mentioned above. Previously proposed converters of this type, however, have at least one of the following disadvantages:

The converter is a resonant converter[2][5]and therefore has the disadvantages associated with many resonant converters. Such disadvantages include the need for variable switching frequency control, which complicates the design of the transformer as it must be able to operate across a wide range of switching frequencies, and high circulating primary current, which increases conduction and turnoff switching losses. Although the converter becomes more efficient, if ZVS is not implemented, the gains in efficiency are not as much as what they could possibly be because of these losses.

The converter is implemented with some sort of dissipative snubber at the DC bus to suppress voltage overshoots and ringing across the switches[6], [22]. Although the efficiency of these techniques is improved, the losses in the dissipative snubber limit the gains in efficiency

The converter is implemented with some sort of active auxiliary circuit that consists of an active device and a few passive components. The auxiliary circuit is connected parallel to the full bridge. It is used to discharge the switch output capacitances before the switches are turned on and is deactivated shortly afterward. The active switch in the auxiliary circuit, however, does not turn off softly and thus entails turnoff losses[7]. Again, these losses partially offset whatever gains in efficiency may be achieved by the reduction in the converter’s turnon switching losses.

The auxiliary circuit is an active clamptype circuit[8][12], and although the converter operates with ZVS, its ZVS operation is load dependent and is lost at light loads. Moreover, the current stresses of the switches are higher than those of other PWM boost fullbridge converters because the switches must conduct current from the auxiliary circuit in addition to the input inductor current.
The converter’s auxiliary circuit is very complicated and its cost is not negligible because it contains many components
[13]
.
A new ZVSPWM fullbridge boost converter (
Fig. 2
) with none of the disadvantages discussed above is proposed in this paper. The converter is specifically designed for applications that require a high stepup voltage ratio. In the paper, the operation of the proposed converter is explained in detail, and a mathematical analysis of its steadystate operation is performed. The results of the analysis are used to establish a procedure for the design of the converter. The feasibility of the converter is confirmed with results obtained from an experimental prototype.
Proposed ZVS fullbridge boost converter.
II. CONVERTER OPERATION
The proposed converter is a standard PWM fullbridge converter but with an auxiliary circuit that consists of auxiliary switch S
_{aux}
, snubber capacitor C
_{r}
, resonant inductor L
_{r}
, and two diodes D
_{1}
and D
_{2}
. The sequence of gating signals that the converter operates with in a typical switching cycle is as follows: S
_{1}
and S
_{4}
on → all bridge switches on → S
_{2}
and S
_{3}
on → all switches on. In other words, an energy transfer mode, in which only a pair of diagonally opposed switches is on, is always followed by a “boosting” mode, in which all the switches are on and no energy is transferred. The basic principle behind the converter is that the auxiliary circuit is activated whenever two converter switches are about to be turned on to short out the DC bus. The switches turn off with ZVS because of the switch output capacitances (which may be a combination of internal and external capacitances) and capacitor C
_{r}
in the auxiliary circuit, which is larger than the switch output capacitances. The ZVS operation of the switches can be seen by considering the various modes of operation that the proposed converter undergoes during a halfswitching cycle. The modes are as follows:
Converter modes of operation.
Typical converter waveforms.
Mode 0 (t< t_{0}) (Fig. 3(a)):
In this mode, only switches S
_{1}
and S
_{4}
are on. The converter is in an energy transfer mode as energy is transferred from the input to the output through diodes D
_{3}
and D
_{6}
. The current through L
_{main}
decreases throughout this mode.
Mode 1 (t_{0}1) (Fig. 3(b)):
This mode begins when switch S
_{aux}
is turned on in anticipation of the DC bus being shorted and the converter entering a boosting mode. The current starts flowing through S
_{aux}
because snubber capacitor voltage V
_{Cr}
is greater than the input voltage. S
_{aux}
turns on softly given that inductor L
_{r}
is in series with this switch and limits the increase in current through it. C
_{r}
discharges into the auxiliary inductor during this mode. Diode D
_{1}
is reversebiased and does not conduct because voltage V
_{Cr}
is higher than the bridge voltage. This mode ends when C
_{r}
voltage reaches the voltage across the offstate bridge switches, which is
Mode 3 (t_{2}3) (Fig. 3(d)):
The output capacitances of switches S
_{2}
and S
_{3}
and capacitor C
_{r}
continue to discharge in this mode. The current in the auxiliary circuit branch is equal to the sum of the current from the full bridge caused by discharging the switch output capacitances and C
_{r}
and the input current that flows through L
_{main}
.
Mode 4 (t_{3}4) (Fig. 3(e)):
At the beginning of this mode, the DC bus voltage is zero and is clamped to zero as the body diodes of the converter switches are forwardbiased and begin to conduct. Switches S
_{2}
and S
_{3}
can be turned on with ZVS sometime during this mode as the current flows through their bodydiodes. Moreover, during this mode, the current that flows through the auxiliary circuit (and thus, the current through the full bridge) begins to decrease because the voltage across the auxiliary inductor is negative as the input voltage is at one end of the circuit and the DC bus voltage is zero. The auxiliary circuit current is equal to the current through L
_{main}
at the end of this mode; this condition makes the current flowing through the full bridge zero.
Mode 5 (t_{4}5) (Fig. 3(f)):
At t = t
_{4}
, the current flowing through the full bridge reverses its direction and flows through the switches. The current in the auxiliary circuit continues to decrease as the input current is gradually transferred to the full bridge. The auxiliary circuit current is zero by the end of this mode, and S
_{aux}
can be turned off softly at any time afterward until a diagonal pair of switches is turned off and the DC bus is no longer shorted.
Mode 6 (t_{5}6) (Fig. 3(g)):
The converter is in a boosting mode. It operates like a standard PWM boost converter as the DC bus is shorted. The current through L
_{main}
increases, and the auxiliary circuit is inactive.
Mode 7 (t_{6}7) (Fig. 3(h)):
At t = t
_{6}
, switches S
_{1}
and S
_{4}
are turned off. These switches can be turned off with ZVS because of the presence of their output capacitances (not shown in the fig) and C
_{r}
. The main switch output capacitances and C
_{r}
begin charging. At the end of this mode, their voltage reaches
Mode 8 (t_{7}8) (Fig. 3(i)):
At the beginning of this mode, as the DC bus voltage increases, the transformer primaryside voltage reaches a certain level and results in the output diodes becoming forwardbiased and thus conducting current. The main inductor current transfer from snubber capacitor C
_{r}
to the transformer primary winding is gradual and requires some time because of the leakage inductance of the transformer. During this time, the current flowing through C
_{r}
results in the capacitor being charged over and above the DC bus voltage, which in turn results in voltage overshoots across the main fullbridge switches that are off. At the end of this mode, the voltage across C
_{r}
reaches its maximum value and is clamped at this value as no current path exists for it to discharge. In the meantime, the main switch output capacitances and capacitor C
_{r}
begin to resonate with the transformer leakage inductance at the start of this mode.
Mode 9 (t > t_{8}) (Fig. 3(j)):
After t = t
_{8}
, the converter is in an energytransfer mode as switches S
_{2}
and S
_{3}
conduct current. Power is transferred from the input to the output, and the current in L
_{main}
decreases. The transformer leakage inductance continues to resonate with the output capacitors of the main switches at the beginning of this mode, but this resonance eventually recedes because of the parasitic resistances in the converter.
III. CONVERTER ANALYSIS
To design the converter, its steadystate characteristics must be determined. In this section, a mathematical analysis of converter modes of operation is performed to derive key equations and understand the steadystate behavior of the converter relative to the values of certain key components. These relations will be used to develop a design procedure for the proposed converter.
For the steadystate mathematical analysis, the following assumptions are made:

Input inductor Lmainis sufficiently large to be considered a constant current source.

The output capacitor is sufficiently large to be considered a voltage source equal to the output voltage.

All semiconductors have zero voltage drops while turned on.

The transformer is ideal and has an infinite magnetizing inductance.
The main objective of the mathematical analysis is to obtain equations for auxiliary circuit capacitor voltage V
_{Cr}
and auxiliary circuit inductor current i
_{Lr}
for each mode of operation where the auxiliary circuit is active. Using a computer program to monitor V
_{Cr}
and i
_{Lr}
throughout one switching cycle, analytical waveforms related to these parameters are then generated. These waveforms can then be used as part of a design procedure for the converter so that it is possible to turn its switches on and off softly, and to determine the voltages across them and the currents that flow through them so that appropriate devices can be selected. In what follows, the circuit analyses of the proposed converter in different modes of operation are presented and explained:
Mode 0 (Fig. 3(a)):
Based on the circuit in
Fig. 3
(a), the following Kirchhoff’s Voltage Law (KVL) equation can be written applied at the transformer primary side:
where
i_{Lm}
is the current flowing through the input voltage source and N is the secondary to primary turns ratio of the transformer.
Mode 1 (Fig. 3(b)):
In this mode, the auxiliary switch is turned on and the current begins to circulate through the auxiliary circuit without any influence on the main converter operation. The initial current of auxiliary circuit inductor L
_{r}
is zero, and the initial value of snubber capacitor C
_{r}
can be expressed as
where
C_{tot}
=
C_{r}
+ 2
C_{s}
, C
_{S}
is the output capacitor of one of main switches, L
_{lk}
is the transformer leakage inductance, and I
_{in}
is the boost inductor current. The derivation of this equation is based on Mode 8. Mode 8 is the last mode of the halfswitching cycle when the auxiliary circuit is active; thus, the value of V
_{Cr}
at the end of Mode 8 can be considered to be the initial value of Mode 1, which is the first mode when the auxiliary circuit is active in the converter.
By applying KVL to the auxiliary circuit loop shown in
Fig. 3
.3, the following differential equation can be derived:
This equation can be solved to obtain
where
V
_{o}
can be substituted with
where D is the duty ratio of each main switch and N is the transformer secondary to primary turn ratio.
Snubber capacitor voltage V
_{Cr}
reaches
at the end of Mode 1, at time t = t
_{1}
; thus,
Substituting Eqs. (6) and (7) into Eqs. (4) and (5), the equation that expresses the duration of time for Mode 1, t
_{1}
− t
_{0}
, can be written as
Substituting Eq. (8) into Eq. (5) provides the following equation for
i_{Lr}
(t
_{1}
) :
i_{Lr}
(
t
_{1}
) is henceforth referred to as
α
to simplify the expression of the Mode 2 equations.
Mode 2 (Fig. 3(c)):
In this mode, the output capacitors of switches S
_{2}
and S
_{3}
have the same voltage as capacitor C
_{r}
,
By applying KVL and KCL to the circuit shown in
Fig. 3
(c), the following equations can be derived:
where the initial value conditions are
The current in the transformer reaches zero at the end of this mode. Given the complexity of the above modal equations, a closedform equation for the length of time (
t_{2}

t_{1}
) is required to be determined by the computer program.
Mode 3 (Fig. 3(d)):
At the start of this mode, the transformer primary current is zero and the initial values of the inductor current and capacitor voltage are I
_{0}
and V
_{0}
, respectively. With KVL and KCL, the following equations can be derived:
Solving these equations results in the following expressions:
where
Similar to Mode 2, the length of this mode can be calculated by the computer program by determining the time (t
_{3}
– t
_{2}
) required for V
_{Cr}
to decrease to zero.
Mode 4 (Fig. 3(e)):
During this mode, the voltage across C
_{tot}
, V
_{Cr}
, is always zero and that across the auxiliary circuit inductor is constant and equal to –V
_{in}
because one end of the inductor is connected to the V
_{in}
input source through S
_{aux}
and the other end is connected to C
_{r}
(thus, 0 V) through D
_{2}
. The auxiliary circuit inductor voltage can be expressed as
By solving Eq. (18), i
_{Lr}
(t) can be derived as
with the initial value of i
_{Lr}
(t
_{3}
) = I
_{02}
and
t_{2}
<
t
<
t_{4}
; thus, current linearly decreases in the auxiliary branch. From KCL, the total current flowing through the bridge switches equals
I_{in}  i_{Lr}
; therefore, the current in each main switch, i
_{S}
, can be expressed as:
Given that
I_{in} < i_{Lr}
in this mode, this current is negative because it flows through the body diodes of the switches.
Mode 5 (Fig. 3(f)):
The only difference between this mode and Mode 4 is that current reverses in the bridge switches. The voltage across capacitor C
_{r}
remains clamped at zero because all fullbridge switches are on and the DC bus is shorted. Eqs. (18) and (19), which were derived for the previous mode, are also valid for this mode. Eq.(19) can be rewritten as
with the initial value of i
_{Lr}
(t
_{4}
) = I
_{03}
and
t_{4}
<
t
<
t_{5}
. At the end of this mode, the current through L
_{r}
, i
_{Lr}
, reaches zero and the auxiliary circuit is inactive.
Mode 6 (Fig. 3(g)):
During this mode of operation, the converter is in a boosting mode because all bridge switches are on. The input current flows through the main switches, and the auxiliary circuit is inactive. The input inductor is magnetized according to following equation:
The auxiliary switch can be turned off anytime during this mode with zerocurrent switching. After the switch is turned off, the output capacitance that is parallel to the auxiliary switch cannot be charged because of blocking diode D
_{2}
. The voltage across this switch therefore remains zero until the start of the next mode. The duration of this mode is determined by the converter’s duty cycle.
Mode 7 (Fig. 3(h)):
This mode begins when a pair of diagonally opposed switches, S
_{1}
and S
_{4}
, are turned off. In this mode, the full input inductor current flows through capacitor C
_{r}
and the output capacitances of switches S
_{1}
and S
_{4}
. No power is delivered to the output through the fullbridge switches. As current flows through the auxiliary circuit, an equation is required to define V
_{Cr}
. No such equation is required for i
_{Lr}
because S
_{aux}
is off. Such an equation can be written as
where
C_{tot}
=
C_{r}
+ 2
C_{s}
, V
_{C}
(
t
_{6}
) =0 and
t_{6} < t < t_{7}
. Rearranging this equation gives
where V
_{Cr}
is the same as the voltage across switches S
_{1}
and S
_{4}
. At the end of this mode, V
_{Cr}
reaches
This condition makes output bridge diodes D
_{4}
and D
_{5}
forwardbiased so that they can conduct current. This condition allows power to be transferred through D
_{4}
and D
_{5}
to the output.
It should be noted that the voltage across diode D
_{2}
is V
_{in}
V
_{Cr}
. After V
_{Cr}
is charged to the level of the input voltage, diode D
_{2}
becomes forwardbiased and the output capacitance of the auxiliary switch voltage begins to charge. Given that the capacitance is small compared with that of C
_{tot}
, this capacitance is ignored in Eqs. (23) and (24). At the end of this mode, the voltage across S
_{aux}
, V
_{aux}
, is equal to
Mode 8 (Fig. 3(i)):
During this mode, the main inductor current is gradually diverted from snubber capacitor C
_{r}
to the transformer. As this transition occurs, the input inductor current continues to charge C
_{r}
and V
_{Cr}
begins to exceed
which results in voltage overshoots across switches S
_{1}
and S
_{4}
. The following equations can be derived with KCL and KVL:
where
By solving Eqs. (26) and (27), the following expression for V
_{Cr}
(t) can be derived.
where
(28) shows that the voltage overshoot of C
_{r}
, S
_{1}
, and S
_{4}
is
such that the initial value of the snubber capacitor voltage of the next mode is the maximum of
V_{Cr}
in Eq. (28):
Mode 9 (Fig. 3(i)):
During this mode, the converter is in an energytransfer mode because switches S
_{2}
and S
_{3}
conduct current. Power is transferred from the input to the output, and the current in L
_{main}
declines. The transformer’s leakage inductance continues to resonate with the output capacitors of the main switches at the beginning of this mode, but this resonance eventually recedes because of parasitic resistances in the converter. From a mathematical point of view, the voltage across the fullbridge switches eventually settles to
sometime during this mode.
IV. DESIGN PROCEDURE
A design procedure for the proposed fullbridge boost converter is explained with an example in this section. The following specifications are considered for the design:

Output voltage Vo= 300 V

Output power Po= 500 W

Input voltage Vin= 100 V

Expected efficiency at full load ή = 93 %

Switching frequency fsw= 50 kHz
The design procedure presented requires several iterations, both theoretical and experimental, before the final design can be achieved. The general approach taken in the procedure is as follows: First, the converter is designed as a conventional hardswitched converter without the auxiliary circuit. Next, the auxiliary circuit is designed. Finally, the design of the converter is confirmed. Eqs. (4) to (19) can be used to generate graphs of the key steadystate characteristic curves of this converter. The curves can be generated by a computer program, such as MATLAB.
 A. Transformer Turns Ratio
The turns ratio of the transformer can be considered the most critical converter parameter, considering that all other parameters are ultimately dependent on it. The turns ratio, N, affects the converter’s duty cycle range, which in turn affects the selection of input inductor and output capacitor values. An appropriate value of N can only be determined after several iterations. Once N is determined, the rest of the converter parameters are designed based on this value. Verification or “checking” should be performed afterward to confirm the validity of the design.
If the input inductor current is continuous, then the relation between output voltage V
_{O}
and input voltage V
_{in}
can be expressed by the equation below, which is based on the operation of a conventional singleswitch boost converter:
Given that a path for current to flow through in the converter must always be provided, each switch must be on for at least a switch dutycycle of D = T/2. Converter duty cycle D
_{c}
is based on the amount of overlap between the gating signals of S
_{1}
and S
_{4}
and those of S
_{2}
and S
_{3}
; thus, the relation between D and D
_{c}
can be expressed as
where D
_{c}
T represents the amount of time during which an overlap occurs in the two pairs of gating signals (i.e. all the switches are on) throughout a switching cycle. Considering that there are two instances during a switching cycle when all the converter switches are on, the term
is used in Eq. (32). If Eq. (32) is substituted into Eq. (31), then the following equation can be derived:
Eq. (42) can be rearranged to give
For this design example, a value of N = 1, which was determined from the previous iteration is used. The converter is designed based on this value. With this value of N and assuming that the input inductor current is continuous, a value of D = 0.83 is determined based on input voltage V
_{in}
= 100 V and V
_{O}
= 300 V. If D = 0.83, then D
_{c}
= 0.66 from Eq. (34). This value of D
_{c}
is used in the subsequent sections to determine the input inductor and output capacitor values.
 B. Input Inductor
With the values of N and D determined, the design of the rest of the hardswitching converter can proceed, beginning with the input inductor in this section and the output capacitor in the next section. The main consideration for the design of the input inductor in an isolated fullbridge DC–DC boost PWM converter is to limit the peaktopeak ripple of the current flowing through the inductor. There is, however, a compromise that should be considered in selecting the inductor value. If L
_{main}
is large, then the peaktopeak ripple of the current will be small, but the physical size of the inductor will increase significantly, as will the size and weight of the converter. If L
_{main}
is too small, then the physical size of the inductor will likewise be small, whereas the peaktopeak ripple of the inductor current will be large. A 10% peaktopeak ripple to average current ratio is a compromise that is typically made
[21]
; such compromise is adopted in this example design.
The converter operates with a continuous input current. The average input current (input current without the ripple) can be determined from the converter specifications:
The auxiliary circuit injects some current back into the input source during Modes 1 to 5 of operation; thus, the value of I
_{in}
when the converter operates with the auxiliary circuit is different from the value of I
_{in}
when the converter operates without the auxiliary circuit. Given that the average value of this current is small compared to the input current, it can be considered negligible and is thus not considered in calculating the average inductor current in Eq. (35) for simplicity.
After the average inductor current value is determined, ΔI should be
A relation between L
_{main}
and ΔI exists. The voltage across the input inductor when the converter is in a boosting mode and when all switches are on can be expressed as
where
V_{in}
is the voltage across
L_{main}
when switches S
_{1,4}
and S
_{2,3}
are conducing.
is the duration of the boosting mode in a halfswitching cycle, and
di
= ΔI is the change in the input current during that time.
The value of can thus be determined by rearranging Eq. (37) to obtain
 C. Output Capacitor
The minimum value of the output capacitor can be determined from Eq. (39) as provided in
[20]
:
where R is the output resistance at maximum load (V
_{o}
^{2}
/P
_{o,max}
), f
_{o}
is the output voltage ripple frequency that is twice the switching frequency, and
is the percentage of the peaktopeak output voltage ripple. By assuming a 0.1 % peaktopeak output voltage ripple, which is considered as acceptable for many converter applications, and by substituting D
_{c}
= 0.66, f
_{o}
= 100 kHz, and R = 180 Ω, C
_{o}
is determined to be
 D. Snubber Capacitor
The first step in the design of the auxiliary circuit is the selection of a value for the snubber capacitor C
_{r}
considering that the design of the other auxiliary circuit parameters is dependent on this value.
The value of C
_{r}
should be as small as possible to minimize the amount of energy ultimately transferred to the input after it is discharged. It should also be small to minimize the amount of time that the auxiliary circuit is in the circuit and to minimize the effect that it may have on the general operation of the converter. A large C
_{r}
means that much time is required by the auxiliary circuit to discharge it. C
_{r}
, however, should be large enough to decrease the rate of the voltage rise across the main switches during Mode 7, to obtain a ZVS turnoff for the main switches, and to prevent voltage spikes from appearing across the switches when they are turned off, as much as possible.
One measure of the amount of energy processed by the auxiliary circuit is the rms value of the current that flows through it during a switching cycle. With this in mind, a graph of auxiliary circuit rms current vs. % voltage overshoot, such as the one shown in
Fig. 5
, can be generated with a MATLAB program. The graph in
Fig. 5
was generated with Eq. (29), which is reproduced here
Voltage overshoots of the main switches versus the auxiliary circuit rms current.
It should be noted that voltage overshoot is dependent on the transformer leakage inductance, as shown in the description of Mode 8 of the converter. The higher the leakage inductance of the transformer is, the more voltage overshoot can appear across the main fullbridge switches. Leakage inductance, however, cannot be eliminated because it is an inherent part of any transformer. The leakage inductance of the transformer used for this design example is L
_{lk}
= 750 nH.
The graph in
Fig. 5
shows that overshoot levels higher than 20% do not have a significant effect on the reduction of the auxiliary circuit rms current. An overshoot of 20% is therefore, is selected for this design example. From Eq. (41)
and thus
C_{tot}
= 6.2 nF, according to
C_{tot}
=
C_{r}
+ 2
C_{S}
where C
_{s}
is the output capacitance of a main switch. If it is assumed, based on previous iterations, that IXFH52N50P2 MOSFET devices, which have an output drainsource capacitance of approximately 600 pF, are used as the main power switches, then the required
C_{r}
is 5 nF.
 E. Auxiliary Inductor
Given that the auxiliary switch operates with soft switching, the main concern in selecting the auxiliary inductor is to minimize the amount of rms current that flows in the auxiliary circuit and the peak current stress on the devices in the auxiliary circuit. An appropriate auxiliary inductor value can be selected using graphs, such as those shown in
Figs. 6
and
7
. The graph shown in
Fig. 6
is a graph of the auxiliary switch peak current vs. the auxiliary circuit inductor value. The graph shown in
Fig. 7
is a graph of the auxiliary switch rms current vs. the auxiliary circuit inductor value. These graphs were generated from the modal equations derived in Section III
Current peak of the auxiliary circuit.
Rms of the auxiliary circuit current.
Figs. 6
and
7
show that there is little change occurs in the peak auxiliary switch current when the auxiliary circuit inductor L
_{r}
is greater than 7 μH, but that the rms current increases when L
_{r}
is greater than 7 μH. This is because the L
_{r}
current becomes flat as L
_{r}
increases, but it exists for a longer amount of time as increasing L
_{r}
increases the resonant cycle between L
_{r}
and C
_{r}
. As a result, a value of L
_{r}
= 7 μH is selected.
 F. Conditions for the soft switching operation of the converter switches
Due to the inductor in series with the auxiliary switch, this switch turns on softly and the current in the switch increases gradually. The auxiliary switch can be turned off with ZCS when no current flows through the switch. No specific time window exists during which the auxiliary switch needs to be turned off with ZCS because of the nature of the auxiliary circuit in the converter and because the current flows through this circuit for only a small fraction of the switching cycle.
As long as the auxiliary switch is turned off before a pair of main fullbridge switches is about to be turned off, the auxiliary circuit will not interfere with the operation of the main fullbridge switches. The main power switches can be turned off with ZVS as described above because each main power switches has an output drainsource capacitance and because C
_{r}
is present in the converter. As for the ZVS turnon of the main switches, snubber capacitor voltage
V_{Cr}
should reach zero at the end of Mode 3 of converter operation before a switch is turned on with ZVS; therefore, the following expression can be derived from Eq. (17) from Mode 3:
Given that the parameters such as
ω
_{2}
, C
_{tot}
, and V
_{o}
are interrelated by
V_{in}, L_{r}, C_{r}, C_{s}, L_{k}, I_{in}
, and D, Eq. (43) can be rewritten as a function of D and can be used to explore the converter’s ZVS range with different values of D. A graph of snubber capacitor voltage V
_{Cr}
vs. time for different values of main switch duty cycle D is shown in
Fig. 8
, with the time axis starting from time
t_{2}
.
Variation in snubber capacitor voltage for different values of the main switch duty cycle (D).
The ZVS time window (the amount of time during which a main power switch can be turned on with ZVS) is the interval during which the snubber capacitor voltage is negative, as shown in
Fig. 8
. A main power switch will not turn on with ZVS unless its main switch duty cycle is at least D = 0.81 as it can be seen in
Fig. 8
. Given that D is equal to 0.83 as shown in the previous steps, the main fullbridge switches can be turned on with ZVS.
The key condition for ZVS operation is that the DC bus voltage (voltage at the input of the bridge) must be at least twice the input voltage. If the converter is designed to operate with D < 0.5 under steadystate fullload conditions, then the converter will not operate with ZVS. If the converter is designed to operate with D > 0.5 under fullload conditions, then it can operate with ZVS even if D is less than 0.5 under light load conditions because the voltage reflected to the primary side is still greater than twice the input voltage.
 G. Voltage and current stress of auxiliary switch Saux
The KVL and KCL equations of the auxiliary circuit in Mode 1 show that the maximum current flowing through the auxiliary switch can be maintained at twice the value of the input inductor current. Moreover, the maximum voltage across this switch occurs at the end of Mode 5, which is around V
_{o}
/N.
V. EXPERIMENTAL RESULTS
An experimental prototype of the proposed converter was built to confirm its feasibility. The prototype was designed based on the following specifications:

Input voltage Vin= 100 V

Output voltage Vo= 300 V

Output power Po= 500 W

Switching frequency fsw= 50 kHz
The prototype was implemented with the component values determined from the design example discussed in Section IV. The main bridge switches, S
_{14}
, were IXFH52N50P2, auxiliary switch S
_{aux}
was FCA36N60NF. Diode D
_{1}
was BYV29300, diode D
_{2}
was BYV29300, and output diodes D
_{36}
were BYV29500. Auxiliary inductor L
_{r}
was 7 μH, input inductor L
_{main}
was 750 μH, resonant capacitor C
_{r}
was 5 nF, and the transformer turns ratio was 1:1.
The ZVS operation of one of the main fullbridge switches during turnon and turnoff is shown in
Figs. 9
(a) and
9
(b). Typical auxiliary switch S
_{aux}
voltage and current waveforms are shown in
Fig. 9
(c) to demonstrate that this switch can be turned on and off with ZCS. The voltage and current waveforms of the power transformer are shown in
Fig. 9
(d). All the waveforms were obtained with the converter operating at maximum load.
Experimental results.
The efficiency of the converter prototype was measured with the auxiliary circuit (ZVS softswitching implementation) and without it (hardswitching implementation) to determine the effectiveness of this circuit in improving converter efficiency. If the auxiliary circuit is removed, then the hardswitching converter may exhibit high voltage spikes across its main switches when they are turned off because the switch output capacitances are not, by themselves, sufficiently large to limit voltage rise and overshoots. As a result, an RCD snubber circuit was placed across the DC bus of the converter. The value of the capacitor (C) of this snubber was similar to that of C
_{r}
in the auxiliary circuit of the proposed converter.
Fig. 10
shows the efficiency of the converter prototype with ZVS and with hardswitching. The proposed ZVS converter exhibits considerably higher efficiency than the hardswitching boost converter over the load range. Efficiency is improved because no turnon or turnoff switching losses occur in the main switches and because the energy used for softswitching operation is delivered to the input. Normally, turnon and turnoff switching losses account for most of the losses in a hardswitching converter at high load.
Efficiency measurement for the proposed ZVS converter and the conventional hardswitching converter.
The proposed converter has the following features:

All four main switches can be turned on and off with ZVS.

The auxiliary switch can be turned on and off softly.

The auxiliary circuit is very simple as it consists of a switch, an inductor, and a few diodes.

The timing of the turning off of the auxiliary switch is very flexible as it can be performed at any time while the DC bus is shorted. This condition is in contrast to other ZVS converters where the auxiliary switch, if it can actually be turned off softly, must be turned off within a narrow window of time.

The auxiliary circuit does not dump additional current into the fullbridge switches so that their rms current and peak current ratings are similar to those of the switches of the PWM converter shown inFig. 1.
The converter’s ZVS operation is load independent because its switches can be turned on with ZVS from fullload to noload. The proposed converter is very well suited to industrial applications mentioned in the Introduction of this paper.
VI. CONCLUSIONS
A new ZVSPWM fullbridge converter that is specifically targeted towards for applications that require a high stepup voltage ratio is proposed in this paper. The proposed converter does not have any of the disadvantages associated with other converters of this type, including a complicated auxiliary circuit, increased current stresses in the main power switches, and load dependent ZVS operation. In this paper, the operation of the new converter, its steadystate characteristics, and its design were explained and examined. The feasibility of the converter was confirmed with the results obtained from an experimental prototype.
BIO
Mohammadjavad Baei received his B.Sc. degree from Sharif University of Technology, Tehran, Iran, in 2009 and his M.Sc. degree from the University of Western Ontario, Ontario, Canada in 2012, both in electrical engineering. He is currently a design engineer at Evertz Microsystem Ltd., Burlington, Ontario, Canada.
Mehdi Narimani received his B.Sc. and M.Sc. degrees from Isfahan University of Technology (IUT), Isfahan, Iran, in 1999 and 2002, respectively, and his Ph.D. degree from the University of Western Ontario, Ontario, Canada, all in electrical engineering. He is currently a postdoctoral research associate at the Department of Electrical and Computer Engineering at Ryerson University and Rockwell Automation, Canada. He worked as a faculty member of Isfahan University of Technology from 2002 to 2009, where he was involved in the design and implementation of several industrial projects. His current research interests include power converters, control of power electronics, and renewable energy.
Gerry Moschopoulos received his B.Eng., M.A.Sc., and Ph.D. degrees in electrical engineering from Concordia University, Montreal, QC, Canada, in 1989, 1992, and 1997, respectively. He worked as a design engineer in the Advanced Power Systems Division, Nortel Networks, Lachine, QC, Canada, from 1996 to 1998. He was a postdoctoral fellow at Concordia University from 1998 to 2000, where he was involved in research on power electronics for telecommunication applications. He is currently an associate professor at the University of Western Ontario, London, ON, Canada. Dr. Moschopoulos is a registered professional engineer in the province of Ontario.
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