Performance Analysis of a Novel Reduced Switch Cascaded Multilevel Inverter

Journal of Power Electronics.
2014.
Jan,
14(1):
48-60

- Received : June 03, 2012
- Accepted : September 11, 2013
- Published : January 30, 2014

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Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.
dv
/
dt
) stress on the load and the electromagnetic compatibility concerns
[1]
. Another important feature of multilevel inverters is that their semiconductors are wired in a series-type connection, which allows operation at higher voltages. However, this series connection is typically made with clamping diodes, which eliminates overvoltage concerns. Furthermore, since the switches are not truly series connected, their switching can be staggered. This reduces the switching frequency which reduces the switching losses.
One clear disadvantage of multilevel power conversion is the higher number of semiconductor switches required. It should be pointed out that lower voltage rated switches can be used in the multilevel inverter. Therefore, the active semiconductor cost is not appreciably increased when compared with two level cases. However, each active semiconductor added requires associated gate drive circuits and adds further complexity to the converter mechanical layout. Another disadvantage of multilevel power converters is the fact that the small voltage steps are typically produced by isolated voltage sources or a bank of series capacitors. Isolated voltage sources may not always be readily available, and series capacitors require voltage balancing
[2]
. To some extent, the voltage balancing can be addressed by using redundant switching states, which exist due to the high number of semiconductor devices. However, for a complete solution to the voltage-balancing problem, another multilevel inverter may be required
[3]
.
In recent years, there has been a substantial increase in interest in multilevel power conversion. Recent research has involved the introduction of novel inverter topologies and unique modulation strategies. However, the most recently used inverter topologies, which are mainly addressed as applicable multilevel inverters, are the neutral-point clamped (NPC) inverter, the flying capacitor inverter, and the cascade inverter. Among these, the cascade inverter topology is the most attractive, since it requires the least number of components and increases the number of levels in the inverter without requiring high ratings on individual devices while increasing the power rating of the inverter
[4]
.
Some applications for these new converters include industrial drives
[5]
, flexible ac transmission systems (FACTS)
[6]
–
[8]
, and vehicle propulsions
[9]
,
[10]
. One area where multilevel inverters are particularly suitable is that of renewable photovoltaic energy where efficiency and power quality are of great concern to researchers
[11]
.
Some new approaches have been recently suggested such as a topology utilizing low-switching-frequency high power devices
[12]
. Although this topology has some modification to reduce output voltage distortions, the general disadvantage of this method is that it has significant low-order current harmonics. It is also unable to exactly manipulate the magnitude of the output voltage due to an adopted pulse width modulation (PWM) method
[13]
.
Another approach is selection based on a set target which can be either the minimum switches used or the minimum dc voltage used. It also requires different voltage source values which are defined according to the target selection
[14]
. However, this approach requires basic units which are connected in series, and the basic units require more switches than the proposed topology. Another disadvantage of this topology is that the power switches and diodes need to have a different rating which is a major drawback of the topology.
The proposed topology is a symmetrical topology since all the values of all the voltage sources are equal. However, there are asymmetrical topologies
[15]
which require different voltage sources. This criterion makes it necessary to arrange the dc power supplies according to a specific relation between the supplies. Differences in the ratings of the switches in this topology are also a major drawback. This problem also occurs in similar topologies
[16]
–
[18]
. Some of the high frequency switches in this topology should approximately withstand the maximum overall voltage which makes its application limited to high-voltage products. In
[19]
, a new approach has been proposed that decreases the number of required dc supplies by inserting a transformer instead. The main disadvantage of this approach is the need to add so many transformer windings which will increase the overall volume and cost of the inverter.
This paper presents an overview of a new multilevel inverter topology referred to as a RSCML inverter. It is based on a multilevel DC link (MLDCL) topology. This topology requires a smaller number of components when compared to conventional topologies. It is also more efficient since the inverter has a component which operates the switching power devices at line frequency. Therefore, there is no need for all the switches to work in high frequency which leads to simpler and more reliable control of the inverter. Different multicarrier PWM techniques which use triangular carrier waveforms, saw tooth carrier waveforms and unipolar sine carrier waveforms are simulated for a 1KW, 3φ, nine-level RSCMLI using MATLAB/SIMULINK. The fundamental output voltage and the percentage of THD are observed and compared for different switching frequencies and modulation indexes. These results are verified by building an experimental prototype of a single phase nine level RSCML inverter and implementing the different multicarrier PWM techniques on it.
_{dc}
, 0 and ?V
_{dc}
, by connecting the dc source to the ac output with different switching combinations of the four semiconductor switches T
_{1}
,T
_{2}
,T
_{3}
and T
_{4}
. To obtain +V
_{dc}
, switches T
_{1}
and T
_{2}
are tuned on, while ?V
_{dc}
can be obtained by tuning on switches T
_{3}
and T
_{4}
. By turning on T
_{1}
and T
_{3}
or T
_{2}
and T
_{4}
, the output voltage is 0. The ac outputs of each of the full-bridge inverter levels are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs
[20]
,
[21]
.
Where m is the number of levels, n is the number of DC sources, and N is the number of switching devices in each phase. The most well known SPWM which can be applied to a conventional cascaded multilevel inverter (CCMLI) is the Phase-Shifted SPWM. This modulation technique is almost the same as the conventional SPWM technique which is applied to a conventional single phase full-bridge inverter. The only difference between them is that the Phase-Shifted SPWM utilizes more than one carrier. The number of carriers used per phase is equal to twice the number of dc voltage sources per phase (2n)
[20]
.
Single phase structure of the conventional cascaded multilevel inverter.
Single phase structure of the proposed multilevel inverter.
This topology easily extends to higher voltage levels by including an additional end stage in the level generation part in
Fig. 2
. Therefore, this topology is modular and can be easily increased to higher voltage levels. This topology is also suitable for applications where separate dc voltage sources are available, such as photovoltaic (PV) generators, fuel cells and batteries. The phase output voltage is generated by the sum of the output voltages of each stage, which results in an output phase voltage with nine-levels. In general, if m is the number of levels and N is the number of switching devices in each phase, then the following relation applies:
It can also be applied to three-phase applications with the same principle. This topology uses isolated dc supplies. Therefore, it does not face voltage-balancing problems due to fixed dc voltage values. When compared with a conventional cascaded inverter topology, it requires fewer switching components. Another advantage of the proposed topology is that it requires half the carriers when compared to a conventional SPWM controller. The SPWM for a nine-level CCML inverter consists of eight carriers. However, in this topology, four carriers are sufficient. This is because, according to
Fig. 2
, the level generation part generates only positive polarity voltage levels and does not generate negative voltage levels. Therefore, it implements the multilevel inverter with a reduced number of carriers, which is a great achievement for inverter control. In the CCMLI topology all of the switches should be selected from fast switches. However, the proposed topology does not require fast switches for the polarity generation part.
Fig. 3
presents the three-phase power circuit of the nine-level RSCML inverter. MATLAB/SIMULINK simulation results are obtained for the output phase and line voltages of the three phase nine level RSCMLI with 1KW, 3φ, resistive loads for the various PWM techniques.
Three-phase power circuit of the nine-level RSCMLI.
Comparison of RSCML inverter and CCML inverter.
The
Fig. 4
shows a comparison of the proposed RSCML inverter and a CCML inverter based on the required number of switches and the number of levels. From this comparison, it is clear that as the number of voltage levels, m, grows, the number of active switches increases according to m+2 for the RSCML inverter and 2(m-1) for the CCML inverter. The switching sequence in the nine-level RSCMLI is given in
Table I
to produce the output voltage of the different levels. In general, n-number of isolated dc supply sources are required to produce m-output voltage levels with the cascaded inverter. Based on the various switching sequences given in
Table I
, switching signals are generated for the switches in the RSCML inverter.
SWITCHING SEQUENCES FOR SINGLE PHASE NINE-LEVEL RSCML INVERTER
Each carrier is compared with a corresponding modulating unipolar sine wave. The reference or modulation waveform has peak amplitude A
_{m}
and a frequency f
_{m}
, and it is centered in the middle of the carrier set. The general principle of the carrier based PWM technique is a comparison of a reference waveform with a carrier waveform, this typically being a triangular carrier waveform. The reference is continuously compared with the carrier signal. If the reference is greater than the carrier signal, then the active device corresponding to that carrier is switched on, and if the reference is less than the carrier signal, then the active device corresponding to that carrier is switched off. The carrier frequency defines the switching frequency of the converter and the high order harmonic components of the output voltage spectrum. and the sidebands occur around the carrier frequency and its multiples. In multilevel inverters, the amplitude modulation index, Ma, and the frequency ratio, Mf, are defined as:
Where A
_{r}
and A
_{c}
are the amplitude of the reference and the carrier signal, respectively. f
_{r}
and f
_{c}
are the frequency of the reference and the carrier signal respectively
[22]
.
In this paper, the modulation indexes used are 0.8, 0.9 and 1 for a nine-level RSCML inverter. For multilevel applications, carrier based PWM techniques with multiple carriers are used. Multicarrier Modulation (MCM) techniques, can be divided in to the following categories
[23]
:
The above modulation strategies are implemented for different carriers such as the triangular multicarrier wave, saw tooth multicarrier wave and unipolar sine multicarrier wave. The phase voltage waveform, line voltage waveform and harmonic spectrum of the phase and line voltages are shown for different modulation techniques by doing simulations using MATLAB-SIMULINK for a nine-level RSCMLI and CCMLI. A comparison is done on the obtained results.
Where y
_{c}
is a normalized symmetrical triangular carrier defined as:
where φ represents the phase angle of y
_{c}
. y
_{c}
is a periodic function with the period
It is shown that using a symmetrical triangular carrier generates less harmonic distortion at the inverter’s output
[26]
,
[27]
.
The multicarrier modulation techniques (PD, IPD, POD, and APOD) are implemented using triangular multicarrier signals for a nine-level RSCMLI with different modulation indexes. They are shown in
Fig. 5
(a) and
5
(b), respectively.
(a) PD TMC USPWM with M_{a} =1 for nine-level RSCMLI. (b) POD TMC USPWM with M_{a} = 0.8 for nine-level RSCMLI.
_{c}
. The simulink block sets the input period as the difference between the first and last value of the time values parameter. The output at any time t is the output at time:
Where n is an integer. The sequence repeats at:
The simulink block uses linear interpolation to compute the value of the waveform between the specified output times. In this technique, the gate signals are generated by comparing the saw tooth multicarrier wave with a unipolar sinusoidal modulating signal.
The multicarrier modulation techniques (PD, IPD, POD, and APOD) are implemented using saw tooth multicarrier signals for a nine level RSCMLI with different modulation indexes. They are shown in
Fig. 6
(a) and
6
(b), respectively.
(a) IPD STMC USPWM with M_{a} =1 for nine-level RSCMLI. (b) APOD STMC USPWM with M_{a} = 0.9 for nine-level RSCMLI.
(a) PD USMC USPWM with M_{a} =1 for nine-level RSCMLI. (b) POD USMC USPWM with M_{a} = 0.8 for nine-level RSCMLI.
Where n is the harmonic order, v
_{n}
is the RMS value of the n
^{th}
harmonic component and v
_{1}
is the RMS value of the fundamental component. Here, the %THD is calculated up to a harmonic order which is twice the switching frequency. For a 2 KHz switching frequency, up to the 80
^{th}
order harmonics are taken in to account for calculating the THD. For a 10 KHz switching frequency, up to the 400
^{th}
order harmonics are taken in to account for calculating the THD.
_{a}
=1 .
(a) Phase Voltage for nine-level APOD USPWM with M_{a} =1 . (b) Percentage phase Voltage THD for nine-level APOD USPWM with M_{a} =1.
Table II
shows the percentage phase voltage THD for a nine-level RSCMLI and CCMLI with triangular multicarrier signals with different multicarrier PWM techniques with switching frequencies of 2 KHz and 10 KHz for different modulation indexes.
From
Table II
, it can be observed that when the switching frequency of the RSCMLI is increased, the percentage phase voltage THD increases for the PD scheme with all of the modulation indexes. In the IPD scheme, if the switching frequency is increased, the percentage phase voltage THD decreases with modulation indexes of 1 and 0.8. In the POD scheme, when the switching frequency is increased, the percentage phase voltage THD increases with a modulation index of 1. In the APOD scheme, if the switching frequency is increased, the percentage phase voltage THD decreases with a modulation index of 0.8.
PHASE VOLTAGE % THD FOR NINE-LEVEL RSCMLI AND CCMLI WITH TRIANGULAR MULTI CARRIER USPWM
The results obtained from the nine-level RSCMLI are also compared with those of the CCMLI when the switching frequencies are 2 KHz and 10 KHz (To limit the number of pages, the comparison is done for only for the switching frequency). It is found that in some of the modulation techniques the percentage phase voltage THD slightly increases in the CCMLI. However, the proposed RSCMLI has a reduced number of switches and increases in the fundamental phase and line voltages.
From the simulation results of the triangular multicarrier USPWM technique with the PD and IPD PWM schemes, from the 3
^{rd}
order harmonics to the 21
^{st}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 23
^{rd}
harmonics to the 79
^{th}
harmonics are 1% to 2%. The dominant 39
^{th}
and 41
^{st}
harmonic factors are about 5% for the PD and IPD schemes.
In the POD scheme, from the 3
^{rd}
order harmonics to the 21
^{st}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 23
^{rd}
harmonics to the 55
^{th}
harmonics are 1% to 3%. The dominant 35
^{th}
and 45
^{th}
harmonic factors are 4.77% and 4.88%, respectively, for the POD scheme.
In the APOD scheme, from the 3
^{rd}
order harmonics to the 25
^{th}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 27
^{th}
harmonics to the 69
^{th}
harmonics are 1% to 3%. The dominant 29
^{th}
and 51
^{st}
harmonic factors are 4.67% and 4.61%, respectively, for the APOD scheme.
It is observed that when the switching frequency of the RSCMLI is increased, the percentage line voltage THD increases very slightly and the fundamental phase and line voltage decrease for the all of the PWM schemes.
_{a}
=1.
(a) Phase Voltage for nine-level PD USPWM with M_{a} =1 . (b) Percentage Phase Voltage THD for nine-level PD USPWM with M_{a} = 1 .
Table III
shows the percentage of phase voltage THD for the nine-level RSCML inverter and the CCML inverter with the saw tooth multicarrier signal with different multicarrier PWM techniques with a switching frequency of 2 KHz and 10 KHz, respectively, for different modulation indexes.
From
Table III
, it is observed that when the switching frequency of the RSCMLI is increased, the percentage phase voltage THD decreases for the PD and POD schemes with a modulation index of 1. In the IPD and APOD schemes, if the switching frequency is increased, the percentage phase voltage THD increases for all of the modulation indexes.
PHASE VOLTAGE % THD FOR NINE-LEVEL RSCMLI AND CCMLI WITH SAW TOOTH MULTI CARRIER USPWM
From the simulation result in the saw tooth multicarrier USPWM technique with the PD and IPD PWM schemes, from the 3
^{rd}
order harmonics to the 13
^{th}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 15
^{th}
harmonics to the 79
^{th}
harmonics are 1% to 2%. The dominant 39
^{th}
and 41
^{st}
harmonic factors are about 4% for the PD and IPD schemes.
In the POD scheme, from the 3
^{rd}
order harmonics to the 13
^{th}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 15
^{th}
harmonics to the 79
^{th}
harmonics are 1% to 3%. The dominant 35
^{th}
and 45
^{th}
harmonic factors are 4.10% and 4.75%, respectively, for the POD scheme.
In the APOD scheme, from the 3
^{rd}
order harmonics to the 13
^{th}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 15
^{th}
harmonics to the 79
^{th}
harmonics are 1% to 3%. The dominant 29
^{th}
and 51
^{st}
harmonic factors are 4.26% and 4.55%, respectively, for the APOD scheme.
It is observed that when the switching frequency of the RSCML inverter is increased, the percentage line voltage THD decreases and the fundamental phase and line voltage increase for the PD scheme. In the IPD and APOD schemes, if the switching frequency is increased, the percentage line voltage THD increases and the fundamental phase and line voltage decrease. In the POD scheme, when the switching frequency is increased, the percentage line voltage THD and the fundamental phase and line voltage increase. The fundamental line voltage is maximum for the PD and POD schemes and minimum for the IPD and APOD schemes.
_{a}
=1 .
(a) Line Voltage for nine-level IPD USPWM with M_{a} =1 . (b). Percentage Line Voltage THD for nine-level IPD USPWM with M_{a} =1 .
Table IV
shows the percentage phase voltage THD for the nine-level RSCML inverter and the CCML inverter with a unipolar sine multicarrier signal with different multicarrier PWM techniques with switching frequencies of 2 KHz and 10 KHz, respectively, for different modulation indexes.
From
Table IV
, it is observed that when the switching frequency of the RSCMLI is increased, the percentage line voltage THD increases for the PD, IPD, POD and APOD schemes with all of the modulation indexes.
PHASE VOLTAGE % THD FOR NINE-LEVEL RSCMLI AND CCMLI WITH UNIPOLAR SINE MULTI CARRIER USPWM
From the simulation results of the unipolar sine multicarrier USPWM technique PD PWM scheme, from the 3
^{rd}
order harmonics to the 17
^{th}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 19
^{th}
harmonics to the 77
^{th}
harmonics are 1% to 2%. The dominant 79
^{th}
harmonic factor is 7.03% for the PD scheme.
In the IPD scheme, from the 3
^{rd}
order harmonics to the 21
^{st}
order harmonics and from the 25
^{th}
order harmonics to the 55
^{th}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 57
^{th}
harmonics to the 77
^{th}
harmonics are 1% to 2%. The dominant 79
^{th}
harmonic factor is 5.13% for the IPD scheme.
In the POD scheme, from the 3
^{rd}
order harmonics to the 15
^{th}
order harmonics and from the 21
^{st}
order harmonics to the 55
^{th}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 57
^{th}
harmonics to the 77
^{th}
harmonics are 1% to 2%. The dominant 75
^{th}
and 79
^{th}
harmonic factors are 5.17% and 3.49%, respectively, for the POD scheme.
In the APOD scheme, from the 3
^{rd}
order harmonics to the 7
^{th}
order harmonics and from the 25
^{th}
order harmonics to the 55
^{th}
order harmonics are less than 1% and all of the even order harmonics are zero. A few of the odd order harmonics from the 57
^{th}
harmonics to the 77
^{th}
harmonics are 1% to 2%. The dominant 69
^{th}
and 73
^{rd}
harmonic factors are 5.15% and 3.23%, respectively, for the APOD scheme.
It is observed that, when the switching frequency of the RSCML inverter is increased, the percentage line voltage THD increases and the fundamental phase and line voltage increase for the PD scheme. In the IPD scheme, if the switching frequency is increased, the percentage line voltage THD increases and the fundamental phase and line voltage decrease. In the POD and APOD schemes, when the switching frequency is increased, the percentage line voltage THD increases and the fundamental phase and line voltage decrease. In addition, the fundamental line voltage is maximum for the IPD and POD schemes and is minimum for the PD and APOD schemes. M
_{a}
=1
Table V
shows the percentage line voltage THD, fundamental phase and line voltage and dominant harmonic factors obtained for the nine-level RSCMLI with different multicarrier PWM techniques with switching frequencies of 2 KHz and 10 KHz with modulation index of unity.
PERFORMANCE ANALYSIS OF NINE-LEVEL RSCMLI WITH M_{a}=1
From
Table V
, it is observed that when the switching frequency is 2 KHz, the unipolar sine (IPD) scheme gives maximum phase and line voltage and the triangular (PD) scheme gives minimum % THD for the line voltage. If the switching frequency is 10 KHz, the unipolar sine (IPD) scheme gives maximum phase and line voltage and the saw tooth (PD) scheme gives minimum % THD for the line voltage.
_{a}
= 0.9.
Nine-level RSCMLI Experimental setup.
(a) Phase Voltage for nine-level TMC PD USPWM with M_{a} =1. (b) Harmonics spectrum for nine-level TMC PD USPWM with M_{a} =1 .
Phase Voltage for nine-level STMC PD USPWM with M_{a} = 0.9 .
Fig. 14
shows the phase voltage waveform for a nine-level RSCMLI using the phase disposition technique for the unipolar sine multi carrier unipolar sinusoidal PWM with M
_{a}
= 0.8 . Due to the switching and ohmic losses of the converter switches, the peak value of the ac output voltage is found to be 96V. By varying the amplitude of the modulating signal, the RMS output phase voltage can be varied from 0V to 76V.
Phase Voltage for nine-level USMC PD USPWM with M_{a} = 0.8 .
EXPERIMENTAL ANALYSIS OF NINE-LEVEL RSCMLI
Table VI
shows the fundamental phase voltage and percentage THD of the phase voltage obtained experimentally for a nine-level RSCMLI with the different multicarrier PWM techniques with a switching frequency of 2 KHz with different modulation indexes. From the above table, it is observed that in all of the multicarrier PWM schemes, if the modulation index is decreased, the phase voltage decreases and the percentage phase voltage THD increases. From the experimental results the saw tooth multicarrier scheme gives the maximum output phase voltage and the triangular multicarrier gives minimum % THD for the phase voltage.
R. Nagarajan received his B.E. in Electrical and Electronics Engineering from Madurai Kamarajar University, Madurai, India, in 1997. He received his M.E. in Power Electronics and Drives from Anna University, Chennai, India, in 2008. He is currently working toward his Ph.D. in Power Electronics at Anna University, Tamilnadu, India. He has worked in the industry as an Electrical Engineer. He is currently working as an Associate Professor at the Raja College of Engineering and Technology, Madurai, Tamilnadu, India. His current research interest include multilevel inverters.
M. Saravanan received his B.E from Madurai Kamarajar University, Madurai, India, in 1991. He received his M.E. from the Coimbatore Institute of Technology, Coimbatore, India, in 1992. He received his Ph.D. From Madurai Kamarajar University, in 2007. He is currently working as a Professor of Electrical and Electronics Engineering at the Thiagarajar College of Engineering, Madurai, Tamilnadu, India. His current research interests include power electronics and renewable energy sources.

Modulation Index (MI)
;
Unipolar Sinusoidal Pulse Width Modulation (USPWM)
;
Saw Tooth Multicarrier USPWM (STMC USPWM)
;
Total Harmonic Distortion (THD)
;
Triangular Multicarrier USPWM (TMC USPWM)
;
Unipolar Sine Multicarrier USPWM (USMC USPWM)

I. INTRODUCTION

Multilevel power conversion was first introduced more than two decades ago. The general concept involves utilizing a higher number of active semiconductor switches to perform power conversion in small voltage steps. There are several advantages to this approach when compared with the conventional power conversion approach. The smaller voltage steps lead to the production of higher power quality waveforms, and they reduce both the voltage (
II. CONVENTIONAL CASCADED MULTILEVEL INVERTER

The single-phase structure of a three-phase nine-level conventional cascaded inverter is illustrated in
Fig 1
. Each separate dc source is connected to a single-phase full-bridge or H-bridge inverter. Each inverter level can generate three different voltage outputs, +V
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III. PROPOSED REDUCED SWITCH CASCADED MULTILEVEL INVERTER TOPOLOGY

In conventional multilevel inverters, the power semiconductor switches are combined to produce a high-frequency waveform in positive and negative polarities. However, there is no need to utilize all of the switches for generating bipolar levels. This idea has been put into practice by the novel topology.
This topology is a hybrid multilevel inverter topology which uses two parts to generate the output voltage. One part is named the level generation part and it is responsible for the generation of different voltage levels. This part requires high-frequency switches to generate the required levels. The switches in this part should have high-switching-frequency capability. The other part is called the polarity generation part and it is responsible for generating the polarity of the output voltage. The polarity generation part operates at a low-frequency (line frequency). The proposed topology combines the two parts (high frequency and low frequency parts) to generate the multilevel voltage output. In order to generate a complete multilevel output, the positive levels are generated by the high-frequency part (level generation). Then, this part’s output voltage is fed to a full-bridge cascaded inverter (polarity generation), which will generate the required polarity for the output. This eliminates many of the semiconductor switches which were responsible for generating the output voltage levels in positive and negative polarities in conventional cascaded multilevel inverters.
The proposed RSCMLI topology in the single phase structure of nine-levels is shown in
Fig. 2
. As can be seen, it requires eleven switches and four isolated sources. The principal idea of this topology is that the left circuit in
Fig. 2
generates the required output levels (without polarity) and the right circuit cascaded inverter (full-bridge inverter) determines the polarity of the output voltage. This part, which is named the polarity generation part, transfers the required output level to the output with the same direction or the opposite direction according to the required output polarity.
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SWITCHING SEQUENCES FOR SINGLE PHASE NINE-LEVEL RSCML INVERTER

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IV. MODULATION TECHNIQUES

Pulse Width Modulation (PWM) control strategy development tries to reduce the total harmonic distortion (THD) of the output voltage. Increasing the switching frequency of the PWM pattern reduces the lower frequency harmonics by moving the switching frequency carrier harmonic and the associated sideband harmonics away from the fundamental frequency component
[21]
. This increased switching frequency reduces harmonics. This results in a lower THD with high quality output voltage waveforms of the desired fundamental RMS value and frequency, which are as close as possible to the sinusoidal wave shape.
Any deviation from the sinusoidal wave shape will result in harmonic currents in the load and this harmonic current produces electromagnetic interference (EMI), harmonic losses and torque pulsation in the case of motor drives. A higher switching frequency can be employed for low and medium power inverters. Meanwhile, for high power and medium voltage applications the switching frequency should be low. Harmonic reduction can then be strictly related to the performance of an inverter with any switching strategy.
Three phase multilevel inverters require three modulating signals or reference signals which are three-unipolar sine waves with a 120 degree phase shift. In this paper, three new carrier based PWM techniques are developed as follows:
- 1. Triangular Multicarrier Unipolar Sine PWM(TMC USPWM)
- 2. Saw Tooth Multicarrier Unipolar Sine PWM(STMC USPWM)
- 3. Unipolar Sine Multicarrier Unipolar Sine PWM(USMC USPWM)

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- 1. Phase Disposition (PD) where all of the carriers are in phase.
- 2. Inverted Phase Disposition (IPD) where all of the carriers are in phase and inverted.
- 3. Phase Opposition Disposition (POD) where the carriers above half of the reference are in phase but shifted by 180 degrees from those carriers below half of the reference.
- 4 Alternative Phase Opposition Disposition (APOD) where each carrier band is shifted by 180 degrees from the adjacent carrier band[24].

- A. Triangular Multicarrier Unipolar Sinusoidal PWM (TMC USPWM)

The performance of a multilevel inverter is based on the multi carrier modulation technique used. Two-level to multilevel inverters are made using several triangular carrier signals and one reference signal per phase. Carrara
[25]
developed multilevel sub harmonic PWM (SH-PWM), which is as follows:
For m-level inverters, (m-1)/2 carriers with the same frequency fc and the same amplitude Ac are disposed such that the bands they occupy are contiguous. They are defined as:
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- B. Saw Tooth Multicarrier Unipolar Sinusoidal PWM (STMC USPWM)

The saw tooth wave is a periodic signal which is generated arbitrarily and can be obtained from the repeated sequence carrier wave by limiting its magnitude to A
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- C. Unipolar Sine Multicarrier Unipolar Sinusoidal PWM (USMC USPWM)

In this PWM technique, the sinusoidal signal is converted into a unipolar sinusoidal signal. The entire negative half cycles in the waveform are converted into positive half cycles with the same amplitude and frequency. This signal is the same as that of the full wave rectifier output. That is the signal has only continuous positive half cycles. This is called the unipolar sine wave.
The control strategy uses the same signal for the reference (synchronized unipolar sinusoidal signal) and carrier signals. The control scheme uses a high frequency unipolar sine carrier that helps maximize the output voltage for a given modulation index.
The multicarrier modulation techniques (PD, IPD, POD, and APOD) are implemented using unipolar sine multicarrier signals for a nine level RSCMLI with different modulation indexes. They are shown in
Fig 7
(a) and
7
(b), respectively.
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V. SIMULATION RESULTS

The nine level RSCML inverter model with different modulation indexes was implemented in MATLAB/SIMULINK software to demonstrate the feasibility of the PWM techniques. The phase disposition, inverted phase disposition, phase opposition disposition and alternative phase opposition disposition techniques are used for the various multicarrier USPWM techniques such as:
1. Triangular Multicarrier Unipolar Sine PWM (TMC USPWM)
2. Saw Tooth Multicarrier Unipolar Sine PWM (STMC USPWM)
3. Unipolar Sine Multicarrier Unipolar Sine PWM (USMC USPWM)
The phase and line voltage waveform with its harmonic spectrum at a fundamental frequency of 50Hz and switching frequencies (SF) of 2 KHz and 10 KHz are obtained for the proposed RSCML inverter. For comparison, the total harmonic distortion (THD) was evaluated for all of the modulation techniques. In order to get the THD level of the waveform, a Fast Fourier Transform (FFT) was applied to obtain the spectrum of the output voltage
[28]
. The THD was calculated using the following equation:
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- A. Triangular Multicarrier USPWM (TMC USPWM)

Fig 8
(a) and
8
(b) show the phase voltage waveforms and the percentage THD of the phase voltage for the nine-level APOD USPWM using the alternative phase opposition disposition technique for triangular multicarrier unipolar sinusoidal PWM with M
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PHASE VOLTAGE % THD FOR NINE-LEVEL RSCMLI AND CCMLI WITH TRIANGULAR MULTI CARRIER USPWM

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- B. Saw Tooth Multicarrier USPWM (STMC USPWM)

Fig 9
(a) and
9
(b) show the phase voltage waveforms and the percentage THD of the phase voltage for the nine level PD USPWM using the phase disposition technique for the saw tooth multicarrier unipolar sinusoidal PWM with M
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PHASE VOLTAGE % THD FOR NINE-LEVEL RSCMLI AND CCMLI WITH SAW TOOTH MULTI CARRIER USPWM

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- C. Unipolar Sine Multicarrier USPWM (USMC USPWM)

Fig 10
(a) and
10
(b) show the line voltage waveforms and the percentage THD of the line voltage for the nine level IPD USPWM using the inverted phase disposition technique for the unipolar sine multicarrier unipolar sinusoidal PWM with M
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PHASE VOLTAGE % THD FOR NINE-LEVEL RSCMLI AND CCMLI WITH UNIPOLAR SINE MULTI CARRIER USPWM

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PERFORMANCE ANALYSIS OF NINE-LEVEL RSCMLI WITH Ma=1

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VI. EXPERIMENTAL RESULTS

In order to experimentally validate the proposed multicarrier PWM techniques, a prototype 100W, 96V, single phase nine-level RSCMLI was constructed using MOSFETs as the switching devices. The MOSFETs, ramp generator, comparator and diodes used are IRF840, UA741, LM324 and IN5408, respectively. The source voltage is 24V for each of the DCMLIs. In total 96V DC is applied across the input side of the nine-level RSCMLI. The RSCMLI output provides power to a 100W resistive load. A picture of the laboratory experimental prototype, built to verify the operation and to obtain the phase voltage of the different multicarrier phase disposition USPWM techniques is shown in
Fig. 11
. The prototype includes a nine-level RSCMLI circuit and measurement equipment.
Fig. 12
(a) and
12
(b) show the phase voltage waveform and the harmonics spectrum of the phase voltage for a nine-level RSCMLI using the phase disposition technique for the triangular multi carrier unipolar sinusoidal
Fig. 13
shows the phase voltage waveform for a nine-level RSCMLI using the phase disposition technique for the saw tooth multi carrier unipolar sinusoidal PWM with M
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EXPERIMENTAL ANALYSIS OF NINE-LEVEL RSCMLI

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VII. CONCLUSION

In this paper, a novel reduced switch cascaded multilevel inverter (RSCMLI) topology has been proposed which has superior features when compared with the conventional cascaded multilevel inverter (CCMLI) topology in terms of the minimum number of required power switches, control requirements, cost, and reliability. This topology can be a good candidate for the inverters used in power applications such as FACTS, HVDC, PV systems, UPS, etc. In the proposed topology, the switching operation is separated into high-frequency and low-frequency parts. This increases the efficiency of the inverter and reduces the size and cost of the final prototype.
In this paper, the performance of different multicarrier PWM techniques which use the triangular multicarrier waveform, saw tooth multicarrier waveform and unipolar sine multicarrier waveform are determined. In all of the above PWM techniques, different modulation strategies such as the phase disposition (PD), inverted phase disposition (IPD), phase opposition disposition (POD) and alternative phase opposition disposition (APOD) are implemented. The results are verified through simulations for a 1KW, 3φ nine-level RSCMLI in MATLAB/SIMULINK. The output quantities such as the fundamental phase and line voltage, percentage THD of the phase voltage, line voltage and percentage dominant harmonic factor are measured in the all of the above PWM schemes and the results are compared. Experimental results of the developed prototype for a single phase nine-level RSCMLI of the proposed topology are obtained for the different multicarrier PWM techniques. The USPWM control method is used to drive the inverter. The PWM for this topology has fewer complexities since it generates only the positive carriers for PWM control. The results clearly show that the proposed topology can effectively work as a multilevel inverter with a reduced number of switches and carriers for PWM.
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Citing 'Performance Analysis of a Novel Reduced Switch Cascaded Multilevel Inverter
'

@article{ E1PWAX_2014_v14n1_48}
,title={Performance Analysis of a Novel Reduced Switch Cascaded Multilevel Inverter}
,volume={1}
, url={http://dx.doi.org/10.6113/JPE.2014.14.1.48}, DOI={10.6113/JPE.2014.14.1.48}
, number= {1}
, journal={Journal of Power Electronics}
, publisher={The Korean Institute of Power Electronics}
, author={Nagarajan, R.
and
Saravanan, M.}
, year={2014}
, month={Jan}