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New Three-Level PWM DC/DC Converter – Analysis, Design and Experiments
New Three-Level PWM DC/DC Converter – Analysis, Design and Experiments
Journal of Power Electronics. 2014. Jan, 14(1): 30-39
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : May 24, 2013
  • Accepted : October 30, 2013
  • Published : January 30, 2014
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About the Authors
Bor-Ren Lin
linbr@yuntech.edu.tw
Chih-Chieh Chen
Dept. of Electrical Eng., National Yunlin University of Science and Technology, Yunlin, Taiwan

Abstract
This paper studies a new three-level pulse-width modulation (PWM) resonant converter for high input voltage and high load current applications. In order to use high frequency power MOSFETs for high input voltage applications, a three-level DC converter with two clamped diodes and a flying capacitor is adopted in the proposed circuit. For high load current applications, the secondary sides of the proposed converter are connected in parallel to reduce the size of the magnetic core and copper windings and to decrease the current rating of the rectifier diodes. In order to share the load current and reduce the switch counts, three resonant converters with the same active switches are adopted in the proposed circuit. Two transformers with a series connection in the primary side and a parallel connection in the secondary side are adopted in each converter to balance the secondary side currents. To overcome the drawback of a wide range of switching frequencies in conventional series resonant converters, the duty cycle control is adopted in the proposed circuit to achieve zero current switching (ZCS) turn-off for the rectifier diodes and zero voltage switching (ZVS) turn-on for the active switches. Finally, experimental results are provided to verify the effectiveness of the proposed converter.
Keywords
I. INTRODUCTION
For three-phase 380V or 480V systems, an AC/DC converter with power factor correction (PFC) is needed in the front stage for reducing current harmonics at the utility side in order to meet international standards (IEC 61000-3-2 or IEEE 519). Thus, the DC bus voltage after the AC/DC converter is greater than 540V or 680V. In order to use MOSFETs instead of IGBTs in the second DC/DC converter stage with a high switching frequency and high power density demand, three-level circuit topologies [1] - [4] have been proposed for high input voltage and medium/high power applications. Soft switching three-level converters have been presented in [5] - [10] to reduce the switching losses at a desired load range. These techniques are based on an additional auxiliary circuit to extend the zero voltage switching (ZVS) range or using the leakage inductance (or external inductance) and the output capacitance of the MOSFETs to turn on the active switches under ZVS. However, the rectifier diodes at the secondary side have reverse recovery losses. Series resonant converters [11] - [16] have been proposed to have the features of ZVS turn-on for power switches and ZCS turn-off for rectifier diodes within a wide range of input voltage and load conditions when the switching frequency is less than the series resonant frequency. The main drawback of series resonant converters is the wide range of switching frequencies from light load to full load. Thus, the magnetic components in the circuit are not easy to design at the optimal condition. In order to keep the advantages of series resonant converters and operate at a fixed switching frequency, the resonant converter has a better ability to operate at duty cycle control with soft switching features such as ZVS for the MOSFETs and ZCS for the fast recovery diodes. For high load current applications such as high power battery chargers, parallel three-level converters are normally adopted.
This paper proposes a new three-level PWM resonant converter with ZVS/ZCS for high input voltage and high load current applications. A three-level DC converter with two clamped diodes and one flying capacitor is used to limit the voltage stress of the power switches at Vin /2. Three PWM resonant converters with the same power switches are used to share the load current for high load current applications. Thus, the switch counts in the proposed circuit are reduced when compared with conventional parallel three-level DC/DC converters. A series resonant converter is adopted in the transformer primary side and the switching frequency is less than the series resonant frequency. Thus, all of the active switches are turned on under ZVS and the rectifier diodes are turned off under ZCS. Duty cycle control instead of frequency modulation (FM) control is adopted to regulate the output voltage. Thus, the drawback of a wide range of switching frequencies in conventional resonant converters is overcome. Finally, experiments are provided to verify the operation principle of the proposed converter.
II. CIRCUIT CONFIGURATION
The circuit configuration of the proposed converter is shown in Fig. 1 for medium/high input voltage and high load current applications. The proposed circuit includes three ZVS DC converters connected in parallel. The first DC converter consists of Cin1 , Cin2 , Da , Db , Cf , S1 - S4 , C1 - C4 , Cr1 , Lr1 , T1 - T2 , D1 - D4 , Co and Ro . The second DC converter includes the components of Cin1 , Cin2 , Da , Db , Cf , S1 - S4 , C1 - C4 , Cr2 , Lr2 , T3 - T4 , D5 - D8 , Co and Ro . In the same manner, the components Cin1 , Cin2 , Da , Db , Cf , S1 - S4 , C1 - C4 , Cr3 , Lr3 , T5 - T6 , D9 - D12 , Co and Ro are included in the third DC converter. The input capacitances, Cin1 and Cin2 , are equal and large enough to be two input voltage sources vCin1 = vCin2 = Vin /2. S1 - S4 are power MOSFETs with Vin /2 voltage stress. C1 - C4 are the output capacitances of S1 - S4 , respectively. Da and Db are the clamped diodes. Cf is a flying capacitor with Vin /2 average voltage. Cr1 - Cr3 are the series resonant capacitors, and Lr1 - Lr3 are the series resonant inductances. Lm1 - Lm6 are the magnetizing inductances of T1 - T6 , respectively. D1 - D12 are the rectifier diodes. Ro is the load resistance, and Co is the output capacitance. These three DC converters share the same components in terms of S1 - S4 , Da , Db , and Cf . In each of the DC converters, the two transformers are connected in series at the primary side and connected in parallel at the secondary side so that the two secondary side currents are balanced for high load current applications. The PWM signals of S1 and S4 are complementary each other with a dead time to allow for ZVS operation. Similarly, the PWM signals of S2 and S3 are complementary each other. Based on the operations of S1 - S4 , there are three voltage levels Vin , Vin /2 and 0 generated on the AC terminal voltages vab , vbc and vbo . Each center-tapped diode rectifier supplies one-sixth of the load current. Thus, the current stresses of each of the transformer secondary windings and the rectifier diodes are reduced.
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Circuit configuration of the proposed resonant converter.
III. OPERATION PRINCIPLE
The key waveforms of the proposed resonant converter are shown in Fig. 2 . The duty cycle of the active switches S1 - S4 is equal to 0.5. The PWM signals of S2 and S3 are phase-shifted with respective to the PWM signals of S1 and S4 , respectively. The duty cycle of the AC side voltages vab , vbc and vbo is regulated to keep the output voltage at a desired value against load variations and input voltage changes. Before the system analysis, the following assumptions are made in the proposed converter. (1) VCin1 and VCin2 are balanced voltage sources; (2) C1 = C2 = C3 = C4 Coss , Cr1 = Cr2 = Cr3 Cr and Cr > Coss ; (3) the average capacitor voltages VCr3 =0 and VCr1 = VCr2 = VCf = Vin /2; (4) Vo is the constant output voltage; (5) Lm1 = Lm2 = Lm3 = Lm4 = Lm5 = Lm6 Lm , Lr1 = Lr2 = Lr3 Lr and Lr << Lm ; (6) the turns ratio of T1 - T6 is n = np / ns1 = np / ns2 ; and (7) the MOSFETs, S1 - S4 , and diodes, D1 - D12 and Da - Db , are ideal. Based on the on/off states of S1 - S4 , Da - Db and D1 - D12 , the proposed converter has ten operating modes in a switching cycle. Fig. 3 gives the equivalent circuits of these operating modes. Prior to t0 , S1 is conducting. The inductor current iLr1 is positive and iLr2 is negative.
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Key waveforms of the proposed converter.
Mode 1 [t0t<t1, Fig. 3(a)]: At t0 , C2 is discharged to zero voltage. Since iLr2 ( t0 )+ iLr3 ( t0 )- iLr1 ( t0 )<0, the anti-parallel diode of S2 is conducting. Thus, S2 can be turned on at this moment under ZVS. The AC terminal voltages vab =0, vbc = Vin and vbo = Vin /2. Diodes D2 , D4 , D5 , D7 , D9 and D11 are conducting in this mode. Magnetizing voltages vLm1 = vLm2 =- nVo and vLm3 = vLm4 = vLm5 = vLm6 = nVo . Thus, iLm1 and iLm2 decrease and iLm3 - iLm6 increase in this mode. Lr1 and Cr1 are resonant with the applied voltage 2 nVo , Lr2 and Cr2 are resonant with the applied voltage Vin -2 nVo , and Lr3 and Cr3 are resonant with the applied voltage Vin /2-2 nVo . In this mode, iLr1 - iLr3 and vCr1 - vCr3 are expressed as:
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where
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In this mode, iLr1 and vCr1 are both decreasing, and iLr2 - iLr3 and vCr2 - vCr3 are increasing. Power is transferred from Vin to Ro through S1 , S2 , T3 - T6 , Lr2 - Lr3 , Cr2 - Cr3 , D5 , D7 , D9 , D11 and Co .
Mode 2 [t1t<t2, Fig. 3(b)]: At t1 , S1 is turned off. Since iLr2 ( t1 ) and iLr3 ( t1 ) are positive and iLr1 ( t1 ) is negative, C1 is charged linearly and C4 is discharged linearly. The rising slope of the drain-to-source voltage of S1 is limited by C1 and C4 . Thus, S1 is turned off under ZVS. Capacitor C4 can be discharged to zero voltage if the energy stored in Lr1 - Lr3 is greater than the energy stored in C1 and C4 . Therefore, the ZVS condition of S4 is expressed as:
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Mode 3 [t2t<t3, Fig. 3(c)]: At t2 , C4 is discharged to zero voltage. Since iLr2 ( t2 ) and iLr3 ( t2 ) are positive and iLr1 ( t2 ) is negative, the anti-parallel diode of S4 is conducting. Thus, S4 is turned on at this moment under ZVS. The AC terminal voltages vab = vbc = Vin /2 and vbo =0. Since diodes D2, D4 , D5 , D7 , D9 and D11 are still conducting, the magnetizing currents iLm1 and iLm2 decrease and iLm3 - iLm6 increase in this mode. Lr1 and Cr1 are resonant with the applied voltage Vin /2+2 nVo . In the same manner, Lr2 and Cr2 are resonant with the applied voltage Vin /2-2 nVo , and Lr3 and Cr3 are resonant with the applied voltage -2 nVo . In this mode, iLr1 - iLr3 and vCr1 - vCr3 are given as:
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The flying capacitor voltage vCf = vCin2 = Vin /2.
Mode 4 [t3t<t4, Fig. 3(d)]: At t3 , iLm1 = iLm2 = iLr1 , iLm3 = iLm4 = iLr2 and iLm5 = iLm6 = iLr3 . Thus, diodes D1 - D12 are all in the off-state. Cr1 , Lr1 , Lm1 and Lm2 are resonant with the applied voltage Vin /2. In the same manner, Cr2 , Lr2 , Lm3 and Lm4 are resonant with the applied voltage Vin /2, and Cr3 , Lr3 , Lm5 and Lm6 are resonant. In this mode, iLr1 - iLr3 and vCr1 - vCr3 are expressed as:
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where
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Mode 5 [t4t<t5, Fig. 3(e)]: At t4 , S2 is turned off. Since iLr2 ( t4 ) and iLr3 ( t4 ) are positive and iLr1 ( t4 ) is negative, C2 is charged and C3 is discharged linearly. The rising slope of the drain-to-source voltage of S2 is limited by C2 and C3 . Thus, S2 is turned off under ZVS. Capacitor C3 can be discharged to zero voltage if the energy stored in Lr1 - Lr3 and Lm1 - Lm6 is greater than the energy stored in C2 and C3 . Therefore, the ZVS condition of S3 is given as:
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Mode 6 [t5t<t6, Fig. 3(f)]: At t5 , C3 is discharged to zero voltage. Since iLr2 ( t5 ) and iLr3 ( t5 ) are positive and iLr1 ( t5 ) is negative, the anti-parallel diode of S3 is conducting. Thus, S3 is turned on at this moment under ZVS. The AC terminal voltages vab = Vin , vbc =0 and vbo =- Vin /2. Diodes D1 , D3 , D6 , D8 , D10 and D12 are conducting in this mode. Thus, the magnetizing voltages vLm1 = vLm2 = nVo and vLm3 = vLm4 = vLm5 = vLm6 =- nVo so that iLm1 and iLm2 increase and iLm3 - iLm6 decrease. Lr1 and Cr1 are resonant with the applied voltage Vin -2 nVo . In the same manner, Lr2 and Cr2 are resonant with the applied voltage 2 nVo , and Lr3 and Cr3 are resonant with the applied voltage - Vin /2+2 nVo .
Mode 7 [t6t<t7, Fig. 3(g)]: At t6 , S4 is turned off. Since iLr2 ( t6 ) and iLr3 ( t6 ) are negative and iLr1 ( t6 ) is positive, C1 is discharged linearly and C4 is charged linearly. The rising slope of the drain-to-source voltage of S4 is limited by C1 and C4 so that S4 is turned off under ZVS. Capacitor C1 can be discharged to zero voltage if the energy stored in Lr1 - Lr3 is greater than the energy stored in C1 and C4 . Thus, the ZVS condition of S1 is given as:
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Mode 8 [t7t<t8, Fig. 3(h)]: At t7 , capacitor C1 is discharged to zero voltage. Since iLr2 ( t7 ) and iLr3 ( t7 ) are negative and iLr1 ( t7 ) is positive, the anti-parallel diode of S1 is conducting. S1 is turned on at this moment under ZVS. The AC terminal voltages vab = vbc = Vin /2 and vbo =0. Since diodes D1 , D3 , D6 , D8 , D10 and D12 are still conducting, iLm1 and iLm2 increase and iLm3 - iLm6 decrease. Lr1 and Cr1 are resonant with the applied voltage Vin /2-2 nVo . In the same manner, Lr2 and Cr2 are resonant with the applied voltage Vin /2+2 nVo , and Lr3 and Cr3 are resonant with the applied voltage 2 nVo in this mode. The flying capacitor voltage vCf = vCin1 = Vin /2.
Mode 9 [t8t<t9, Fig. 3(i)]: At t8 , iLm1 = iLm2 = iLr1 , iLm3 = iLm4 = iLr2 and iLm5 = iLm6 = iLr3 . Thus, D1 - D12 are all in the off-state. Cr1 , Lr1 , Lm1 and Lm2 are resonant with the applied voltage Vin /2. Similarly, Cr2 , Lr2 , Lm3 and Lm4 are resonant with the applied voltage Vin /2, and Cr3 , Lr3 , Lm5 and Lm6 are resonant in this mode.
Mode 10 [t9t<t0, Fig. 3(j)]: At t9 , S3 is turned off. Since iLr2 ( t9 ) and iLr3 ( t9 ) are negative and iLr1 ( t9 ) is positive, C2 is discharged and C3 is charged linearly. The rising slope of the drain-to-source voltage of S3 is limited by C2 and C3 so that S3 is turned off under ZVS. Capacitor C2 can be discharged to zero voltage if the energy stored in Lr1 - Lr3 and Lm1 - Lm6 is greater than the energy stored in C2 and C3 . The ZVS condition of S2 is given as:
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At t0 , C2 is discharged to zero voltage and the anti-parallel diode of S2 is conducting. Then, the operations of the proposed converter in a switching cycle are complete.
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Operation modes of the proposed converter during one switching cycle (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6 (g) mode 7 (h) mode 8 (i) mode 9 (j) mode 10.
IV. CIRCUIT CHARACTERISTICS
Since the time intervals in modes 2, 5, 7 and 10 are much less than the time periods in the other modes, only modes 1, 3, 4, 6, 8 and 9 are discussed in this section in order to derive the circuit characteristics of the proposed converter. In modes 1, 3, 6 and 8, the proposed converter is resonant at the series resonant frequency fr by Lr and Cr . In modes 4 and 9, the converter is resonant at the frequency
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Since a quasi square voltage waveform is generated at the AC terminal voltages vab , vbc and vbo , the maximum duty ratio of vab , vbc and vbo is equal to 0.5. Thus, the AC voltage gain of the proposed resonant converter with a maximum duty ratio of 0.5 can be expressed in (23) based on the fundamental frequency analysis.
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where k = Lr /(2 Lm ), Rac = 48 n 2 Ro 2 ,
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and fs is the switching frequency. The maximum DC voltage gain of the proposed converter can be obtained at the minimum input voltage case.
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where Vf is the voltage drop on D1 - D12 . If the duty ratio of the AC terminal voltages vab , vbc and vbo is less than 0.5, then the DC voltage gain of the proposed converter is less than Gdc,max . The DC voltage gain of the proposed converter is a nonlinear function of the duty cycle of the AC terminal voltages, the initial resonant inductor current and the initial resonant capacitor voltage. Thus, it is difficult to obtain the voltage conversion ratio in a closed form at the steady state. If the duty cycle of the AC terminal voltages is equal to 0.5, then the AC voltage gain of the proposed converter at the switching frequency can be obtained from (23) with the given parameters k , Q , fs and fr . Therefore, the necessary turns ratio of the isolated transformers T1 - T6 is expressed as:
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Since the selected switching frequency fs is less than the series resonant frequency fr in the resonant tank, the active switches S1 - S4 can be turned on under ZVS and the rectifier diodes can be turned off under ZCS. If the duty cycle of the AC terminal voltages vab , vbc and vbo is equal to 0.5, the peak magnetizing current Im can be expressed as:
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Since | iLr1 ( t4 )|= | iLr2 ( t4 )|=| iLr3 ( t4 )|= Im , the minimum resonant inductance to achieve ZVS turn-on for S1 - S4 can be obtained from (7), (20) and (26).
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The average voltages of Cr1 , Cr2 and Cf are equal to Vin /2 and the average voltage of Cr3 is equal to zero. The voltage stress of the active switches is equal to Vin /2 in the proposed converter. The voltage stress and the average current of the rectifier diodes D1 - D12 are equal to 2( Vo + Vf ) and Io /12, respectively.
V. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS
In this section, a design example and test results are provided to demonstrate the converter performance. The circuit specifications of a scale-down laboratory prototype are: Vin =550V-600V, Vo =24V, Io,rated =60A, series resonant frequency fr =125kHz, switching frequency fs =100kHz, k =0.14 and Q =0.2. The designed maximum AC gain of the LLC converter is at the minimum input voltage and full load condition. If the input voltage is increased or the output load is decreased, then the duty cycle is decreased. Thus, a normal duty cycle control PWM IC can be used to regulate the output voltage. Therefore, the requirement turns ratio of T1 - T6 can be obtained under the minimum input voltage case.
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The primary and secondary winding turns of T1 - T6 are 30 turns and 5 turns, respectively. The AC equivalent resistance Rac at full load is obtained as:
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The series resonant inductance and the resonant capacitance are obtained as:
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The magnetizing inductances of T1 - T6 are given as:
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The selected flying capacitance Cf is 0.4 μ F. The output capacitance Co is 4000 μ F. The voltage stress of the power switches S1 - S4 is equal to 300V. In the laboratory, the commercially available MOSFET with at least 300V voltage stress for the power switches S1 - S4 is an IRFP460 which has 500V voltage stress and 20A current stress. The voltage stress and average current of the rectifier diodes D1 - D12 are given as:
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Thus, 30CPQ150 fast recovery diodes with 150V voltage stress, 30A current stress and 0.78V voltage drop are used for D1 - D12 . 30ETH06 fast recovery diodes with 600V voltage stress and 30A current stress are used for the clamped diodes Da and Db . A UCC3895 commercial PWM IC is adopted to generate the necessary gate signals and to regulate the output voltage at a desired voltage level.
Test results based on a scale-down prototype derived from the previous section are provided to verify the effectiveness of the proposed converter. The measured waveforms of the PWM signals of S1 - S4 at a 20% load with different input voltages are shown in Fig. 4 . S2 and S3 are phase-shifted with respective to S1 and S4 , respectively. Fig. 5 gives the measured waveforms of the PWM signals of the active switches at a 100% load and with different input voltages.
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Measured waveforms of the PWM signals of S1-S4 at 20% load and (a) Vin=550V (b) Vin=600V.
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Measured waveforms of the PWM signals of S1-S4 at 100% load and (a) Vin=550V (b) Vin=600V.
The high input voltage has a greater phase-shift angle between S1 and S2 . The measured gate voltage, drain voltage and switch current of S1 at a 7% load and with different input voltages are shown in Fig. 6 . Similarly, the measured gate voltage, drain voltage and switch current of S2 - S4 at a 7% load and with different input voltages are given in Figs. 7 - 9 , respectively. It is clear that S1 - S4 are all turned on under ZVS from 7% loads. The voltage stress of S1 - S4 is equal to Vin /2. Fig. 10 shows the measured results of the gate voltages of S1 and S2 and the resonant inductor currents iLr1 - iLr3 at a full load and different input voltage cases. The inductor currents iLr2 and iLr3 are in phase with each other. Fig. 11 give the test results of the gate voltages of S1 and S2 , the AC side voltages vab - vbo and the resonant capacitor voltages vCr1 - vCr3 at full load and different input voltage cases. Three voltage levels are negated on the AC terminal voltages vab - vbo . When switches S1 and S2 are both on, vCr1 decreases and vCr2 and vCr3 increase. On the other hand, vCr1 increases and vCr2 and iLr2 decrease when S1 and S2 are both off. Fig. 12 gives the measured output currents of the six center-tapped rectifiers at full load and different input voltages. It is clear that all of the diodes D1 - D8 are turned off under ZCS and that the output currents of the six center-tapped rectifiers are balanced. The output current issue is depended on the components Lr1 - Lr3 , Cr1 - Cr3 , T1 - T6 and D1 - D12 . If all of the components are identical, then the output currents of the six center-tapped rectifiers are balanced. If the components variation of Lr1 - Lr3 is less than 5%, then the current unbalanced is less than 3% based on the measured results. Fig. 13 gives the measured circuit efficiencies of the proposed converter at different load conditions and input voltage cases.
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Measured results of the gate voltage, drain voltage and switch current of S1 at 7% load and (a) Vin=550V (b) Vin=600V.
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Measured results of the gate voltage, drain voltage and switch current of S2 at 7% load and (a) Vin=550V (b) Vin=600V.
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Measured results of the gate voltage, drain voltage and switch current of S3 at 7% load and (a) Vin=550V (b) Vin=600V.
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Measured results of the gate voltage, drain voltage and switch current of S4 at 7% load and (a) Vin=550V (b) Vin=600V.
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Measured results of the gate voltages of S1 and S2 and resonant inductor currents iLr1-iLr3 at full load and (a) Vin=550V (b) Vin=600V.
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Measured results of the gate voltages of S1 and S2, AC side voltages vab-vbo and resonant capacitor voltages vCr1-vCr3 at full load and (a) Vin=550V (b) Vin=600V.
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Measured output currents of six center-tapped rectifiers at full load and (a) Vin=550V (b) Vin=600V.
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Measured circuit efficiencies of the proposed converter at different load conditions and input voltage cases.
VI. CONCLUSION
A new three-level PWM resonant converter is presented in this paper. Three resonant circuits with the same active switches are adopted in the proposed converter to share the load current. In order to reduce the current stress of the transformer windings and the rectifier diodes, six center-tapped rectifiers are connected in parallel at the secondary side for high load current applications. A three-level PWM converter is adopted to reduce the voltage stress of the active switches for high input voltage applications. The duty cycle PWM control is used to regulate the output voltage. Since the selected switching frequency is less than the series resonant frequency in terms of the series resonant inductance and resonant capacitance, the power MOSFETs can be turned on under ZVS and the rectifier diodes can be turned off under ZCS. Thus, the switching losses on the power semiconductors are reduced. Finally, experiments based on a scale-down laboratory prototype are provided to verify the effectiveness of the proposed converter.
Acknowledgements
This project is partly supported by the National Science Council of Taiwan under Grant NSC 102-2221-E-224 -022
BIO
Bor-Ren Lin received his B.S. dgree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri-Columbia, Columbia, MO, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings–Power Electronics and the Journal of Power Electronics. His current research interests include power-factor corrections, multilevel converters, active power filters, and soft-switching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of Research Excellence Awards in 2004, 2005, 2007 and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, the Taiwan Power Electronics 2007 Conference, and the IEEE.Power Electronics and Drive Systems 2009 Conference.
Chih-Chieh Chen is currently working toward his M.S. degree in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His current research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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