This paper studies a new threelevel pulsewidth modulation (PWM) resonant converter for high input voltage and high load current applications. In order to use high frequency power MOSFETs for high input voltage applications, a threelevel DC converter with two clamped diodes and a flying capacitor is adopted in the proposed circuit. For high load current applications, the secondary sides of the proposed converter are connected in parallel to reduce the size of the magnetic core and copper windings and to decrease the current rating of the rectifier diodes. In order to share the load current and reduce the switch counts, three resonant converters with the same active switches are adopted in the proposed circuit. Two transformers with a series connection in the primary side and a parallel connection in the secondary side are adopted in each converter to balance the secondary side currents. To overcome the drawback of a wide range of switching frequencies in conventional series resonant converters, the duty cycle control is adopted in the proposed circuit to achieve zero current switching (ZCS) turnoff for the rectifier diodes and zero voltage switching (ZVS) turnon for the active switches. Finally, experimental results are provided to verify the effectiveness of the proposed converter.
I. INTRODUCTION
For threephase 380V or 480V systems, an AC/DC converter with power factor correction (PFC) is needed in the front stage for reducing current harmonics at the utility side in order to meet international standards (IEC 6100032 or IEEE 519). Thus, the DC bus voltage after the AC/DC converter is greater than 540V or 680V. In order to use MOSFETs instead of IGBTs in the second DC/DC converter stage with a high switching frequency and high power density demand, threelevel circuit topologies
[1]

[4]
have been proposed for high input voltage and medium/high power applications. Soft switching threelevel converters have been presented in
[5]

[10]
to reduce the switching losses at a desired load range. These techniques are based on an additional auxiliary circuit to extend the zero voltage switching (ZVS) range or using the leakage inductance (or external inductance) and the output capacitance of the MOSFETs to turn on the active switches under ZVS. However, the rectifier diodes at the secondary side have reverse recovery losses. Series resonant converters
[11]

[16]
have been proposed to have the features of ZVS turnon for power switches and ZCS turnoff for rectifier diodes within a wide range of input voltage and load conditions when the switching frequency is less than the series resonant frequency. The main drawback of series resonant converters is the wide range of switching frequencies from light load to full load. Thus, the magnetic components in the circuit are not easy to design at the optimal condition. In order to keep the advantages of series resonant converters and operate at a fixed switching frequency, the resonant converter has a better ability to operate at duty cycle control with soft switching features such as ZVS for the MOSFETs and ZCS for the fast recovery diodes. For high load current applications such as high power battery chargers, parallel threelevel converters are normally adopted.
This paper proposes a new threelevel PWM resonant converter with ZVS/ZCS for high input voltage and high load current applications. A threelevel DC converter with two clamped diodes and one flying capacitor is used to limit the voltage stress of the power switches at
V_{in}
/2. Three PWM resonant converters with the same power switches are used to share the load current for high load current applications. Thus, the switch counts in the proposed circuit are reduced when compared with conventional parallel threelevel DC/DC converters. A series resonant converter is adopted in the transformer primary side and the switching frequency is less than the series resonant frequency. Thus, all of the active switches are turned on under ZVS and the rectifier diodes are turned off under ZCS. Duty cycle control instead of frequency modulation (FM) control is adopted to regulate the output voltage. Thus, the drawback of a wide range of switching frequencies in conventional resonant converters is overcome. Finally, experiments are provided to verify the operation principle of the proposed converter.
II. CIRCUIT CONFIGURATION
The circuit configuration of the proposed converter is shown in
Fig. 1
for medium/high input voltage and high load current applications. The proposed circuit includes three ZVS DC converters connected in parallel. The first DC converter consists of
C_{in1}
,
C_{in2}
,
D_{a}
,
D_{b}
,
C_{f}
,
S_{1}

S_{4}
,
C_{1}

C_{4}
,
C_{r1}
,
L_{r1}
,
T_{1}

T_{2}
,
D_{1}

D_{4}
,
C_{o}
and
R_{o}
. The second DC converter includes the components of
C_{in1}
,
C_{in2}
,
D_{a}
,
D_{b}
,
C_{f}
,
S_{1}

S_{4}
,
C_{1}

C_{4}
,
C_{r2}
,
L_{r2}
,
T_{3}

T_{4}
,
D_{5}

D_{8}
,
C_{o}
and
R_{o}
. In the same manner, the components
C_{in1}
,
C_{in2}
,
D_{a}
,
D_{b}
,
C_{f}
,
S_{1}

S_{4}
,
C_{1}

C_{4}
,
C_{r3}
,
L_{r3}
,
T_{5}

T_{6}
,
D_{9}

D_{12}
,
C_{o}
and
R_{o}
are included in the third DC converter. The input capacitances,
C_{in1}
and
C_{in2}
, are equal and large enough to be two input voltage sources
v_{Cin1}
=
v_{Cin2}
=
V_{in}
/2.
S_{1}

S_{4}
are power MOSFETs with
V_{in}
/2 voltage stress.
C_{1}

C_{4}
are the output capacitances of
S_{1}

S_{4}
, respectively.
D_{a}
and
D_{b}
are the clamped diodes.
C_{f}
is a flying capacitor with
V_{in}
/2 average voltage.
C_{r1}

C_{r3}
are the series resonant capacitors, and
L_{r1}

L_{r3}
are the series resonant inductances.
L_{m1}

L_{m6}
are the magnetizing inductances of
T_{1}

T_{6}
, respectively.
D_{1}

D_{12}
are the rectifier diodes.
R_{o}
is the load resistance, and
C_{o}
is the output capacitance. These three DC converters share the same components in terms of
S_{1}

S_{4}
,
D_{a}
,
D_{b}
, and
C_{f}
. In each of the DC converters, the two transformers are connected in series at the primary side and connected in parallel at the secondary side so that the two secondary side currents are balanced for high load current applications. The PWM signals of
S_{1}
and
S_{4}
are complementary each other with a dead time to allow for ZVS operation. Similarly, the PWM signals of
S_{2}
and
S_{3}
are complementary each other. Based on the operations of
S_{1}

S_{4}
, there are three voltage levels
V_{in}
,
V_{in}
/2 and 0 generated on the AC terminal voltages
v_{ab}
,
v_{bc}
and
v_{bo}
. Each centertapped diode rectifier supplies onesixth of the load current. Thus, the current stresses of each of the transformer secondary windings and the rectifier diodes are reduced.
Circuit configuration of the proposed resonant converter.
III. OPERATION PRINCIPLE
The key waveforms of the proposed resonant converter are shown in
Fig. 2
. The duty cycle of the active switches
S_{1}

S_{4}
is equal to 0.5. The PWM signals of
S_{2}
and
S_{3}
are phaseshifted with respective to the PWM signals of
S_{1}
and
S_{4}
, respectively. The duty cycle of the AC side voltages
v_{ab}
,
v_{bc}
and
v_{bo}
is regulated to keep the output voltage at a desired value against load variations and input voltage changes. Before the system analysis, the following assumptions are made in the proposed converter. (1)
V_{Cin1}
and
V_{Cin2}
are balanced voltage sources; (2)
C_{1}
=
C_{2}
=
C_{3}
=
C_{4}
≡
C_{oss}
,
C_{r1}
=
C_{r2}
=
C_{r3}
≡
C_{r}
and
C_{r}
>
C_{oss}
; (3) the average capacitor voltages
V_{Cr3}
=0 and
V_{Cr1}
=
V_{Cr2}
=
V_{Cf}
=
V_{in}
/2; (4)
V_{o}
is the constant output voltage; (5)
L_{m1}
=
L_{m2}
=
L_{m3}
=
L_{m4}
=
L_{m5}
=
L_{m6}
≡
L_{m}
,
L_{r1}
=
L_{r2}
=
L_{r3}
≡
L_{r}
and
L_{r}
<<
L_{m}
; (6) the turns ratio of
T_{1}

T_{6}
is
n
=
n_{p}
/
n_{s1}
=
n_{p}
/
n_{s2}
; and (7) the MOSFETs,
S_{1}

S_{4}
, and diodes,
D_{1}

D_{12}
and
D_{a}

D_{b}
, are ideal. Based on the on/off states of
S_{1}

S_{4}
,
D_{a}

D_{b}
and
D_{1}

D_{12}
, the proposed converter has ten operating modes in a switching cycle.
Fig. 3
gives the equivalent circuits of these operating modes. Prior to
t_{0}
,
S_{1}
is conducting. The inductor current
i_{Lr1}
is positive and
i_{Lr2}
is negative.
Key waveforms of the proposed converter.
Mode 1 [t_{0}≤t<t_{1}, Fig. 3(a)]:
At
t_{0}
,
C_{2}
is discharged to zero voltage. Since
i_{Lr2}
(
t_{0}
)+
i_{Lr3}
(
t_{0}
)
i_{Lr1}
(
t_{0}
)<0, the antiparallel diode of
S_{2}
is conducting. Thus,
S_{2}
can be turned on at this moment under ZVS. The AC terminal voltages
v_{ab}
=0,
v_{bc}
=
V_{in}
and
v_{bo}
=
V_{in}
/2. Diodes
D_{2}
,
D_{4}
,
D_{5}
,
D_{7}
,
D_{9}
and
D_{11}
are conducting in this mode. Magnetizing voltages
v_{Lm1}
=
v_{Lm2}
=
nV_{o}
and
v_{Lm3}
=
v_{Lm4}
=
v_{Lm5}
=
v_{Lm6}
=
nV_{o}
. Thus,
i_{Lm1}
and
i_{Lm2}
decrease and
i_{Lm3}

i_{Lm6}
increase in this mode.
L_{r1}
and
C_{r1}
are resonant with the applied voltage 2
nV_{o}
,
L_{r2}
and
C_{r2}
are resonant with the applied voltage
V_{in}
2
nV_{o}
, and
L_{r3}
and
C_{r3}
are resonant with the applied voltage
V_{in}
/22
nV_{o}
. In this mode,
i_{Lr1}

i_{Lr3}
and
v_{Cr1}

v_{Cr3}
are expressed as:
where
In this mode,
i_{Lr1}
and
v_{Cr1}
are both decreasing, and
i_{Lr2}

i_{Lr3}
and
v_{Cr2}

v_{Cr3}
are increasing. Power is transferred from
V_{in}
to
R_{o}
through
S_{1}
,
S_{2}
,
T_{3}

T_{6}
,
L_{r2}

L_{r3}
,
C_{r2}

C_{r3}
,
D_{5}
,
D_{7}
,
D_{9}
,
D_{11}
and
C_{o}
.
Mode 2 [t_{1}≤t<t_{2}, Fig. 3(b)]:
At
t_{1}
,
S_{1}
is turned off. Since
i_{Lr2}
(
t_{1}
) and
i_{Lr3}
(
t_{1}
) are positive and
i_{Lr1}
(
t_{1}
) is negative,
C_{1}
is charged linearly and
C_{4}
is discharged linearly. The rising slope of the draintosource voltage of
S_{1}
is limited by
C_{1}
and
C_{4}
. Thus,
S_{1}
is turned off under ZVS. Capacitor
C_{4}
can be discharged to zero voltage if the energy stored in
L_{r1}

L_{r3}
is greater than the energy stored in
C_{1}
and
C_{4}
. Therefore, the ZVS condition of
S_{4}
is expressed as:
Mode 3 [t_{2}≤t<t_{3}, Fig. 3(c)]:
At
t_{2}
,
C_{4}
is discharged to zero voltage. Since
i_{Lr2}
(
t_{2}
) and
i_{Lr3}
(
t_{2}
) are positive and
i_{Lr1}
(
t_{2}
) is negative, the antiparallel diode of
S_{4}
is conducting. Thus,
S_{4}
is turned on at this moment under ZVS. The AC terminal voltages
v_{ab}
=
v_{bc}
=
V_{in}
/2 and
v_{bo}
=0. Since diodes D2,
D_{4}
,
D_{5}
,
D_{7}
,
D_{9}
and
D_{11}
are still conducting, the magnetizing currents
i_{Lm1}
and
i_{Lm2}
decrease and
i_{Lm3}

i_{Lm6}
increase in this mode.
L_{r1}
and
C_{r1}
are resonant with the applied voltage
V_{in}
/2+2
nV_{o}
. In the same manner,
L_{r2}
and
C_{r2}
are resonant with the applied voltage
V_{in}
/22
nV_{o}
, and
L_{r3}
and
C_{r3}
are resonant with the applied voltage 2
nV_{o}
. In this mode,
i_{Lr1}

i_{Lr3}
and
v_{Cr1}

v_{Cr3}
are given as:
The flying capacitor voltage
v_{Cf}
=
v_{Cin2}
=
V_{in}
/2.
Mode 4 [t_{3}≤t<t_{4}, Fig. 3(d)]:
At
t_{3}
,
i_{Lm1}
=
i_{Lm2}
=
i_{Lr1}
,
i_{Lm3}
=
i_{Lm4}
=
i_{Lr2}
and
i_{Lm5}
=
i_{Lm6}
=
i_{Lr3}
. Thus, diodes
D_{1}

D_{12}
are all in the offstate.
C_{r1}
,
L_{r1}
,
L_{m1}
and
L_{m2}
are resonant with the applied voltage
V_{in}
/2. In the same manner,
C_{r2}
,
L_{r2}
,
L_{m3}
and
L_{m4}
are resonant with the applied voltage
V_{in}
/2, and
C_{r3}
,
L_{r3}
,
L_{m5}
and
L_{m6}
are resonant. In this mode,
i_{Lr1}

i_{Lr3}
and
v_{Cr1}

v_{Cr3}
are expressed as:
where
Mode 5 [t_{4}≤t<t_{5}, Fig. 3(e)]:
At
t_{4}
,
S_{2}
is turned off. Since
i_{Lr2}
(
t_{4}
) and
i_{Lr3}
(
t_{4}
) are positive and
i_{Lr1}
(
t_{4}
) is negative,
C_{2}
is charged and
C_{3}
is discharged linearly. The rising slope of the draintosource voltage of
S_{2}
is limited by
C_{2}
and
C_{3}
. Thus,
S_{2}
is turned off under ZVS. Capacitor
C_{3}
can be discharged to zero voltage if the energy stored in
L_{r1}

L_{r3}
and
L_{m1}

L_{m6}
is greater than the energy stored in
C_{2}
and
C_{3}
. Therefore, the ZVS condition of
S_{3}
is given as:
Mode 6 [t_{5}≤t<t_{6}, Fig. 3(f)]:
At
t_{5}
,
C_{3}
is discharged to zero voltage. Since
i_{Lr2}
(
t_{5}
) and
i_{Lr3}
(
t_{5}
) are positive and
i_{Lr1}
(
t_{5}
) is negative, the antiparallel diode of
S_{3}
is conducting. Thus,
S_{3}
is turned on at this moment under ZVS. The AC terminal voltages
v_{ab}
=
V_{in}
,
v_{bc}
=0 and
v_{bo}
=
V_{in}
/2. Diodes
D_{1}
,
D_{3}
,
D_{6}
,
D_{8}
,
D_{10}
and
D_{12}
are conducting in this mode. Thus, the magnetizing voltages
v_{Lm1}
=
v_{Lm2}
=
nV_{o}
and
v_{Lm3}
=
v_{Lm4}
=
v_{Lm5}
=
v_{Lm6}
=
nV_{o}
so that
i_{Lm1}
and
i_{Lm2}
increase and
i_{Lm3}

i_{Lm6}
decrease.
L_{r1}
and
C_{r1}
are resonant with the applied voltage
V_{in}
2
nV_{o}
. In the same manner,
L_{r2}
and
C_{r2}
are resonant with the applied voltage 2
nV_{o}
, and
L_{r3}
and
C_{r3}
are resonant with the applied voltage 
V_{in}
/2+2
nV_{o}
.
Mode 7 [t_{6}≤t<t_{7}, Fig. 3(g)]:
At
t_{6}
,
S_{4}
is turned off. Since
i_{Lr2}
(
t_{6}
) and
i_{Lr3}
(
t_{6}
) are negative and
i_{Lr1}
(
t_{6}
) is positive,
C_{1}
is discharged linearly and
C_{4}
is charged linearly. The rising slope of the draintosource voltage of
S_{4}
is limited by
C_{1}
and
C_{4}
so that
S_{4}
is turned off under ZVS. Capacitor
C_{1}
can be discharged to zero voltage if the energy stored in
L_{r1}

L_{r3}
is greater than the energy stored in
C_{1}
and
C_{4}
. Thus, the ZVS condition of
S_{1}
is given as:
Mode 8 [t_{7}≤t<t_{8}, Fig. 3(h)]:
At
t_{7}
, capacitor
C_{1}
is discharged to zero voltage. Since
i_{Lr2}
(
t_{7}
) and
i_{Lr3}
(
t_{7}
) are negative and
i_{Lr1}
(
t_{7}
) is positive, the antiparallel diode of
S_{1}
is conducting.
S_{1}
is turned on at this moment under ZVS. The AC terminal voltages
v_{ab}
=
v_{bc}
=
V_{in}
/2 and
v_{bo}
=0. Since diodes
D_{1}
,
D_{3}
,
D_{6}
,
D_{8}
,
D_{10}
and
D_{12}
are still conducting,
i_{Lm1}
and
i_{Lm2}
increase and
i_{Lm3}

i_{Lm6}
decrease.
L_{r1}
and
C_{r1}
are resonant with the applied voltage
V_{in}
/22
nV_{o}
. In the same manner,
L_{r2}
and
C_{r2}
are resonant with the applied voltage
V_{in}
/2+2
nV_{o}
, and
L_{r3}
and
C_{r3}
are resonant with the applied voltage 2
nV_{o}
in this mode. The flying capacitor voltage
v_{Cf}
=
v_{Cin1}
=
V_{in}
/2.
Mode 9 [t_{8}≤t<t_{9}, Fig. 3(i)]:
At
t_{8}
,
i_{Lm1}
=
i_{Lm2}
=
i_{Lr1}
,
i_{Lm3}
=
i_{Lm4}
=
i_{Lr2}
and
i_{Lm5}
=
i_{Lm6}
=
i_{Lr3}
. Thus,
D_{1}

D_{12}
are all in the offstate.
C_{r1}
,
L_{r1}
,
L_{m1}
and
L_{m2}
are resonant with the applied voltage
V_{in}
/2. Similarly,
C_{r2}
,
L_{r2}
,
L_{m3}
and
L_{m4}
are resonant with the applied voltage
V_{in}
/2, and
C_{r3}
,
L_{r3}
,
L_{m5}
and
L_{m6}
are resonant in this mode.
Mode 10 [t_{9}≤t<t_{0}, Fig. 3(j)]:
At
t_{9}
,
S_{3}
is turned off. Since
i_{Lr2}
(
t_{9}
) and
i_{Lr3}
(
t_{9}
) are negative and
i_{Lr1}
(
t_{9}
) is positive,
C_{2}
is discharged and
C_{3}
is charged linearly. The rising slope of the draintosource voltage of
S_{3}
is limited by
C_{2}
and
C_{3}
so that
S_{3}
is turned off under ZVS. Capacitor
C_{2}
can be discharged to zero voltage if the energy stored in
L_{r1}

L_{r3}
and
L_{m1}

L_{m6}
is greater than the energy stored in
C_{2}
and
C_{3}
. The ZVS condition of
S_{2}
is given as:
At
t_{0}
,
C_{2}
is discharged to zero voltage and the antiparallel diode of
S_{2}
is conducting. Then, the operations of the proposed converter in a switching cycle are complete.
Operation modes of the proposed converter during one switching cycle (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6 (g) mode 7 (h) mode 8 (i) mode 9 (j) mode 10.
IV. CIRCUIT CHARACTERISTICS
Since the time intervals in modes 2, 5, 7 and 10 are much less than the time periods in the other modes, only modes 1, 3, 4, 6, 8 and 9 are discussed in this section in order to derive the circuit characteristics of the proposed converter. In modes 1, 3, 6 and 8, the proposed converter is resonant at the series resonant frequency
f_{r}
by
L_{r}
and
C_{r}
. In modes 4 and 9, the converter is resonant at the frequency
Since a quasi square voltage waveform is generated at the AC terminal voltages
v_{ab}
,
v_{bc}
and
v_{bo}
, the maximum duty ratio of
v_{ab}
,
v_{bc}
and
v_{bo}
is equal to 0.5. Thus, the AC voltage gain of the proposed resonant converter with a maximum duty ratio of 0.5 can be expressed in (23) based on the fundamental frequency analysis.
where
k
=
L_{r}
/(2
L_{m}
),
R_{ac}
= 48
n
^{2}
R_{o}
/π
^{2}
,
and
f_{s}
is the switching frequency. The maximum DC voltage gain of the proposed converter can be obtained at the minimum input voltage case.
where
V_{f}
is the voltage drop on
D_{1}

D_{12}
. If the duty ratio of the AC terminal voltages
v_{ab}
,
v_{bc}
and
v_{bo}
is less than 0.5, then the DC voltage gain of the proposed converter is less than
G_{dc,max}
. The DC voltage gain of the proposed converter is a nonlinear function of the duty cycle of the AC terminal voltages, the initial resonant inductor current and the initial resonant capacitor voltage. Thus, it is difficult to obtain the voltage conversion ratio in a closed form at the steady state. If the duty cycle of the AC terminal voltages is equal to 0.5, then the AC voltage gain of the proposed converter at the switching frequency can be obtained from (23) with the given parameters
k
,
Q
,
f_{s}
and
f_{r}
. Therefore, the necessary turns ratio of the isolated transformers
T_{1}

T_{6}
is expressed as:
Since the selected switching frequency
f_{s}
is less than the series resonant frequency
f_{r}
in the resonant tank, the active switches
S_{1}

S_{4}
can be turned on under ZVS and the rectifier diodes can be turned off under ZCS. If the duty cycle of the AC terminal voltages
v_{ab}
,
v_{bc}
and
v_{bo}
is equal to 0.5, the peak magnetizing current
I_{m}
can be expressed as:
Since 
i_{Lr1}
(
t_{4}
)= 
i_{Lr2}
(
t_{4}
)=
i_{Lr3}
(
t_{4}
)=
I_{m}
, the minimum resonant inductance to achieve ZVS turnon for
S_{1}

S_{4}
can be obtained from (7), (20) and (26).
The average voltages of
C_{r1}
,
C_{r2}
and
C_{f}
are equal to
V_{in}
/2 and the average voltage of
C_{r3}
is equal to zero. The voltage stress of the active switches is equal to
V_{in}
/2 in the proposed converter. The voltage stress and the average current of the rectifier diodes
D_{1}

D_{12}
are equal to 2(
V_{o}
+
V_{f}
) and
I_{o}
/12, respectively.
V. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS
In this section, a design example and test results are provided to demonstrate the converter performance. The circuit specifications of a scaledown laboratory prototype are:
V_{in}
=550V600V,
V_{o}
=24V,
I_{o,rated}
=60A, series resonant frequency
f_{r}
=125kHz, switching frequency
f_{s}
=100kHz,
k
=0.14 and
Q
=0.2. The designed maximum AC gain of the LLC converter is at the minimum input voltage and full load condition. If the input voltage is increased or the output load is decreased, then the duty cycle is decreased. Thus, a normal duty cycle control PWM IC can be used to regulate the output voltage. Therefore, the requirement turns ratio of
T_{1}

T_{6}
can be obtained under the minimum input voltage case.
The primary and secondary winding turns of
T_{1}

T_{6}
are 30 turns and 5 turns, respectively. The AC equivalent resistance
R_{ac}
at full load is obtained as:
The series resonant inductance and the resonant capacitance are obtained as:
The magnetizing inductances of
T_{1}

T_{6}
are given as:
The selected flying capacitance
C_{f}
is 0.4
μ
F. The output capacitance
C_{o}
is 4000
μ
F. The voltage stress of the power switches
S_{1}

S_{4}
is equal to 300V. In the laboratory, the commercially available MOSFET with at least 300V voltage stress for the power switches
S_{1}

S_{4}
is an IRFP460 which has 500V voltage stress and 20A current stress. The voltage stress and average current of the rectifier diodes
D_{1}

D_{12}
are given as:
Thus, 30CPQ150 fast recovery diodes with 150V voltage stress, 30A current stress and 0.78V voltage drop are used for
D_{1}

D_{12}
. 30ETH06 fast recovery diodes with 600V voltage stress and 30A current stress are used for the clamped diodes
D_{a}
and
D_{b}
. A UCC3895 commercial PWM IC is adopted to generate the necessary gate signals and to regulate the output voltage at a desired voltage level.
Test results based on a scaledown prototype derived from the previous section are provided to verify the effectiveness of the proposed converter. The measured waveforms of the PWM signals of
S_{1}

S_{4}
at a 20% load with different input voltages are shown in
Fig. 4
.
S_{2}
and
S_{3}
are phaseshifted with respective to
S_{1}
and
S_{4}
, respectively.
Fig. 5
gives the measured waveforms of the PWM signals of the active switches at a 100% load and with different input voltages.
Measured waveforms of the PWM signals of S_{1}S_{4} at 20% load and (a) V_{in}=550V (b) V_{in}=600V.
Measured waveforms of the PWM signals of S_{1}S_{4} at 100% load and (a) V_{in}=550V (b) V_{in}=600V.
The high input voltage has a greater phaseshift angle between
S_{1}
and
S_{2}
. The measured gate voltage, drain voltage and switch current of
S_{1}
at a 7% load and with different input voltages are shown in
Fig. 6
. Similarly, the measured gate voltage, drain voltage and switch current of
S_{2}

S_{4}
at a 7% load and with different input voltages are given in
Figs. 7

9
, respectively. It is clear that
S_{1}

S_{4}
are all turned on under ZVS from 7% loads. The voltage stress of
S_{1}

S_{4}
is equal to
V_{in}
/2.
Fig. 10
shows the measured results of the gate voltages of
S_{1}
and
S_{2}
and the resonant inductor currents
i_{Lr1}

i_{Lr3}
at a full load and different input voltage cases. The inductor currents
i_{Lr2}
and
i_{Lr3}
are in phase with each other.
Fig. 11
give the test results of the gate voltages of
S_{1}
and
S_{2}
, the AC side voltages
v_{ab}

v_{bo}
and the resonant capacitor voltages
v_{Cr1}

v_{Cr3}
at full load and different input voltage cases. Three voltage levels are negated on the AC terminal voltages
v_{ab}

v_{bo}
. When switches
S_{1}
and
S_{2}
are both on,
v_{Cr1}
decreases and
v_{Cr2}
and
v_{Cr3}
increase. On the other hand,
v_{Cr1}
increases and
v_{Cr2}
and
i_{Lr2}
decrease when
S_{1}
and
S_{2}
are both off.
Fig. 12
gives the measured output currents of the six centertapped rectifiers at full load and different input voltages. It is clear that all of the diodes
D_{1}

D_{8}
are turned off under ZCS and that the output currents of the six centertapped rectifiers are balanced. The output current issue is depended on the components
L_{r1}

L_{r3}
,
C_{r1}

C_{r3}
,
T_{1}

T_{6}
and
D_{1}

D_{12}
. If all of the components are identical, then the output currents of the six centertapped rectifiers are balanced. If the components variation of
L_{r1}

L_{r3}
is less than 5%, then the current unbalanced is less than 3% based on the measured results.
Fig. 13
gives the measured circuit efficiencies of the proposed converter at different load conditions and input voltage cases.
Measured results of the gate voltage, drain voltage and switch current of S_{1} at 7% load and (a) V_{in}=550V (b) V_{in}=600V.
Measured results of the gate voltage, drain voltage and switch current of S_{2} at 7% load and (a) V_{in}=550V (b) V_{in}=600V.
Measured results of the gate voltage, drain voltage and switch current of S_{3} at 7% load and (a) V_{in}=550V (b) V_{in}=600V.
Measured results of the gate voltage, drain voltage and switch current of S_{4} at 7% load and (a) V_{in}=550V (b) V_{in}=600V.
Measured results of the gate voltages of S_{1} and S_{2} and resonant inductor currents i_{Lr1}i_{Lr3} at full load and (a) V_{in}=550V (b) V_{in}=600V.
Measured results of the gate voltages of S_{1} and S_{2}, AC side voltages v_{ab}v_{bo} and resonant capacitor voltages v_{Cr1}v_{Cr3} at full load and (a) V_{in}=550V (b) V_{in}=600V.
Measured output currents of six centertapped rectifiers at full load and (a) V_{in}=550V (b) V_{in}=600V.
Measured circuit efficiencies of the proposed converter at different load conditions and input voltage cases.
VI. CONCLUSION
A new threelevel PWM resonant converter is presented in this paper. Three resonant circuits with the same active switches are adopted in the proposed converter to share the load current. In order to reduce the current stress of the transformer windings and the rectifier diodes, six centertapped rectifiers are connected in parallel at the secondary side for high load current applications. A threelevel PWM converter is adopted to reduce the voltage stress of the active switches for high input voltage applications. The duty cycle PWM control is used to regulate the output voltage. Since the selected switching frequency is less than the series resonant frequency in terms of the series resonant inductance and resonant capacitance, the power MOSFETs can be turned on under ZVS and the rectifier diodes can be turned off under ZCS. Thus, the switching losses on the power semiconductors are reduced. Finally, experiments based on a scaledown laboratory prototype are provided to verify the effectiveness of the proposed converter.
Acknowledgements
This project is partly supported by the National Science Council of Taiwan under Grant NSC 1022221E224 022
BIO
BorRen Lin received his B.S. dgree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of MissouriColumbia, Columbia, MO, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings–Power Electronics and the Journal of Power Electronics. His current research interests include powerfactor corrections, multilevel converters, active power filters, and softswitching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of Research Excellence Awards in 2004, 2005, 2007 and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, the Taiwan Power Electronics 2007 Conference, and the IEEE.Power Electronics and Drive Systems 2009 Conference.
ChihChieh Chen is currently working toward his M.S. degree in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His current research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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