This paper studies a new three-level pulse-width modulation (PWM) resonant converter for high input voltage and high load current applications. In order to use high frequency power MOSFETs for high input voltage applications, a three-level DC converter with two clamped diodes and a flying capacitor is adopted in the proposed circuit. For high load current applications, the secondary sides of the proposed converter are connected in parallel to reduce the size of the magnetic core and copper windings and to decrease the current rating of the rectifier diodes. In order to share the load current and reduce the switch counts, three resonant converters with the same active switches are adopted in the proposed circuit. Two transformers with a series connection in the primary side and a parallel connection in the secondary side are adopted in each converter to balance the secondary side currents. To overcome the drawback of a wide range of switching frequencies in conventional series resonant converters, the duty cycle control is adopted in the proposed circuit to achieve zero current switching (ZCS) turn-off for the rectifier diodes and zero voltage switching (ZVS) turn-on for the active switches. Finally, experimental results are provided to verify the effectiveness of the proposed converter. For three-phase 380V or 480V systems, an AC/DC converter with power factor correction (PFC) is needed in the front stage for reducing current harmonics at the utility side in order to meet international standards (IEC 61000-3-2 or IEEE 519). Thus, the DC bus voltage after the AC/DC converter is greater than 540V or 680V. In order to use MOSFETs instead of IGBTs in the second DC/DC converter stage with a high switching frequency and high power density demand, three-level circuit topologies [1] - [4] have been proposed for high input voltage and medium/high power applications. Soft switching three-level converters have been presented in [5] - [10] to reduce the switching losses at a desired load range. These techniques are based on an additional auxiliary circuit to extend the zero voltage switching (ZVS) range or using the leakage inductance (or external inductance) and the output capacitance of the MOSFETs to turn on the active switches under ZVS. However, the rectifier diodes at the secondary side have reverse recovery losses. Series resonant converters [11] - [16] have been proposed to have the features of ZVS turn-on for power switches and ZCS turn-off for rectifier diodes within a wide range of input voltage and load conditions when the switching frequency is less than the series resonant frequency. The main drawback of series resonant converters is the wide range of switching frequencies from light load to full load. Thus, the magnetic components in the circuit are not easy to design at the optimal condition. In order to keep the advantages of series resonant converters and operate at a fixed switching frequency, the resonant converter has a better ability to operate at duty cycle control with soft switching features such as ZVS for the MOSFETs and ZCS for the fast recovery diodes. For high load current applications such as high power battery chargers, parallel three-level converters are normally adopted. This paper proposes a new three-level PWM resonant converter with ZVS/ZCS for high input voltage and high load current applications. A three-level DC converter with two clamped diodes and one flying capacitor is used to limit the voltage stress of the power switches at V_in /2. Three PWM resonant converters with the same power switches are used to share the load current for high load current applications. Thus, the switch counts in the proposed circuit are reduced when compared with conventional parallel three-level DC/DC converters. A series resonant converter is adopted in the transformer primary side and the switching frequency is less than the series resonant frequency. Thus, all of the active switches are turned on under ZVS and the rectifier diodes are turned off under ZCS. Duty cycle control instead of frequency modulation (FM) control is adopted to regulate the output voltage. Thus, the drawback of a wide range of switching frequencies in conventional resonant converters is overcome. Finally, experiments are provided to verify the operation principle of the proposed converter. The circuit configuration of the proposed converter is shown in Fig. 1 for medium/high input voltage and high load current applications. The proposed circuit includes three ZVS DC converters connected in parallel. The first DC converter consists of C_in1 , C_in2 , D_a , D_b , C_f , S₁ - S₄ , C₁ - C₄ , C_r1 , L_r1 , T₁ - T₂ , D₁ - D₄ , C_o and R_o . The second DC converter includes the components of C_in1 , C_in2 , D_a , D_b , C_f , S₁ - S₄ , C₁ - C₄ , C_r2 , L_r2 , T₃ - T₄ , D₅ - D₈ , C_o and R_o . In the same manner, the components C_in1 , C_in2 , D_a , D_b , C_f , S₁ - S₄ , C₁ - C₄ , C_r3 , L_r3 , T₅ - T₆ , D₉ - D₁₂ , C_o and R_o are included in the third DC converter. The input capacitances, C_in1 and C_in2 , are equal and large enough to be two input voltage sources v_Cin1 = v_Cin2 = V_in /2. S₁ - S₄ are power MOSFETs with V_in /2 voltage stress. C₁ - C₄ are the output capacitances of S₁ - S₄ , respectively. D_a and D_b are the clamped diodes. C_f is a flying capacitor with V_in /2 average voltage. C_r1 - C_r3 are the series resonant capacitors, and L_r1 - L_r3 are the series resonant inductances. L_m1 - L_m6 are the magnetizing inductances of T₁ - T₆ , respectively. D₁ - D₁₂ are the rectifier diodes. R_o is the load resistance, and C_o is the output capacitance. These three DC converters share the same components in terms of S₁ - S₄ , D_a , D_b , and C_f . In each of the DC converters, the two transformers are connected in series at the primary side and connected in parallel at the secondary side so that the two secondary side currents are balanced for high load current applications. The PWM signals of S₁ and S₄ are complementary each other with a dead time to allow for ZVS operation. Similarly, the PWM signals of S₂ and S₃ are complementary each other. Based on the operations of S₁ - S₄ , there are three voltage levels V_in , V_in /2 and 0 generated on the AC terminal voltages v_ab , v_bc and v_bo . Each center-tapped diode rectifier supplies one-sixth of the load current. Thus, the current stresses of each of the transformer secondary windings and the rectifier diodes are reduced. The key waveforms of the proposed resonant converter are shown in Fig. 2 . The duty cycle of the active switches S₁ - S₄ is equal to 0.5. The PWM signals of S₂ and S₃ are phase-shifted with respective to the PWM signals of S₁ and S₄ , respectively. The duty cycle of the AC side voltages v_ab , v_bc and v_bo is regulated to keep the output voltage at a desired value against load variations and input voltage changes. Before the system analysis, the following assumptions are made in the proposed converter. (1) V_Cin1 and V_Cin2 are balanced voltage sources; (2) C₁ = C₂ = C₃ = C₄ ≡ C_oss , C_r1 = C_r2 = C_r3 ≡ C_r and C_r > C_oss ; (3) the average capacitor voltages V_Cr3 =0 and V_Cr1 = V_Cr2 = V_Cf = V_in /2; (4) V_o is the constant output voltage; (5) L_m1 = L_m2 = L_m3 = L_m4 = L_m5 = L_m6 ≡ L_m , L_r1 = L_r2 = L_r3 ≡ L_r and L_r << L_m ; (6) the turns ratio of T₁ - T₆ is n = n_p / n_s1 = n_p / n_s2 ; and (7) the MOSFETs, S₁ - S₄ , and diodes, D₁ - D₁₂ and D_a - D_b , are ideal. Based on the on/off states of S₁ - S₄ , D_a - D_b and D₁ - D₁₂ , the proposed converter has ten operating modes in a switching cycle. Fig. 3 gives the equivalent circuits of these operating modes. Prior to t₀ , S₁ is conducting. The inductor current i_Lr1 is positive and i_Lr2 is negative. Mode 1 [t₀≤t<t₁, Fig. 3(a)]: At t₀ , C₂ is discharged to zero voltage. Since i_Lr2 ( t₀ )+ i_Lr3 ( t₀ )- i_Lr1 ( t₀ )<0, the anti-parallel diode of S₂ is conducting. Thus, S₂ can be turned on at this moment under ZVS. The AC terminal voltages v_ab =0, v_bc = V_in and v_bo = V_in /2. Diodes D₂ , D₄ , D₅ , D₇ , D₉ and D₁₁ are conducting in this mode. Magnetizing voltages v_Lm1 = v_Lm2 =- nV_o and v_Lm3 = v_Lm4 = v_Lm5 = v_Lm6 = nV_o . Thus, i_Lm1 and i_Lm2 decrease and i_Lm3 - i_Lm6 increase in this mode. L_r1 and C_r1 are resonant with the applied voltage 2 nV_o , L_r2 and C_r2 are resonant with the applied voltage V_in -2 nV_o , and L_r3 and C_r3 are resonant with the applied voltage V_in /2-2 nV_o . In this mode, i_Lr1 - i_Lr3 and v_Cr1 - v_Cr3 are expressed as: where In this mode, i_Lr1 and v_Cr1 are both decreasing, and i_Lr2 - i_Lr3 and v_Cr2 - v_Cr3 are increasing. Power is transferred from V_in to R_o through S₁ , S₂ , T₃ - T₆ , L_r2 - L_r3 , C_r2 - C_r3 , D₅ , D₇ , D₉ , D₁₁ and C_o . Mode 2 [t₁≤t<t₂, Fig. 3(b)]: At t₁ , S₁ is turned off. Since i_Lr2 ( t₁ ) and i_Lr3 ( t₁ ) are positive and i_Lr1 ( t₁ ) is negative, C₁ is charged linearly and C₄ is discharged linearly. The rising slope of the drain-to-source voltage of S₁ is limited by C₁ and C₄ . Thus, S₁ is turned off under ZVS. Capacitor C₄ can be discharged to zero voltage if the energy stored in L_r1 - L_r3 is greater than the energy stored in C₁ and C₄ . Therefore, the ZVS condition of S₄ is expressed as: Mode 3 [t₂≤t<t₃, Fig. 3(c)]: At t₂ , C₄ is discharged to zero voltage. Since i_Lr2 ( t₂ ) and i_Lr3 ( t₂ ) are positive and i_Lr1 ( t₂ ) is negative, the anti-parallel diode of S₄ is conducting. Thus, S₄ is turned on at this moment under ZVS. The AC terminal voltages v_ab = v_bc = V_in /2 and v_bo =0. Since diodes D2, D₄ , D₅ , D₇ , D₉ and D₁₁ are still conducting, the magnetizing currents i_Lm1 and i_Lm2 decrease and i_Lm3 - i_Lm6 increase in this mode. L_r1 and C_r1 are resonant with the applied voltage V_in /2+2 nV_o . In the same manner, L_r2 and C_r2 are resonant with the applied voltage V_in /2-2 nV_o , and L_r3 and C_r3 are resonant with the applied voltage -2 nV_o . In this mode, i_Lr1 - i_Lr3 and v_Cr1 - v_Cr3 are given as: The flying capacitor voltage v_Cf = v_Cin2 = V_in /2. Mode 4 [t₃≤t<t₄, Fig. 3(d)]: At t₃ , i_Lm1 = i_Lm2 = i_Lr1 , i_Lm3 = i_Lm4 = i_Lr2 and i_Lm5 = i_Lm6 = i_Lr3 . Thus, diodes D₁ - D₁₂ are all in the off-state. C_r1 , L_r1 , L_m1 and L_m2 are resonant with the applied voltage V_in /2. In the same manner, C_r2 , L_r2 , L_m3 and L_m4 are resonant with the applied voltage V_in /2, and C_r3 , L_r3 , L_m5 and L_m6 are resonant. In this mode, i_Lr1 - i_Lr3 and v_Cr1 - v_Cr3 are expressed as: where Mode 5 [t₄≤t<t₅, Fig. 3(e)]: At t₄ , S₂ is turned off. Since i_Lr2 ( t₄ ) and i_Lr3 ( t₄ ) are positive and i_Lr1 ( t₄ ) is negative, C₂ is charged and C₃ is discharged linearly. The rising slope of the drain-to-source voltage of S₂ is limited by C₂ and C₃ . Thus, S₂ is turned off under ZVS. Capacitor C₃ can be discharged to zero voltage if the energy stored in L_r1 - L_r3 and L_m1 - L_m6 is greater than the energy stored in C₂ and C₃ . Therefore, the ZVS condition of S₃ is given as: Mode 6 [t₅≤t<t₆, Fig. 3(f)]: At t₅ , C₃ is discharged to zero voltage. Since i_Lr2 ( t₅ ) and i_Lr3 ( t₅ ) are positive and i_Lr1 ( t₅ ) is negative, the anti-parallel diode of S₃ is conducting. Thus, S₃ is turned on at this moment under ZVS. The AC terminal voltages v_ab = V_in , v_bc =0 and v_bo =- V_in /2. Diodes D₁ , D₃ , D₆ , D₈ , D₁₀ and D₁₂ are conducting in this mode. Thus, the magnetizing voltages v_Lm1 = v_Lm2 = nV_o and v_Lm3 = v_Lm4 = v_Lm5 = v_Lm6 =- nV_o so that i_Lm1 and i_Lm2 increase and i_Lm3 - i_Lm6 decrease. L_r1 and C_r1 are resonant with the applied voltage V_in -2 nV_o . In the same manner, L_r2 and C_r2 are resonant with the applied voltage 2 nV_o , and L_r3 and C_r3 are resonant with the applied voltage - V_in /2+2 nV_o . Mode 7 [t₆≤t<t₇, Fig. 3(g)]: At t₆ , S₄ is turned off. Since i_Lr2 ( t₆ ) and i_Lr3 ( t₆ ) are negative and i_Lr1 ( t₆ ) is positive, C₁ is discharged linearly and C₄ is charged linearly. The rising slope of the drain-to-source voltage of S₄ is limited by C₁ and C₄ so that S₄ is turned off under ZVS. Capacitor C₁ can be discharged to zero voltage if the energy stored in L_r1 - L_r3 is greater than the energy stored in C₁ and C₄ . Thus, the ZVS condition of S₁ is given as: Mode 8 [t₇≤t<t₈, Fig. 3(h)]: At t₇ , capacitor C₁ is discharged to zero voltage. Since i_Lr2 ( t₇ ) and i_Lr3 ( t₇ ) are negative and i_Lr1 ( t₇ ) is positive, the anti-parallel diode of S₁ is conducting. S₁ is turned on at this moment under ZVS. The AC terminal voltages v_ab = v_bc = V_in /2 and v_bo =0. Since diodes D₁ , D₃ , D₆ , D₈ , D₁₀ and D₁₂ are still conducting, i_Lm1 and i_Lm2 increase and i_Lm3 - i_Lm6 decrease. L_r1 and C_r1 are resonant with the applied voltage V_in /2-2 nV_o . In the same manner, L_r2 and C_r2 are resonant with the applied voltage V_in /2+2 nV_o , and L_r3 and C_r3 are resonant with the applied voltage 2 nV_o in this mode. The flying capacitor voltage v_Cf = v_Cin1 = V_in /2. Mode 9 [t₈≤t<t₉, Fig. 3(i)]: At t₈ , i_Lm1 = i_Lm2 = i_Lr1 , i_Lm3 = i_Lm4 = i_Lr2 and i_Lm5 = i_Lm6 = i_Lr3 . Thus, D₁ - D₁₂ are all in the off-state. C_r1 , L_r1 , L_m1 and L_m2 are resonant with the applied voltage V_in /2. Similarly, C_r2 , L_r2 , L_m3 and L_m4 are resonant with the applied voltage V_in /2, and C_r3 , L_r3 , L_m5 and L_m6 are resonant in this mode. Mode 10 [t₉≤t<t₀, Fig. 3(j)]: At t₉ , S₃ is turned off. Since i_Lr2 ( t₉ ) and i_Lr3 ( t₉ ) are negative and i_Lr1 ( t₉ ) is positive, C₂ is discharged and C₃ is charged linearly. The rising slope of the drain-to-source voltage of S₃ is limited by C₂ and C₃ so that S₃ is turned off under ZVS. Capacitor C₂ can be discharged to zero voltage if the energy stored in L_r1 - L_r3 and L_m1 - L_m6 is greater than the energy stored in C₂ and C₃ . The ZVS condition of S₂ is given as: At t₀ , C₂ is discharged to zero voltage and the anti-parallel diode of S₂ is conducting. Then, the operations of the proposed converter in a switching cycle are complete. Since the time intervals in modes 2, 5, 7 and 10 are much less than the time periods in the other modes, only modes 1, 3, 4, 6, 8 and 9 are discussed in this section in order to derive the circuit characteristics of the proposed converter. In modes 1, 3, 6 and 8, the proposed converter is resonant at the series resonant frequency f_r by L_r and C_r . In modes 4 and 9, the converter is resonant at the frequency Since a quasi square voltage waveform is generated at the AC terminal voltages v_ab , v_bc and v_bo , the maximum duty ratio of v_ab , v_bc and v_bo is equal to 0.5. Thus, the AC voltage gain of the proposed resonant converter with a maximum duty ratio of 0.5 can be expressed in (23) based on the fundamental frequency analysis. where k = L_r /(2 L_m ), R_ac = 48 n ² R_o /π ² , and f_s is the switching frequency. The maximum DC voltage gain of the proposed converter can be obtained at the minimum input voltage case. where V_f is the voltage drop on D₁ - D₁₂ . If the duty ratio of the AC terminal voltages v_ab , v_bc and v_bo is less than 0.5, then the DC voltage gain of the proposed converter is less than G_dc,max . The DC voltage gain of the proposed converter is a nonlinear function of the duty cycle of the AC terminal voltages, the initial resonant inductor current and the initial resonant capacitor voltage. Thus, it is difficult to obtain the voltage conversion ratio in a closed form at the steady state. If the duty cycle of the AC terminal voltages is equal to 0.5, then the AC voltage gain of the proposed converter at the switching frequency can be obtained from (23) with the given parameters k , Q , f_s and f_r . Therefore, the necessary turns ratio of the isolated transformers T₁ - T₆ is expressed as: Since the selected switching frequency f_s is less than the series resonant frequency f_r in the resonant tank, the active switches S₁ - S₄ can be turned on under ZVS and the rectifier diodes can be turned off under ZCS. If the duty cycle of the AC terminal voltages v_ab , v_bc and v_bo is equal to 0.5, the peak magnetizing current I_m can be expressed as: Since | i_Lr1 ( t₄ )|= | i_Lr2 ( t₄ )|=| i_Lr3 ( t₄ )|= I_m , the minimum resonant inductance to achieve ZVS turn-on for S₁ - S₄ can be obtained from (7), (20) and (26). The average voltages of C_r1 , C_r2 and C_f are equal to V_in /2 and the average voltage of C_r3 is equal to zero. The voltage stress of the active switches is equal to V_in /2 in the proposed converter. The voltage stress and the average current of the rectifier diodes D₁ - D₁₂ are equal to 2( V_o + V_f ) and I_o /12, respectively. In this section, a design example and test results are provided to demonstrate the converter performance. The circuit specifications of a scale-down laboratory prototype are: V_in =550V-600V, V_o =24V, I_o,rated =60A, series resonant frequency f_r =125kHz, switching frequency f_s =100kHz, k =0.14 and Q =0.2. The designed maximum AC gain of the LLC converter is at the minimum input voltage and full load condition. If the input voltage is increased or the output load is decreased, then the duty cycle is decreased. Thus, a normal duty cycle control PWM IC can be used to regulate the output voltage. Therefore, the requirement turns ratio of T₁ - T₆ can be obtained under the minimum input voltage case. The primary and secondary winding turns of T₁ - T₆ are 30 turns and 5 turns, respectively. The AC equivalent resistance R_ac at full load is obtained as: The series resonant inductance and the resonant capacitance are obtained as: The magnetizing inductances of T₁ - T₆ are given as: The selected flying capacitance C_f is 0.4 μ F. The output capacitance C_o is 4000 μ F. The voltage stress of the power switches S₁ - S₄ is equal to 300V. In the laboratory, the commercially available MOSFET with at least 300V voltage stress for the power switches S₁ - S₄ is an IRFP460 which has 500V voltage stress and 20A current stress. The voltage stress and average current of the rectifier diodes D₁ - D₁₂ are given as: Thus, 30CPQ150 fast recovery diodes with 150V voltage stress, 30A current stress and 0.78V voltage drop are used for D₁ - D₁₂ . 30ETH06 fast recovery diodes with 600V voltage stress and 30A current stress are used for the clamped diodes D_a and D_b . A UCC3895 commercial PWM IC is adopted to generate the necessary gate signals and to regulate the output voltage at a desired voltage level. Test results based on a scale-down prototype derived from the previous section are provided to verify the effectiveness of the proposed converter. The measured waveforms of the PWM signals of S₁ - S₄ at a 20% load with different input voltages are shown in Fig. 4 . S₂ and S₃ are phase-shifted with respective to S₁ and S₄ , respectively. Fig. 5 gives the measured waveforms of the PWM signals of the active switches at a 100% load and with different input voltages. The high input voltage has a greater phase-shift angle between S₁ and S₂ . The measured gate voltage, drain voltage and switch current of S₁ at a 7% load and with different input voltages are shown in Fig. 6 . Similarly, the measured gate voltage, drain voltage and switch current of S₂ - S₄ at a 7% load and with different input voltages are given in Figs. 7 - 9 , respectively. It is clear that S₁ - S₄ are all turned on under ZVS from 7% loads. The voltage stress of S₁ - S₄ is equal to V_in /2. Fig. 10 shows the measured results of the gate voltages of S₁ and S₂ and the resonant inductor currents i_Lr1 - i_Lr3 at a full load and different input voltage cases. The inductor currents i_Lr2 and i_Lr3 are in phase with each other. Fig. 11 give the test results of the gate voltages of S₁ and S₂ , the AC side voltages v_ab - v_bo and the resonant capacitor voltages v_Cr1 - v_Cr3 at full load and different input voltage cases. Three voltage levels are negated on the AC terminal voltages v_ab - v_bo . When switches S₁ and S₂ are both on, v_Cr1 decreases and v_Cr2 and v_Cr3 increase. On the other hand, v_Cr1 increases and v_Cr2 and i_Lr2 decrease when S₁ and S₂ are both off. Fig. 12 gives the measured output currents of the six center-tapped rectifiers at full load and different input voltages. It is clear that all of the diodes D₁ - D₈ are turned off under ZCS and that the output currents of the six center-tapped rectifiers are balanced. The output current issue is depended on the components L_r1 - L_r3 , C_r1 - C_r3 , T₁ - T₆ and D₁ - D₁₂ . If all of the components are identical, then the output currents of the six center-tapped rectifiers are balanced. If the components variation of L_r1 - L_r3 is less than 5%, then the current unbalanced is less than 3% based on the measured results. Fig. 13 gives the measured circuit efficiencies of the proposed converter at different load conditions and input voltage cases. A new three-level PWM resonant converter is presented in this paper. Three resonant circuits with the same active switches are adopted in the proposed converter to share the load current. In order to reduce the current stress of the transformer windings and the rectifier diodes, six center-tapped rectifiers are connected in parallel at the secondary side for high load current applications. A three-level PWM converter is adopted to reduce the voltage stress of the active switches for high input voltage applications. The duty cycle PWM control is used to regulate the output voltage. Since the selected switching frequency is less than the series resonant frequency in terms of the series resonant inductance and resonant capacitance, the power MOSFETs can be turned on under ZVS and the rectifier diodes can be turned off under ZCS. Thus, the switching losses on the power semiconductors are reduced. Finally, experiments based on a scale-down laboratory prototype are provided to verify the effectiveness of the proposed converter. Bor-Ren Lin received his B.S. dgree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri-Columbia, Columbia, MO, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings–Power Electronics and the Journal of Power Electronics. His current research interests include power-factor corrections, multilevel converters, active power filters, and soft-switching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of Research Excellence Awards in 2004, 2005, 2007 and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, the Taiwan Power Electronics 2007 Conference, and the IEEE.Power Electronics and Drive Systems 2009 Conference. Chih-Chieh Chen is currently working toward his M.S. degree in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His current research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.