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Parameter Optimization of the LC filters Based on Multiple Impact Factors for Cascaded H-bridge Dynamic Voltage Restorers
Parameter Optimization of the LC filters Based on Multiple Impact Factors for Cascaded H-bridge Dynamic Voltage Restorers
Journal of Power Electronics. 2014. Jan, 14(1): 165-174
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : June 27, 2013
  • Published : January 30, 2014
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About the Authors
Guodong Chen
Technology Center, Shanghai Electric Power Transmission & Distribution Group, Shanghai, P.R. China
chengd@shanghai-electric.com
Miao Zhu
Key Laboratory of Control of Power Transmission and Transformation, Wind Power Research Center, School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, P.R. China
Xu Cai
Key Laboratory of Control of Power Transmission and Transformation, Wind Power Research Center, School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, P.R. China

Abstract
The cascaded H-Bridge Dynamic Voltage Restorer (DVR) is used for protecting high voltage and large capacity loads from voltage sags. The LC filter in the DVR is needed to eliminate switching ripples, which also provides an accurate tracking feature in a certain frequency range. Therefore, the parameter optimization of the LC filter is especially important. In this paper, the value range functions for the inductance and capacitance in LC filters are discussed. Then, parameter variations under different conditions of voltage sags and power factors are analyzed. In addition, an optimized design method is also proposed with the consideration of multiple impact factors. A detailed optimization procedure is presented, and its validity is demonstrated by simulation and experimental results. Both results show that the proposed method can improve the LC filter design for a cascaded H-Bridge DVR and enhance the performance of the whole system.
Keywords
I. INTRODUCTION
In recent decades, due to an increase in sensitive loads, economic loss events caused by voltage sags are a frequent occurrence. In order to minimize the adverse impact of voltage sags, the load side must be equipped with an appropriate compensation facility. A Dynamic Voltage Restorer (DVR) is connected between the grid and a sensitive load in series for suppressing voltage sags [1] , [2] . When grid voltage sag occurs, the DVR resumes the load voltage to the rated value in a millisecond, thus ensuring the normal operation of the sensitive load. Many studies on DVRs have been carried out and a variety of topologies of the DVR have been discussed by scholars. In order to resolve the energy problem during compensation, some experts are committed to introducing energy storage devices to the structure of the DVR, such as chemical battery energy storage [3] , superconducting energy storage [4] and flywheel energy storage [5] . Other experts have done research on topologies and control strategies utilizing low-voltage DVRs with a three-phase three-wire [6] or a three-phase four-wire [7] . High-voltage DVRs with the neutral-point clamped type [8] , flying capacitor type [9] or cascaded type [10] have also been studied. Currently, the industrial application of DVRs is mainly in low-voltage. This is due to the extensive application of renewable energy, especially the grid integration of large-scale wind power and solar power. Power systems are becoming more and more complex, and the requirement for the low voltage ride through capability of wind farms and photovoltaic power plants has become more stringent. Because the DVR can effectively suppress voltage sags, the promotion and assembly of high voltage and large capacity DVRs is particularly urgent [11] , [12] . Therefore, the study of high voltage and large capacity DVRs has become a new research focus [13] , [14] .
A reasonable LC filter design is the key to the development of a DVR. However, the design emphasis of LC filters for different DVR topologies is usually different. In [15] the characteristics of multi-level PWM waveform harmonics are summed up on basis of a large number of simulation datum. Then the design of the output filter is founded on a harmonic analysis, but it lacks a theoretical derivation. In [16] the high order harmonic contents and Total Harmonic Distribution (THD) values of two cascaded H-bridge inverters are accurately calculated. This provides a theoretical basis for the filter design. However, there is no further analysis on the filter parameters of the cascaded H-bridge topology. In [17] the LC parameters are designed by a transfer function analysis of the low-voltage DVR system based on the characteristic of the control strategy. This method guarantees that the LC filter can satisfy the system performance. However, it does not optimize the LC parameters to ensure the minimization of cost and volume. In [18] the LC filter parameters are designed for the two-level topology of a low-voltage DVR. However, the load harmonic current, the output power factor and the voltage sag depth are not taken into account during the design process. In the paper, the output LC filter parameter optimization of the H-bridge cascaded DVR is studied. In consideration of the load harmonic current, different output power factors and different voltage sag depths, a systematic analysis of the LC filter parameters’ upper and lower limits is presented. The optimization of an LC filter based on multiple impact factors for a cascaded H-bridge dynamic voltage restorer is proposed. The theoretical derivation is discussed in detail, and the optimization method is validated by simulation and experimental results. The results show that the optimization method of the LC filter design is able to fully meet the system performance requirements, and reduce the cost and volume of the DVR system. It provides a reference for the design of the filter parameters in high voltage and large capacity power electronic equipment.
II. SYSTEM DESCRIPTION OF THE CASCADED H-BRIDGE DVR
As shown in Fig.1 , a cascaded H-bridge DVR is mainly comprised of a phase-shifting step-down transformer, power units and a LC filter. The system voltage ue is connected to each power unit by the phase-shifting step-down transformer TR . In each power unit, the AC voltage is converted into DC voltage Vdc by the diode rectifier bridge which is composed of D1, D2, D3, D4, D5 and D6. After smoothing by the capacitor C, the DC voltage is used as the input of the H-bridge inverter which is made up of Q1, Q2, Q3 and Q4.
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System diagram of Cascaded H-bridge DVR
Take phase A for example, after filtering by the inductor La and the capacitor Ca , the output transient voltage ua formed by N cascaded power units is turned into the instantaneous capacitor voltage eca . The capacitor Ca is connected in series between the grid and the load. Therefore, eca can be used to implement the dynamic voltage compensation. As shown in Fig.1 , after the system voltage phase locking and voltage sag detection, the DVR control system generates a CPS-SPWM (Carrier Phase Shifting SPWM) signal to achieve control of the switching devices in each power unit by using a voltage feed-forward and feedback control.
An LC filter is the main part of a cascaded H-bridge DVR. It has a direct impact on the waveform quality of the output compensation voltage, the speed of the dynamic response and the performance of the control system. In addition, it affects the cost and volume of the DVR system. Because the DVR is series connected to the grid, the load characteristic determines the design requirements of the LC filter. In practical industrial situations, the load current contains large harmonic contents which lead to grid voltage distortion. Therefore, higher requirements for the LC filter are put forward.
There are multiple compensation strategies in the actual running of a DVR, such as the pre-sag compensation strategy, the in-phase compensation strategy and the minimum energy compensation strategy [19] [20] . As a result, the output power factor of a DVR cannot be uniquely determined. Different output power factors will have different impacts on the LC filter design. Meanwhile, the DC voltage of each power unit Vdc is influenced by the voltage sag depth. Therefore, different Vdc values also influence the LC filter design. Therefore, an optimized design strategy for the LC filter needs to take full account of multiple impact factors such as load current harmonics, different output power factors and different voltage sag depths.
During the LC filter design, changes in the capacitance have a smaller impact on cost and size. In addition, inductance changes bring relatively large variations in cost and size. Therefore, the upper and lower limits of the inductance are a key aspect in design. Inductance design is necessary to achieve both fast current tracking and current ripple suppression. The inductor current mainly consists of load current. However, it also contains a certain amount of capacitor current. Since the capacitor current is much less than the load current, in the design, it can be approximated that the inductor current is equal to the load current.
Take phase A for example. Assume that the inductor current iLa is sinusoidal and that the DVR output power factor equals 1. When the inductor current is crossing zero, its change rate is at its largest. The inductance should be designed to be small enough to meet the requirements for the fast current tracking. Therefore, there is an upper limit to the inductance. When the inductor current reaches its peak, the current ripples are at its most serious. The inductance should be designed to be large enough to suppress the current ripples. Therefore, there is a lower limit to the inductance. By a transient analysis under the condition of multiple impact factors for these two moments, the upper limit Lmax and the lower limit Lmin of the inductance can be obtained. After determining the inductance range, the upper limit Cmax and the lower limit Cmin of the capacitance can be derived according to the LC filter requirements of the DVR. Finally, reasonable LC filter parameters can be determined.
III. THE DERIVATION OF LmaxBASED ON MULTIPLE IMPACT FACTORS
Taking phase A for example, the transient state process of the zero-crossing current tracking wave is analyzed, as shown in Fig.2 . When using CPS-SPWM, the output voltage presents a stepped waveform. The cascaded H-bridge output voltage ua gradually increases by a step of each unit of DC voltage Vdc . In each step, ua is switched between nVdc and ( n -1) Vdc . Meanwhile, n is an integer and the corresponding ceiling of the number for the instantaneous voltage eca . Assume that the output factor of the DVR is cos φ . Then the voltage value at the zero-crossing current time is eca = ecmsinφ . As Fig.2 shows, T 1 is the high pulse time, and Δ i 1 is the amplitude variation of the inductor current at time T 1 . T 2 is the low pulse time, and Δ i 2 is the amplitude variation of the inductor current at time T 2 . L is the inductance, and iLa is the inductor current. Meanwhile, ILm is the peak value of the inductor current, and ecm is the peak value of eca .
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The tracking wave of zero-crossing current under CPS-SPWM(partial enlarged view).
According to the steady-state formula, at the zero-crossing current, when 0 < t < T 1 :
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When T 1 < t < Ts :
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In order to meet the requirements of the rapid current tracking:
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Where ω is the angular frequency of the inductor current iLa . From formula (1), (2) and (3):
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When T 2 = 0 , the current tracking response should be the fastest. At this time, the inductance is sufficiently small and satisfied the following formula:
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L is determined by the value of nVdc - ecmsinφ , and n is an integer and the corresponding ceiling of the number for ecmsinφ . Therefore, ecmsinφ is always between ( n -1) Vdc and nVdc . Then Vdc is at its maximum. Therefore:
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In practical applications, considering the case where a nonlinear load current distortion occurs, the formula of the current should be:
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ω0 = 2πf0 is the fundamental angular frequency. Assuming that the load current is constituted by the n th harmonic, in order to meet the tracking requirements of the n th harmonic change rate, the upper limit of the inductance should be:
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From the above analysis, it is clear that the upper limit of the inductance is unrelated to the voltage sag depth and the output power factor but is determined by the load harmonic current.
IV. THE DERIVATION OF LminBASED ON MULTIPLE IMPACT FACTORS
As shown in Fig.3 , the transient state process of the peak current is analyzed. In order to facilitate the analysis and derivation, assume that the DVR output power factor is cosφ . Then the corresponding voltage instantaneous value at the peak current time is ecmcosφ . Meanwhile, n is an integer and is determined by ecmcosφ . ue is the grid phase voltage rating. Um is the reference peak value of ue , and u 1m is the instantaneous peak value of ue . Δ um is the peak fluctuation of the grid phase voltage, which is the value of the DVR for compensation. Thus, u 1m = Um um . As a result, the voltage sag depth is Δ um / Um .
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The tracking wave of peak current under CPS-SPWM(partial enlarged view).
According to the steady-state formula at the peak current, when 0 < t < T 1 :
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When T 1 < t < Ts :
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When the current is on the top of the sine wave, |Δ i 1 |=|Δ i 2 |.Because of T 1 + T 2 = Ts :
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This can be solved from formula (9) and (10).And:
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Obviously, when using CPS-SPWM modulation, in order to reduce the current ripples effectively, |Δ i 1 |should be the maximum pulsation of the current, which is Δ Imax .. Formula (13) changes to:
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Set the phase shift step-down transformer turns ratio k , and the phase voltage utilization factor of the three-phase full-wave bridge rectifier k 1 so that the relationship between the DC voltage Vdc and u 1m is Vdc = kk 1 u 1m . In the range of satisfying the compensation requirement, formula (14) changes to:
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Since ecm um , the expression f um , cosφ ) of the relationship between the lower limit of the inductance, the output power factor and the voltage sag depth can be obtained.
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Formula (16) is a bivariate distribution function. To analyze the relationship among f um , cosφ ), Δ um and cosφ , the derivation is presented below in detail.
Firstly, by solving df um , cosφ )/ dcosφ =0, the distribution of the extreme point changes with the output power factor under the condition of a certain voltage sag depth can be obtained when:
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There are extreme points of f um , cosφ ). The ceiling of the number n is determined mainly by the value of Δ um cosφ . Therefore, there are n extreme points of formula (17).
For example, if the voltage sag depth is 0.5pu, when the output power factor changes from 0 to 1, there are plenty of extreme points.
When n =1,
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an extreme point exists.
When n =2,
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an extreme point exists. Other extreme points are similar. It can been seen from Fig.4 , that when the output power factor changes from 0 to 1, the extreme points of the lower limit present a regional distribution.
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Lower inductance limit versus output power factor.
Secondly, by solving df um , cosφ )/ d Δ um =0, the distribution of the extreme point changes with the voltage sag depth variation in the case of a certain output power factor can be obtained when:
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There are many extreme points. The ceiling of the number n is determined by Δ umcosφ . Therefore, there are n extreme points in formula (18).
For example, if the output power factor is 1, when the voltage sag depth changes from 0pu to 0.5pu, plenty of extreme points exist.
When n =1 ,
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an extreme point exists.
When n =2 ,
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an extreme point exists, and so on.
As shown in Fig.5 , when the sag depth changes from 0pu to 0.5pu, extreme points of the lower limit present a regional distribution.
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Lower inductance limit versus voltage sag.
To sum up, the lower limit of the inductance is determined by both the output power factor and the voltage sag depth. Therefore:
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V. THE DERIVATION OF CminAND CmaxBASED ON MULTIPLE IMPACT FACTORS
After determining the range of the inductance, the capacitance can be designed. Firstly, due to the current limit of the power electronic switching device, the filter capacitor current cannot be too large, otherwise it will increase the cost of the design and lead to a rise in the power loss. Secondly, the major role of the capacitor C is to filter the voltage ripples in the CPS-SPWM and to smooth the DVR output voltage waveform for reducing the distortion. This also guarantees that the LC filter bandwidth can meet the requirements of the output voltage tracking feature. When considering the design of the capacitance, there are two important points:
1. The capacitor current needs to be far less than the load current.
2. The natural frequency of the LC filter should satisfy the condition of 10 fn < fr <0.5 fpsw . fn is the maximum pass-band frequency of the system, fpsw is the system equivalent switching frequency, and fs is the LC filter natural frequency.
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The equivalent circuit of DVR.
Firstly, according to Fig.1 , the DVR equivalent diagram in Fig.6 is derived. iload is the load current, and Zeq is the equivalent impedance per phase. Meanwhile, iCa is the capacitor current, and ZCf is the capacitive reactance.
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To meet the requirements of point 1, iC should be far less than iload , according to [18] . Therefore:
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After the voltage compensation of the DVR, the load voltage recovers to the rated level. Therefore, uload = Um , eca um . At this time:
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It can be seen from formula (23) that the capacitance design should be inversely proportional to the voltage sag depth. As Δ um becomes larger, the upper and lower limits of the capacitance become smaller. The capacitance should be designed according to the maximum voltage sag depth.
At the same time, in order to meet the requirements of point 2, the LC filter natural frequency should be:
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For reducing the cost and volume of the whole DVR system, the inductance should be as smaller as possible under the premise of meeting the performance requirement. The inductance in formula (25) is usually selected as the lower limit Lmin . Set Cmin and Cmax as the minimum and maximum capacitances. The range of the capacitances should be:
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VI. THE DESIGN OPTIMIZATION AND SIMULATION ANALYSIS
According to the system parameters in Table 1 , since iC is far less than iload , iLa is equal to iload . Taking these parameters to the formula (8), the upper limit value of the inductance is:
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Through the description in chapter 4, on the condition of different output power factors and voltage sag depths, the lower inductance limit has a different extreme value distribution, and it is hard to determine the maximum extreme value. Therefore, a further analysis of the three-dimensional coordinate is needed. According to system parameters and the simulation results, the relationship between the voltage sag depth, the output power factor and the lower inductance limit is an extreme value surface, as shown in Fig.7 .
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Distribution curves of inductance versus double impact factors.
SYSTEM PARAMETERS
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SYSTEM PARAMETERS
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Multi-curves of output power factor and inductance.
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Multi-curves of voltage sag and inductance
With the voltage sag depth changing, the relationship between the output power factor and the lower inductance limit is shown in Fig. 8 . The extreme value distribution is monotonically growing.
With the output power factor changing, the relationship between the voltage sag depth and the lower inductance limit is shown in Fig.9 . The extreme value distribution is a parabola and has a peak point.
According to the extreme value surface shown in Fig.7 , the distribution of the inductance has nine extremal curves. According to the relationship of Fig.8 , the higher the output power factor, the larger the corresponding lower inductance limit value. Based on the analysis from Chapter 4, when the output power factor is 1, there is a maximum value for the inductance. Taking the system parameters into formula (18), when Δ um =0.05124 um , it has the maximum value of the function f um , cosφ ):
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Therefore, the maximum value of the lower inductance limit is 0.3343 mH .
According to the system design requirements, a voltage deviation among ±0.07pu of the normal voltage is allowed. Therefore, the 10kV H-bridge cascaded DVR does not need compensation when the voltage sag depth is in this range. Because the corresponding voltage sag depth of the maximum point is 0.05124pu, which is less than 0.07pu and not in the DVR design requirement, the lower inductance limit can be further optimized.
According to Fig.9 , the relationship curve presents a monotonously rising trend within the range of the abscissa (0, 0.05124pu), and within the range of the abscissa (0.05124pu, 0.5pu) it is a monotonic downdard trend. Therefore, within the scope of the grid voltage sag depth 0.07pu-0.5pu, when Δ um =0.07 um , there is a maximum of f um , cosφ ). According to formula (17), an extreme point exists when cosφ =0.7586. At this moment:
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In summary, within the scope of the grid voltage sag depth 0.07pu-0.5pu:
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According to formulas (27) and (30), the range of the inductance upper and lower limits can be obtained:
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According to formulas (23) and (25), the capacitance range is:
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The LC filter natural frequency distribution surface can be obtained according to the range of the upper and lower limit of the inductance and capacitance which are shown in Fig.10 . Because the value of the inductance has a direct relationship on the cost and volume of the system, the inductance should be as small as possible under the condition of satisfying the DVR output performance.
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Planes of cut-off frequency, inductance and capacitance.
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The inductor current under the condition of output power factor 1.
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The inductor current under the condition of output power factor 0.75.
It is shown in Fig.10 that plane 1 is a 3500Hz natural frequency plane, and plane 2 is a natural frequency plane with different LC parameters. The point at the intersection of the two planes is the LC parameters satisfying the system requirements. On the premise of minimizing the inductance, the optimized parameters of the LC filter are:
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According to the calculated inductance and capacitance, a 10kV medium voltage grid H-bridge cascaded DVR simulation model is built and the optimized design of the LC filter is validated in Matlab/Simulink.
Fig.11 shows that the inductor current waveform under the output power factor equals 1 when the voltage sag depth is 0.1pu. Fig.12 is the inductor current waveform when the output power factor equals 0.75 and the voltage sag depth equals 0.1pu. It can be seen from the comparison that the maximum current ripples in Fig.11 are smaller than those in Fig.12 . Thus, under the condition of different output power factors, the maximum values of the inductor current ripples will be different, and a variation in the output power factor directly affects the design of the inductance.
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The inductor current under the condition of voltage sag 0.15pu.
Fig.13 is the inductor current waveform when the output power factor equals 1 and the voltage sag depth equals 0.15pu. It can be seen from a comparison with Fig.11 that the maximum current ripples under the voltage sag equals 0.1pu, which is smaller than the one in Fig.13 where the voltage sag equals 0.15pu. Thus, different voltage sag depths cause different inductor current ripple maximum values, and the variation in the voltage sag depth directly affects the design of the inductance.
VII. EXPERIMENTAL RESULTS
According to the theoretical derivation and the simulation, a 10kV/2MW DVR prototype has been built as shown Fig. 14 . A dual-DSP-TMS320F28335 is used as an algorithm processor. The CPS-SPWM is realized by an EP3C25-EQFP144 of Altera. The H-bridge consists of a FF300R17ME3 of Infineon. All of the tests have been carried out on the platform with the voltage sag composed by different inductors, as shown in Fig. 15 . Fig. 16 shows the experimental result under the condition of 0.4pu voltage sag. Fig. 17 shows that the inductor current under the voltage sag equals 0.1pu and the output power factor equals 1. Fig. 18 shows that the inductor current under the output power factor equals 0.75 and the voltage sag depth equals 0.1pu. Fig. 19 is the inductor current when the output power factor equals 1 and the voltage sag depth equals 0.15pu. It can be seen that when the voltage sag depth is 0.1pu, the maximum current ripples in Fig. 17 are a little smaller than those in Fig. 18 . When the output power factor is 1, the maximum current ripples in Fig. 17 are a little smaller than that in Fig. 19 .
By analyzing and comparing the inductor current waveforms under different output power factors and different voltage sag depths, it can be seen that the optimized design method of the LC filter based on the load current harmonic, the output power factor and the voltage sag depth is able to satisfy the system performance. Meanwhile, due to the inductance optimization, the cost and volume of a DVR system can be effectively reduced. The optimized design is correct and effective, and it provides a theoretical guide for engineering design.
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The 10kV DVR principle prototype.
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Voltage sag generation system.
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Waveform under the condition of voltage sag 0.4pu(up to down: Grid current, Grid voltage, Load voltage, DVR voltage.
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The inductor current under the condition of output power factor 1.
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The inductor current under the condition of output power factor 0.75.
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The inductor current under the condition of voltage sag 0.15pu.
VIII. CONCLUSION
The paper presents an optimized design for the LC filter used in the H-bridge cascaded DVR topology based on multiple impact factors. By building and analyzing the upper and lower limit functions of the inductance and capacitance, it can be obtained that the load harmonic current affects the inductance upper limit design, while the output power factor and the voltage sag depth affect the lower inductance limit design. At the same time the upper and lower limit of the inductance also determines the range of the capacitance. Finally, LC filter parameters based on the multiple impact factors are worked out. The simulation and experimental results show that the filter parameters using the optimized design fully meet the system performance requirements. In addition, the cost and volume of the DVR system are minimized. The optimized design provides a reference for the filter design of high voltage and large capacity power electronic equipment, and has a tremendous engineering application prospect.
Acknowledgements
This work was supported by National High Technology Research and Development Program 863(2011AA05A104) and Shanghai Science and Technology Innovation Action Plan(13DZ1200200).
BIO
Guodong Chen was born in China, in 1982. He received his M.S. in Power Electronics from Tongji University, Shanghai, China, in 2006. He is currently pursuing his Ph.D. in Power Electronics at Shanghai Jiao Tong University, Shanghai, China. He is also an Engineer of Shanghai Electric. His current research interests include power quality systems and energy conversion systems.
Miao Zhu received his B.S. in Electrical Engineering from Southeast University, Nanjing, China, in 2001, and his Ph.D. in Electrical Engineering from the Nanyang Technological University, Singapore, in 2009. From 2001 to 2002, he was an Assistant Engineer at Wuxi Power Supply Company, State Grid of China, Wuxi, China. From 2008 to 2009, he was with Meiden Asia Pte Ltd., Singapore, as an R&D Engineer. After that, he was a Scientist in the Experimental Power Grid Centre, Agency for Science Technology and Research, Singapore. In July 2012, he joined Shanghai Jiao Tong University, Shanghai, China, as an Associate Professor with the title of Distinguished Researcher. He is a Regular Reviewer for a number of academic journals and has published nearly 40 papers in refereed journals and conference proceedings. His current research interests include power converters, power quality, and microgrids. Dr. Zhu was a recipient of the 2009 IEEE Power Electronics Society Prize Letter Award. In 2010, he was awarded the World Future Foundation Ph.D. Prize in Environmental and Sustainability Research.
Xu Cai received his B.S. in Electrical Engineering from Southeast University, Nanjing, China, in 1983, and his M.S. and Ph.D. from the China University of Mining and Technology, Xuzhou, China, in 1988 and 2000, respectively. From 1989 to 2001, he was with the Department of Electrical Engineering, China University of Mining and Technology, as an Associate Professor. In 2002, he joined Shanghai Jiao Tong University, Shanghai, China, as a Professor, and he has been the Director of the Wind Power Research Center, Shanghai Jiao Tong University, since 2008. His current research interests include power electronics and renewable energy exploitation and utilization, including wind power converters, wind turbine control systems, pitch control, large power battery storage systems, clustering of wind farms and their control systems and grid integration.
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