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Novel Switched-Inductor Quasi-Z-source Inverter
Novel Switched-Inductor Quasi-Z-source Inverter
Journal of Power Electronics. 2014. Jan, 14(1): 11-21
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : July 06, 2013
  • Accepted : October 09, 2013
  • Published : January 30, 2014
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About the Authors
Kai Deng
School of Electrical Engineering, Southeast University, Nanjing, China
dengkai1986@seu.edu.cn
Jianyong Zheng
School of Electrical Engineering, Southeast University, Nanjing, China
Jun Mei
School of Electrical Engineering, Southeast University, Nanjing, China

Abstract
A novel switched-inductor quasi-Z-source inverter is proposed in this study. Compared with classic topologies, the boost ability of the proposed topology is strengthened. The voltage stress of the capacitors, diodes, and power devices are reduced, and the current ripple of the DC voltage source is suppressed. Conversion efficiency is also improved. The operation principle of the proposed topology is analyzed in detail and compared with that of similar topologies. The feasibility of the proposed topology is verified by simulations and experiments on a laboratory prototype.
Keywords
I. INTRODUCTION
The Z-source inverter (ZSI) has elicited much interest recently because of its obvious advantages compared with the classic voltage source inverter. First, ZSIs utilize the shoot-through of the inverter bridge to boost voltage and are thus more suitable for applications with low input voltages, such as photovoltaic and fuel cells. Second, no dead time exists between the conduction of the upper switch and that of the lower switch; thus, the distortion of the output waveform is reduced. Third, boost and inversion of the voltage are realized with single-stage power conversion; efficiency is thus increased. Lastly, ZSIs exhibit better immunity against EMI noise [1 5] . However, classic ZSI have obvious disadvantages, such as high voltage stress in the switches and capacitors, huge inrush current, and weak boost ability. The most significant drawback is the discontinuous input current, which limits the use of ZSIs and causes lifetime damage to the DC source. Several pulse width modulation (PWM) methods, such as the maximum boost control method [6] and the constant boost control method [7] , have been developed to overcome these drawbacks and obtain reduced voltage stress and increased boost ability. However, these PWM methods have yet to extend the voltage gain without sacrificing the device cost as well as avoid the discontinuous input current. Fortunately, the improvement of circuit topology appears to be an opportunity for ZSIs [8] - [19] .
In [8] and [9] , an improved ZSI was proposed to reduce the capacitor voltage stress and startup inrush current; however, boost ability remained unchanged and the input current was still discontinuous. In [10] , a novel family of extended-boost ZSIs was developed. Diode or capacitor assistance was applied to increase the boost ability and make the input current continuous. However, these extended-boost ZSIs have obvious shortcomings, such as small boost effect, complicated structure, and large size. In [11] and [12] , a class of quasi-Z-source inverters (qZSI) was proposed by Peng et al. Compared with the classic ZSI, qZSI has a lower rating and fewer power devices, continuous input current, and lower current stress for the DC source. A common ground point also exists in qZSI for the DC source and the inverter. Nevertheless, the boost ability of qZSIs remains limited. In [13] , a class of trans-Z-source inverters was presented; these inverters employed two coupled magnetic inductors instead of separate ones, and the DC link voltage was boosted according to the changes in turn and shoot-through duty ratios. However, the effect of leak inductance remains inevitable.
Switched capacitor (SC), switched inductor (SL), and hybrid SC/SL techniques are commonly used in DC–DC converters to achieve high boost capability with transformerless cascade structures; thus, size is reduced and power density is increased [14] - [16] . ZSI and SL techniques were successfully combined in [17] to overcome the boost limitation of the classic ZSI; a switched-inductor Z-source inverter (SL-ZSI) was presented. Compared with [17] , two isolated DC sources were embedded into the SL-ZSI topology in [18] to make the input current continuous, suppress the voltage stress, and improve reliability. Nevertheless, the circuits in [17] and [18] still entail increased cost, loss, and size because of the large number of components.
Compared with the SL-ZSIs mentioned above, the switched-inductor quasi-Z-source inverter (SL-qZSI) in [19] not only has fewer passive components but also produces lower stress on the capacitors, inductors, and diodes. Continuous input current is likewise generated. At startup, SL-qZSIs can avoid inrush current, which could destroy the switching devices. A novel SL-qZSI is proposed in this study to further enhance the performance of SL-qZSIs. The typical switched inductors are replaced by a bootstrap capacitor and boost inductors derived from [20] without increasing the complexity of the circuit. Compared with the classic qZSI and SL-qZSI in [11] and [19] , the proposed topology possesses much greater boost ability with the same shoot-through duty ratio. The proposed SL-qZSI achieves low voltage stress for capacitors, diodes, and power devices as well as low current ripple for the input inductor. Furthermore, the conversion efficiency of the proposed topology is improved. The operation principle of the proposed topology is analyzed in detail. Afterward, the topology is compared with similar topologies in literature. Finally, the feasibility of the proposed SL-qZSI is validated by simulations. A laboratory prototype based on a TMS320F28335 digital signal processor is developed.
II. CIRCUIT ANALYSIS OF THE PROPOSED SL-QZSI
Fig. 1 shows the proposed SL-qZSI, which consists of three inductors ( L 1 , L 2 , L 3 ), three capacitors ( C 1 , C 2 , C 3 ), and three diodes ( D 1 , D 2 , D 3 ). A diode inside the switched-inductor cell of the SL-qZSI topology in [11] is replaced by a bootstrap capacitor. The operating principle of the proposed topology is similar to that of the classical SL-qZSI in [19] . The operating state can be simplified into two parts: shoot-through state and non-shoot-through state. Figs. 2 and 3 show the equivalent circuits of the proposed SL-qZSI in the two states.
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Proposed SL-qZSI.
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Equivalent circuit of the proposed SL-qZSI in the shoot-through state.
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Equivalent circuit of the proposed SL-qZSI in the non-shoot-through state.
All devices were assumed to be ideal, that is, L 1 = L 2 = L 3 = L , C 1 = C 2 = C 3 = C , to simplify the analysis. During the shoot-through state ( Fig. 2 ), diodes D 2 and D 3 are on, whereas D 1 is off. L 2 , L 3 , and C 3 are connected in parallel. Capacitors C 1 and C 2 are discharged, whereas C 3 is charged. Inductors L 1 , L 2 , and L 3 store energy, and the corresponding voltages across L 1 , L 2 , and L 3 are VL 1 , VL 2 , and VL 3 , respectively. The voltages across C 1 , C 2 , and C 3 are VC 1 , VC 2 , and VC 3 , respectively, and the currents flowing through C 1 , C 2 , C 3 , L 1 , L 2 , and L 3 are iC 1 , iC 2 , iC 3 , IL 1 , iL 2 , and iL 3 , respectively. ish 1 denotes the shoot-through current. Thus, we obtain
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Similarly, in the non-shoot-through state ( Fig. 3 ), diodes D 2 and D 3 are off, whereas D 1 is on. Capacitors C 1 and C 2 are charged, whereas C 3 is discharged. L 2 , L 3 , and C 3 are connected in series. Inductors L 1 , L 2 , and L 3 transfer energy from the DC voltage source to the load. ii 1 denotes the non-shoot-through current. We can then obtain
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Based on the volt-second balance principle, we can obtain the voltage across inductor L 1 from period (1) to (2). Setting the interval of the shoot-through as DT and non-shoot-through as (1- D ) T , we obtain
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Equation (3) can be revised as
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The voltages across L 2 and L 3 are equal in a period because of the symmetry of L 2 and L 3 ; that is, VL 2 = VL 3 = VC 3 in the shoot-through state and VL 2 = VL 3 =( VC 2 - VC 3 )/2 in the non-shoot-through state. Therefore, by re-applying the volt-second balance principle to L 2 or L 3 from (1) and (2), we acquire
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Equation (5) can be revised as
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In a switching cycle, the voltage across the capacitor remains nearly unchanged, and the capacitor is equivalent to a voltage source. Thus, we obtain
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Substituting Equations (4) and (6) into (7) yields
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Therefore, the voltage across capacitor C 2 can be described as
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Substituting Equations (9) into (6) and (7) yields
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The peak DC link voltage across the main circuit ( VPN ) expressed in Equation (2) can be rewritten as
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Thus, the ratio between DC link voltage VPN and input DC voltage Vin of the proposed inverter, called boost factor B , is defined by
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According to Equation (12), the proposed SL-qZSI can obtain high voltage-conversion ratios when shoot-through duty ratio D ≤1/3. Fig. 4 shows the boost factor versus the duty cycle for different topologies when simple boost control method is employed. Fig. 4 shows that the boost ability of the proposed SL-qZSI is significantly higher than that of the other two topologies in [11] and [19] with the same shoot-through interval. Therefore, at the same voltage conversion ratio, the proposed topology employs a high modulation index to improve inverter output performance. In conclusion, the proposed SL-qZSI is suitable for low-voltage power applications.
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Comparison of the boost ability of different topologies when simple boost control method is employed.
III. COMPARISON WITH PREVIOUS TOPOLOGIES
- A. Voltage Gain
Compared with the simple boost and constant boost control methods, the maximum boost control method converts all zero states into shoot-through states without affecting the active state; thus, the largest possible voltage gain can be obtained for a given modulation index [6] . In the following comparisons, the maximum boost control method was used for the analysis. Simulations and experiments were conducted to verify the merits of the proposed topology. As described in [1] , voltage gain G can be expressed as
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where
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is the output peak phase voltage, Vin is the input DC voltage, M is the modulation index, and B is the boost factor. As shown in [6] , when the maximum boost control method is used, the average duty cycle of shoot-through state D is described as
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where T0 is the shoot-through time interval over switching period T . Substituting Equations (12) and (14) into (13) provides voltage gain G of the proposed topology, which can be expressed as
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Fig. 5 (a) shows the voltage gain of the different topologies under maximum boost control. The dashed box in the figure is expanded and can be seen more clearly in Fig. 5 (b). The abscissa in Fig. 5 refers to modulation index M , and the ordinate represents voltage gain G . The proposed SL-qZSI employs a higher modulation index and a shorter shoot-through duty cycle than the other two topologies in [11] and [19] to obtain the same voltage gain G . Thus, inverter output quality is improved.
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(a) Comparison of the voltage gain of the different topologies with maximum boost control method. (b) Expanded waveforms (dashed box).
- B. Capacitor Voltage Stress
Capacitor voltage stress and inductor current ripple are important factors that affect the performance of qZSIs; they also determine the inverter cost and volume [8] . Therefore, the different qZSI topologies were compared in this study. To ensure a fair and valid comparison, all inverters were assumed to have the same input voltage Vin and output voltage Vo under the maximum boost control method; that is, all inverters have the same voltage gain G . From Equations (14) and (15), we can obtain modulation index M and shoot-through duty ratio D of the proposed SL-qZSI, both of which are defined by voltage gain G .
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Substituting Equation (16) into (10), we can obtain the voltage stress across capacitor C1 of the proposed topology shown in Fig. 1 . The voltage stress across C1 is described as
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Similarly, the capacitor voltages of the topologies mentioned in [11] and [19] ( VC 12 and VC 13 , respectively) in the same position can also be replaced by voltage gain G with the same control method as follows:
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Modulation index M1 of the SL-qZSI topology in [19] is described as
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where the respective coefficients can be rewritten as
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Fig. 6 shows the voltage stress of capacitor C 1 in the different topologies. The abscissa refers to voltage gain G , and the ordinate denotes the ratio of capacitor voltage stress Vc1i ( i = 1, 2, 3) and input voltage Vin . Compared with that in the other two topologies, the voltage stress across C 1 in the proposed SL-qZSI is lower under the same voltage gain.
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Comparison of the voltage stress across C1 in the different topologies with maximum boost control method.
Similar to the analysis for capacitor C 1 , Equation (16) is substituted into (9) to obtain the capacitor voltage stress across C 2 for the proposed SL-qZSI, SL-qZSI, and classic qZSI as described by Equation (21) below.
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Fig. 7 shows the capacitor voltage stress across C 2 in the three topologies. With the same voltage gain, the voltage stress across C 2 in the three topologies is exactly the same.
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Comparison of the voltage stress across C2 in the different topologies with maximum boost control method.
- C. Inductor Current Ripple
Given that the input and output voltages of the different topologies are similar, the input current ripple of the inductor must be different under the same control method. In the shoot-through state shown in Fig. 2 , the voltage across inductor L 1 can be expressed as
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Therefore, the current ripple of L 1 can be described as
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Substituting Equation (9) into (23), we can obtain the inductor current ripple of the proposed topology as follows:
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Similarly, the inductor current ripple of the other two topologies in [11] and [19] can be described as
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where
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Rearranging the inductor current ripple of the three topologies, we obtain
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where ri is the inductor current ripple coefficient that can be described as
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Fig. 8 shows the inductor current ripples of the three topologies. The inductor current ripple of the proposed SL-qZSI is smaller than that of the other two topologies with the same voltage gain G .
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Comparison of the input current ripples of the different topologies with maximum boost control method.
- D. Switch Voltage Stress and Diode Reverse Voltage
The voltage stress in the switching devices is related to DC bus voltage VPN for qZSI. Therefore, substituting Equation (16) into (11) provides DC link voltage VPN1 of the proposed SL-qZSI.
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The DC link voltages of SL-qZSI and classic qZSI can also be described as VPN 2 and VPN 3 , respectively.
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The power diode provides uncontrolled rectification in power conversion applications, and its switching phenomenon, which contains forward and reverse recovery, determines the power losses when operating at high frequency. The reverse voltage of a diode is an important factor that affects the reverse recovery; thus, it is worth mentioning as well [21] . In the shoot-through state ( Fig. 2 ), the D 1 reverse voltage of the proposed topology, VD 11 , can be described as
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In the non-shoot-through state ( Fig. 3 ), the D 2 and D 3 reverse voltages of the proposed topology, VD 21 and VD 31 , can be described as
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From Equations (31) and (32), we can conclude that diode D 1 in the proposed topology withstands high reverse voltage that is equal to DC link voltage VPN 1 . The maximum reverse voltages in the diodes of the other two topologies are VD 12 and VD 13 , which are also equal to DC link voltages VPN 2 and VPN 3 .
Fig. 9 shows the comparison of the device voltage stress and maximum diode reverse voltage of the three topologies. The abscissa refers to voltage gain G , and the ordinate denotes the ratio of DC bus voltage VPNi ( i =1,2,3) and input voltage Vin . With the same voltage gain G , the proposed SL-qZSI has lower voltage stress and diode reverse voltage across the switching devices than the other two topologies. This condition is extremely beneficial for high voltage gain applications.
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Comparison of the DC bus voltages of the different topologies with maximum boost control method.
- E. Shoot-Through Current and Efficiency
Shoot-through current is an important factor that affects the choice of switching devices and the power loss of the inverter. Therefore, the shoot-through currents of the three topologies were analyzed. To simplify the analysis, we assumed that the inductor current is basically constant in a given period. Applying the volt-second balance principle to the capacitors, from (1) and (2), we can obtain
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Simplifying Equation (33) and substituting it into (1), we obtain
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In the same manner, the shoot-through currents of SL-qZSI and classic qZSI ( Ish 2 and Ish 3 ), which are described by inductor current iL 12 and iL 13 , are expressed as
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To facilitate the analysis, we assumed that no power losses occur in the three topologies. Given that the input and output voltages are similar, the three topologies have the same input and output power. Therefore, the inductor L 1 currents of the three topologies are similar and thus indicates that iL 1 = iL 12 = iL 13 = Iin . Iin stands for the average value of the input current. Moreover, the first part of Ish 1 [ Ish 11 =(1-3 D )* iL 1 /(1+ D )] was utilized to compare the other two shoot-through currents. D and D 2 were then substituted with Equations (16) and (26), respectively.
Fig. 10 shows the comparison of the shoot-through currents of the three topologies. The abscissa refers to voltage gain G , and the ordinate denotes the ratio of shoot-through current Ish and input current Iin . The first part of Ish1 is larger than that of Ish 2 and Ish 3 .
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Comparison of the shoot-through current of the three topologies.
Fig. 11 shows that the second part of Ish 1 [ Ish 12 =(3+ D )* iC 1 /(1+ D )] is positive. With a given range of voltage gain, the ratios of Ish 12 and iC 1 are always greater than zero, which means that the shoot-through current Ish 1 = Ish 11 + Ish 12 > Ish 2 > Ish 3 . Therefore, the shoot-through current of the proposed topology is larger than that of the other two topologies.
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Polarity judge of Ish12.
Fig. 12 shows the relationship between the voltage gain and shoot-through duty ratio of the three topologies. The shoot-through duty ratio of the proposed topology is much smaller than that of the other two topologies and nearly less than half of classic qZSI to obtain the same voltage gain. Thus, the power loss in the proposed topology may be small because of the drop forward of IGBTs and the parasitic impedance of the components and the wire.
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Relationship between the voltage gain and shoot-through duty ratio of the three topologies.
IV. SIMULATION RESULTS
The merits of the proposed SL-qZSI shown in Fig. 1 were verified. The simulation results shown in Figs. 13 to 17 compare the performance of the proposed SL-qZSI with that of SL-qZSI and qZSI in [11] and [19] . Table 1 provides the list of the simulation parameters for the three topologies.
SIMULATION PARAMETERS FOR qZSI
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SIMULATION PARAMETERS FOR qZSI
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Simulation results of DC link voltages based on the different topologies with simple boost control method.
Fig. 13 shows the DC bus voltages of the three topologies when simple boost control method is employed. The shoot-through duty ratio is 0.2. The DC bus voltage of the proposed topology is higher than that of the other two topologies and thus indicates that the proposed topology has stronger boost ability. As shown in Fig.14 , in the steady state, VPN is boosted to 240 V when input DC voltage Vin is 48 V and the output phase voltage peak value is 90 V . VC 1 and VC 2 of the proposed SL-qZSI are boosted to 96 and 144 V , respectively, similar to the analysis.
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Simulation results of the proposed topology with simple boost control method.
Figs. 15 to 17 show the simulation results for the three topologies when maximum boost control is used to produce the same input and output voltages. Fig. 15 shows the simulation results for the three phase voltages, shoot-through currents, and DC link voltages for the proposed SL-qZSI, SL-qZSI, and classic qZSI when M 1 =0.92, M 2 =0.78, and M 3 =0.67, respectively. The output phase voltage is 110 V (RMS), and the phase resistive load is 5.5 Ω. When the output phase voltages of the three topologies are almost similar, the DC bus voltage of the proposed topology becomes the lowest. This result means that the voltage stress across the IGBTs of the proposed topology is smaller than that of the other two topologies. However, the shoot-through current of the proposed topology is larger than that of the other two topologies.
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Simulation results of DC link voltages, output voltages, and shoot-through currents of the different topologies with maximum boost control method.
Fig. 16 shows the input inductor currents and capacitor voltages across C 1 and C 2 . In the steady state, the amplitude of the input current ripple and the voltage stress across C 1 of the proposed topology are both less than those of the other two topologies. The voltages across C 2 of the three topologies are similar. The simulation results are in good agreement with the theoretical analysis results.
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Simulation results of the different topologies with maximum boost control method.
Fig. 17 shows the input inductor current ripples, diode reverse voltages, and shoot-through currents of the three topologies. The maximum current ripples of the proposed SL-qZSI, SL-qZSI, and classic qZSI are 2.5, 3.0, and 3.5 A, respectively. The input current ripple of the proposed topology is the smallest. The diode reverse voltages are mostly equal to the DC link voltages, and the diode of the proposed topology bears lower reverse voltage. The shoot-through current of the proposed topology is the largest. All simulation results concur with the theoretical analysis.
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Simulation results of input current ripples, diode reverse voltages, and shoot-through currents of the three topologies with maximum boost control method.
V. EXPERIMENTAL RESULTS
Experiments were conducted on the three topologies with the same parameters ( Table 1 ) to verify the properties of the proposed SL-qZSI. Fig. 18 shows the experimental results for the proposed inverter by using the simple boost control method when the shoot-through duty ratio is 0.2. In Fig. 18 (a), VPN is boosted to 221 V when input voltage Vin is 48 V and the output phase voltage peak value is 100 V. In Fig. 18 (b), VC 1 , VC 2 , and VPN are boosted to 89, 125, and 220 V, respectively. These experimental results concur with the theoretical analysis and simulation results.
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Experimental results of the proposed topology with simple boost control method when D=0.2. (a) From top to bottom: output phase voltage, input DC voltage, and DC link voltage. (b) From top to bottom: capacitor C2 voltage, input DC voltage, DC link voltage, and capacitor C1 voltage.
Figs. 19 to 21 show the experimental results for the three topologies when the maximum boost control method is used. To produce the same phase voltage (100 V/peak value), the modulation index for the proposed SL-qZSI, SL-qZSI, and classic qZSI is M 1 =0.93, M 2 =0.723, and M 3 =0.63, respectively. A 15Ω/phase resistive load was utilized in the experiment to reduce the current in the power circuit. The voltage across C 1 for the proposed SL-qZSI, SL-qZSI, and classic qZSI is 80, 120, and 160 V, respectively, as shown in Fig. 19 . Thus, capacitor C 1 of the proposed topology withstands low voltage. Moreover, the voltages across C 2 for the three topologies are almost 110 V.
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Experimental results of the three topologies with maximum boost control method when (a) M1=0.93, (b) M2=0.723, and (c) M3=0.63. From top to bottom: capacitor C1 voltage, capacitor C2 voltage, output phase voltage, and input inductor L1 current.
The DC link voltage for the proposed SL-qZSI, SL-qZSI, and classic qZSI is 200, 240, and 260 V, respectively, as shown in Fig. 20 . The proposed topology achieves low DC link voltage. In the three topologies, the diode reverse voltages are mostly equal to the DC link voltage. Furthermore, the shoot-through current of the proposed topology is larger than that of other two topologies.
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Experimental results of the three topologies with maximum boost control method. From top to bottom: diode reverse voltage, DC link voltage, output voltage, and shoot-through current.
Fig. 21 shows that with the same voltage gain, the shoot-though time of the proposed topology is much less than that of the other two topologies although the shoot-through current of the proposed topology is slightly larger. Therefore, the power loss produced by the forward drop of IGBT as well as the parasitic impedance of the components and line is smaller in the proposed topology than in the other two topologies. Fig. 22 shows the comparison of the experimental efficiency of the three topologies under maximum boost control. The proposed SL-qZSI can obtain high conversion efficiency because of its small shoot-through duty ratio.
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Experimental results of the three topologies with maximum boost control method. From top to bottom: DC link voltage, input inductor L1 current ripple, and shoot-though current.
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Comparison of the efficiency of the three topologies under maximum boost control.
VI. CONCLUSIONS
A novel switch-inductor SL-qZSI with strong boost ability was presented in this paper. Compared with the other SL-qZSIs, the proposed topology offers lower capacitor voltage stress, diode reverse voltage, and input current ripple as well as lower voltage stress in the switching devices with the same input and output voltages. To obtain the same voltage gain, the proposed topology uses a modulation index higher than that of the other two topologies. Thus, the quality of the output waveform is improved. The proposed topology can also achieve high conversion efficiency. The effectiveness of the proposed SL-qZSI was verified by simulations and experiments with both the simple boost and maximum boost control methods. According to these methods, the proposed SL-qZSI is a promising candidate in distributed generation applications of low-voltage sources, such as fuel and photovoltaic cells.
Acknowledgements
This work was supported by the Science and Technology Support Program of Jiangsu Province, China (Grant No. BE2012036).
BIO
Kai Deng was born in Jiangsu, China. He received his B.S. degree from Nanjing Agricultural University, Nanjing, China, in 2009 and his M.S. degree from Beijing Institute of Technology, Beijing, China, in 2012, both in electrical engineering. He is currently pursuing his Ph.D. degree in electrical engineering in Southeast University, Nanjing, China. His current research interests include Z-source inverters, digital control of power converters, and system integration of modular power converters.
Jianyong Zheng was born in China in 1966. He received his B.S., M.S., and Ph.D. degrees from the School of Electrical Engineering, Southeast University, Nanjing, China, in 1988, 1991, and 1999, respectively. He is a full professor in the School of Electrical Engineering, Southeast University. His research interests are in the fields of power electronics application in power systems and renewable energy technology.
Jun Mei received his B.S. degree in radio engineering from Chongqing University in 1994 and his M.S. and Ph.D. degrees in electrical engineering from Southeast University, Nanjing, China, in 2001 and 2006, respectively. He is an associate professor in the School of Electrical Engineering, Southeast University. He was a visiting scholar in the University of Tennessee, Knoxville, TN, from 2011 to 2012. His interests include electric power converters for distributed energy sources, FACTS, and power quality control.
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