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High-Efficiency Supercapacitor Charger Using an Improved Two-Switch Forward Converter
High-Efficiency Supercapacitor Charger Using an Improved Two-Switch Forward Converter
Journal of Power Electronics. 2014. Jan, 14(1): 1-10
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : June 20, 2013
  • Accepted : October 04, 2013
  • Published : January 30, 2014
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About the Authors
Woo-Young Choi
Division of Electronic Engineering, Chonbuk National University, Jeonju, Korea
wychoi@jbnu.ac.kr
Min-Kwon Yang
Division of Electronic Engineering, Chonbuk National University, Jeonju, Korea
Yongsug Suh
Department of Electrical Engineering, Chonbuk National University, Jeonju, Korea

Abstract
This paper proposes a high-efficiency supercapacitor charger. Conventional two-switch forward converter can be used for charging supercapacitors. However, the efficiency of conventional converters is low because of their switching losses. This study presents a high-efficiency two-switch forward converter for supercapacitor chargers. The proposed converter improves power efficiency by 4 %, from 89 % to 93 %. The proposed converter has the advantages of reduced switch voltage stresses and minimized circulating current when compared to other converter topologies. The performance of the proposed converter is evaluated by experimental results using a 300 W prototype circuit for a 54-V, 35-F supercapacitor bank.
Keywords
I. INTRODUCTION
Supercapacitors have been widely used for automotive and energy conversion systems [1] - [3] . The life and capacity of supercapacitors depend on several factors such as charge mode, maintenance, temperature, and age [4] . Among these factors, the charge mode has the greatest impact on battery life and capacity. Supercapacitors are charged with current and voltage levels by a supercapacitor charger [5] . The supercapacitor charger is designed by using switched mode power supplies. The basic requirements for supercapacitor chargers are small size and high efficiency. A high switching frequency is necessary to achieve a small size. However, as the switching frequency is increased, the efficiency of the supercapacitor chargers is reduced because the switching losses increase. Thus, selecting an optimal converter topology is important for the design of high-efficiency supercapacitor chargers.
The forward converter is a popular DC-DC converter topology for low voltage and high current applications [6] , [7] . In particular, the two-switch forward converter in Fig. 1 is a good candidate for supercapacitor chargers due to its simple structure and low switch voltage stress [8] - [11] . The two switches S1 and S2 are turned on and off simultaneously [10] . The magnetizing current iLm flows into the input source Vi through the reset diodes DC1 and DC2 . Thus, the two-switch forward converter can eliminate the need for a separate demagnetizing winding, which is used in the conventional forward converter. However, when the switches are turned off, the energy stored in the leakage inductor Llk causes high voltage spikes across the switches [11] . These voltage spikes increase the switching losses. Another drawback of the two-switch forward converter is a duty cycle limitation [12] . The maximum duty cycle is limited to 0.5 to guarantee the transformer reset. This small duty cycle operation increases the output filter size and current stress. To cope with these problems, the active-clamping method has recently been applied to the two-switch forward converter [13] , [14] . By using one more power switches in the primary side, zero-voltage switching of the power switches is achieved. However, the voltage stress of the auxiliary switch for the active-clamping circuit is still high. As a result, high-cost switches are usually used.
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Circuit diagram of the conventional two-switch forward converter.
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Circuit diagram of the proposed two-switch forward converter.
To relieve the abovementioned drawbacks, a high-efficiency two-switch forward converter is proposed for supercapacitor chargers. The proposed converter in Fig. 2 can reduce switching losses. The two reset diodes are replaced by two auxiliary switches S3 and S4 . As a result, all of the power switches operate without any voltage spikes. Switching losses can be reduced by zero-voltage switching of the power switches. The duty cycle range is also extended by using one clamping capacitor Cc . Thus, the proposed converter can be used for a high input voltage range of around 300 V ~ 400 V. In addition, the proposed converter has the advantages of reduced switch voltage stresses and minimized circulating current when compared to the other converter topologies. The supercapacitor charging strategy is presented by using a constant current and constant voltage charging control [15] . All of the control functions are implemented in software with a single-chip microcontroller. The proposed converter is realized with minimal hardware at a low-cost. The performance of the proposed converter is evaluated through experimental results by using a 300 W prototype circuit for a 54-V, 35-F supercapacitor bank. The proposed converter improves the converter efficiency by 4 %, from 89 % to 93 %.
II. PROPOSED CONVERTER
- A. Converter Operation
Fig. 2 shows a circuit diagram of the proposed converter. Vi is the input voltage. Vs is the supercapacitor voltage. The primary part consists of power switches ( S1 , S2 , S3 , S4 ), a clamping capacitor ( Cc ), and a transformer ( T ). The power switches are considered to be ideal switches except body diodes D1 ~ D4 and output capacitors C1 ~ C4 . The transformer T has a magnetizing inductor Lm and leakage inductor Llk with a turns ratio of 1 : N where N = Ns / Np . The secondary part consists of output diodes ( Do1 , Do2 ), an output filter inductor ( Ls ), and a supercapacitor bank ( Cs ).
Fig. 3 shows the switching waveforms of the proposed converter during one switching period Ts . The converter has four switching modes during Ts . S1 and S2 are turned on and off simultaneously. S3 and S4 are also turned on and off simultaneously. Then, S1 ( S2 ) and S3 ( S4 ) operate complementarily with a short dead time. When the duty cycle D is based on the on-time of S1 and S2 , the duty cycle of S3 and S4 is 1 – D . Before t = t0 , S3 and S4 are turned off. Voltages VS1 and VS2 are zero when the primary current ip flows through body diodes D1 and D2 .
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Switching waveforms of the proposed converter.
Mode 1 [t0, t1]: At t = t0 , S1 and S2 are turned on at zero voltage. Lm and Llk store energy from Vi . The magnetizing inductor current iLm increases linearly as
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At the secondary side, output diode Do1 is turned on. The output inductor current is flows through output diode Do1 .
Mode 2 [t1, t2]: At t = t1 , S1 and S2 are turned off. The primary current ip charges C1 and C2 and discharges C3 and C4 . VS1 increases from zero to Vi while VS2 increases from zero to Vi + Vc . VS3 decreases from Vi + Vc to zero while VS4 decreases from Vi to zero. Since the switch output capacitor Cs (= C1 = C2 = C3 = C4 ) is very small, the time interval during this mode is considered negligible when compared to Ts . The magnetizing current iLm is considered to be constant. Switch body diodes D3 and D4 conduct the primary current ip at the end of this mode.
Mode 3 [t2, t3]: At t = t2 , S3 and S4 are turned on at zero voltage. The energy stored in Llk is recycled to the clamping capacitor Cc . S3 and S4 are turned on without any voltage spikes. The magnetizing inductor current iLm decreases linearly as:
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At the secondary side, output diode Do2 is turned on. The output inductor current is freewheels through output diode Do2 .
Mode 4 [t3, t4]: At t = t3 , S3 and S4 are turned off. The primary current ip charges C3 and C4 and discharges C1 and C2 . VS1 decreases from Vi to zero while VS2 decreases from Vi + Vc to zero. VS3 increases from zero to Vi + Vc while VS4 increases from zero to Vi . Switch body diodes D1 and D2 conduct the primary current ip . The next switching cycle begins when S1 and S2 are turned on at zero voltage again.
- B. Circuit Analysis
The voltage stress of S1 and S4 is clamped to the input voltage Vi . The voltage stress of S2 and S3 is clamped to the sum of Vi and Vc . For the volt-second balance relation on Lm during Ts , the following relation between Vi and Vc is obtained as:
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By rearranging (3), the clamp capacitor voltage Vc is derived as:
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For the volt-second balance relation on Ls during Ts , the following relation between Vi and Vs is obtained as:
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Fig. 4 shows a graph of the normalized voltage gain between Vi and Vs . As the duty cycle D varies from zero to one, the normalized voltage gain increases linearly. When compared to the duty cycle of the previous two-switch forward converter [10] , the proposed converter has a wide duty cycle range from zero to one. In particular, when the duty cycle D is below 0.5, the clamping capacitor voltage Vc can be lower than the input voltage Vi .
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Graph for the normalized voltage gain between the input voltage Vi and supercapacitor voltage Vs.
- C. Zero-Voltage Switching Conditions
In order to achieve zero-voltage switching of S3 and S4 , the energy stored in Lm and Ls should be larger than the energy stored in the switch output capacitors, as suggested in [16] . The zero-voltage switching condition of S3 and S4 is:
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Similarly, in order to achieve zero-voltage switching of S1 and S2 , the energy stored in Lm and Ls should be larger than the energy stored in the switch output capacitors. The zero-voltage switching condition of S1 and S2 is:
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- D. Voltage and Current Stresses
In the proposed converter, the voltage stress of S1 and S4 is clamped to the input voltage. On the other hand, the voltage stress of S2 and S3 is the sum of the input voltage and the clamping capacitor voltage. The voltage stress of S2 and S3 can be changed with the duty ratio D . When the duty cycle D is below 0.5, the voltage stress of S2 and S3 can be lower than the input voltage Vi . This is one of the advantages of the proposed converter when compared to the other full-bridge (FB) converter topologies. Table I summarizes the voltage and current stresses of the proposed converter.
VOLTAGE AND CURRENT STRESSES OF THE RROPOSED CONVERTER
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VOLTAGE AND CURRENT STRESSES OF THE RROPOSED CONVERTER
- E. Circulating Current
In the phase-shifted full-bridge (PSFB) converter [17] , a circulating current is inevitable during the freewheeling period. It is especially large at a high input voltage, causing the large conduction losses associated with the transformer and primary switches. This is because there exists a non-powering period, as shown in Fig. 5 (a), where a zero voltage is applied to the transformer winding. The power is not delivered to the secondary side even though the current is circulating at the primary side. On the other hand, in the proposed converter, there is no freewheeling period except for a small dead-time period, as shown in Fig. 5 (b). The power can always be delivered to the secondary side. There is no zero voltage period across the transformer winding. This is another advantage of the proposed converter when compared to the FB converter topologies.
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Comparison of key waveforms between the PSFB converter and proposed converter: (a) PSFB converter and (b) proposed converter.
- F. Averaged Model
In the proposed converter, the switch power stage, together with the transformers and rectifier, can be substituted with an equivalent pulse source Vg , as illustrated in Fig. 6 . This pulsating source can be averaged to a constant dc voltage source Vd . Assume that the output filter inductor current is in the continuous-conduction mode. The average model can then be derived as an equivalent buck converter topology, with an equivalent switching frequency. By using the state-space averaging method [18] , the state-space averaged dc model is expressed as:
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Derivation of the average model.
where:
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where Rs is the equivalent resistance of the supercapacitor bank. Solving (8), the following equations can be obtained as:
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The state-space averaged ac model is expressed as:
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where:
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where
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is the small-signal duty ratio. Solving (11), the following equations can be obtained as:
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III. CONTROL STRATEGY
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Control block diagram of the supercapacitor charging controller.
Fig. 7 shows a control block diagram of the proposed converter. It is assumed that the output filter inductor current is flows continuously. When S1 and S2 are turned on, the inductor current is increases. The following voltage equation is obtained as:
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On the other hand, when S3 and S4 are turned on, the inductor current is freewheels through diode Do2 . Then, the following voltage equation is obtained as:
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Depending on the duty cycle D of S1 and S2 , the average inductor voltage for Ts gives the supercapacitor current variation Δ is as:
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By rearranging (14):
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Here, the duty cycle D is represented as:
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Dn is a nominal duty cycle. Dc is a controlled duty cycle. The nominal duty cycle Dn and the controlled duty cycle Dc can be represented as:
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Then, the duty cycle D becomes
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To force the supercapacitor current is to track its current command is * , a proportional-integral (PI)-type current controller is used for the controlled duty cycle Dc as:
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The current error ierr is calculated by comparing the current command is * to the measured current is . kp and ki are the proportional and integral control gains, respectively. To regulate the supercapacitor voltage Vs , a PI-type voltage controller is used. The voltage error verr is calculated by comparing the reference supercapacitor voltage Vs * to the measured supercapacitor voltage Vs . The voltage controller generates the current command is . is.limit is the maximum charging current of the supercapacitor. If is is higher than is.limit , the supercapacitor is charged with a constant current. On the other hand, if is is lower than is.limit , the supercapacitor is charged with a constant voltage.
IV. EXPERIMENTAL RESULTS
A 300 W prototype circuit has been built and tested to verify the operation principles and performance of the proposed converter. The input voltage ranges from 300 V to 400 V. The supercapacitor voltage ranges from 30 V to 48 V. Table II shows the values of the major circuit parameters. For the power switching devices, S1 = S2 = S3 = S4 = FQA24N50C3 (Fairchild) and Do1 = Do2 = DSEK6002A (IXYS) are used. The current stresses of the switching devices are different, as shown in Table I . The proposed converter adopts FQA24N50 C3 s for all of the four switches by considering the maximum current stresses of the switches. The FQA24N50C3 (24 A, 500 V) can withstand the maximum allowable current stresses of all of the power switches. The power switches operate at a constant switching period of 20 μsec with a dead time of 330 nsec. The transformer has a primary winding turns of Np = 20 and a secondary winding turns of Ns = 10. The controller is digitally implemented by using a single-chip microcontroller dsPIC30F3011 (Mircochip)
MAIN CIRCUIT PARAMETERS
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MAIN CIRCUIT PARAMETERS
The input voltage Vi , supercapacitor voltage Vs , and supercapacitor current is are measured by voltage and current sensing amplifiers. They are sensed through the 10-bit A/D converter in the microcontroller. After the voltage and current signals are read, the duty cycle D is obtained by calculating Dn and Dc . Fig. 8 shows a picture of the hardware prototype including the proposed converter. The designed prototype system includes a power-factor correction circuit and the proposed dc-dc converter.
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Picture of the hardware prototype including the proposed converter.
In order to verify the proposed converter operation and its control method, simulation results are presented in Fig. 9 through Fig. 11 by using PSIM 9.0 software. In the simulation, the control block is implemented by C-language-based DLL blocks. Fig. 9 shows the simulation waveforms when D is 0.4. Fig. 9 (a) shows the primary current ip and switch voltages VS1 and VS4 . Fig. 9 (b) shows the primary current ip and switch voltages VS2 and VS3 . Fig. 10 shows the simulation waveforms when D is 0.6. It is shown that the proposed converter can operate when the duty cycle is over 0.5. It is also shown that all of the power switches are turned on at zero-voltage without any voltage spikes. Fig. 11 shows the simulation waveforms of the proposed converter for charging the supercapacitor banks. Cs = 35-F and Rs = 4.5 mΩ are used for the supercapacitor bank parameters. As shown in Fig. 11 , as the proposed converter supplies a constant current of 15 A, the supercapacitor bank increases linearly. When the supercapacitor voltage reaches the maximum allowable voltage at 48 V, the supercapacitor voltage is regulated constantly and the current decreases.
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Simulation results of the proposed converter when D is 0.4: (a) primary current ip and switch voltages VS1 and VS4 and (b) primary current ip and switch voltages VS2 and VS3.
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Simulation results of the proposed converter when D is 0.6: (a) primary current ip and switch voltages VS1 and VS4 and (b) primary current ip and switch voltages VS2 and VS3.
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Simulation waveforms of the proposed converter for charging the supercapacitor banks.
The conventional two-switch forward converter in [11] has been designed and tested for a performance comparison with the proposed converter. Fig. 12 shows the experimental waveforms of the conventional two-switch forward converter. It shows the primary current ip and switch voltages VS1 and VS2 of the conventional two-switch forward converter. When the switches are turned off, high voltage spikes are observed in Fig. 12 . These voltage spikes increase the switching losses. Fig. 13 shows the experimental waveforms of the proposed converter when the duty cycle D is 0.4. Fig. 13 (a) shows the primary current ip and switch voltages VS1 and VS4 . Fig. 13 (b) shows the primary current ip and switch voltages VS2 and VS3 . As shown in Fig. 13 (a) and (b), when the switches are turned off, voltage spikes are not observed across the switches. Fig. 13 (c) shows switch voltages VS1 and VS2 and switch currents iS1 and iS2 . Fig. 13 (d) shows switch voltages VS3 and VS4 and switch currents iS3 and iS4 . As shown in Fig. 13 (c) and (d), before the primary current ip changes its direction, the switch voltage is zero. Zero-voltage switching of the power switches is achieved, which significantly reduces the switching power losses.
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Experimental waveforms of the conventional converter: primary current ip and switch voltages VS1 and VS2.
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Experimental waveforms of the proposed converter when D is 0.4: (a) primary current ip and switch voltages VS1 and VS4, (b) primary current ip and switch voltages VS2 and VS3, (c) switch voltages VS1 and VS2 and switch currents iS1 and iS2 and (d) switch voltages VS3 and VS4 and switch currents iS3 and iS4.
Fig. 14 shows the experimental waveforms of the proposed converter when the duty cycle D is 0.6. Fig. 14 (a) shows the primary current ip and switch voltages VS1 and VS4 . Fig. 14 (b) shows the primary current ip and switch voltages VS2 and VS3 . As shown in Fig. 14 (a) and (b), zero-voltage switching of the power switches is achieved when the duty cycle D is 0.6. It can also be seen that the proposed converter can operate when the duty cycle is over 0.5. Fig. 15 shows the experimental waveforms when the proposed converter charges the supercapacitor bank. A supercapacitor bank is used, which consists of 20 supercapacitors connected in series. The rated capacitance per capacitor is 700 F. Its rated voltage is 2.7 V. Its equivalent resistance is 4.5 mΩ. The total equivalent resistance of the supercapacitor bank is 90 mΩ. As shown in Fig. 15 , the proposed converter charges the supercapacitor bank by controlling the output filter inductor current is . The supercapacitor voltage increases from 35 V to 40 V linearly when the current command is * is 3 A.
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Experimental waveforms of the proposed converter when D is 0.6: (a) primary current ip and switch voltages VS1 and VS4 and (b) primary current ip and switch voltages VS2 and VS3.
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Experimental waveforms of the proposed converter for charging the supercapacitor bank: supercapacitor voltage Vs and output filter inductor current is.
Fig. 16 shows the experimental waveforms when the supercapacitor voltage Vs reaches a maximum voltage of 48 V. It also shows the supercapacitor voltage Vs and the output filter inductor current is . The output filter inductor current is flows continuously. Fig. 17 shows the dynamic response of the proposed converter when it charges the supercapacitor bank with a constant current of 15 A. As the proposed converter supplies a constant current of 15 A, the supercapacitor bank increases linearly. At the moment that the supercapacitor voltage reaches the maximum allowable voltage at 48 V, the supercapacitor voltage is regulated constantly and the current decreases. In order to evaluate the efficiency, the conventional two-switch forward converter [11] and the proposed converter have been tested for the same power level. Fig. 18 shows the measured efficiencies of the converters for different power levels. The conventional two-switch forward converter achieves an efficiency of 89 % for 300 W. On the other hand, the proposed converter achieves an efficiency of 93 % for 300 W. The proposed converter improves the converter efficiency by 4 % by achieving zero-voltage switching of the power switches. The duty cycle range is also extended for the use of the proposed converter at a high input voltage range of around 300 V to 400 V. In order to compare the efficiency of the proposed converter with that of the PSFB converter [17] , Fig. 19 shows the measured efficiencies of the converters for different power levels. The PSFB converter achieves an efficiency of 92.5 % while the proposed converter achieves an efficiency of 93 % for 300 W. The proposed converter improves the converter efficiency by 0.5 % by reducing the voltage stresses and by minimizing the circulating currents.
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Experimental waveforms of the proposed converter for charging the supercapacitor bank: supercapacitor voltage Vs and output filter inductor current is.
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Experimental waveforms of the proposed converter for charging the supercapacitor bank: supercapacitor voltage Vs and output filter inductor current is.
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Measured efficiencies for different power levels.
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Measured efficiencies for different power levels.
V. CONCLUSIONS
This paper proposed a high-efficiency two-switch forward converter for supercapacitor chargers. The proposed converter reduces switching losses with an extended duty cycle. The power switches are turned on at zero voltage without any voltage spikes. Zero-voltage switching of the power switches is achieved. The power efficiency is increased by reducing the switching losses. The proposed converter has the advantages of reduced switch voltage stresses and a minimized circulating current when compared to the other converter topologies. The supercapacitor charging strategy has been also presented by using a constant current and constant voltage charging control. All of the control functions are implemented in software with a single-chip microcontroller. The performance of the proposed converter has been verified through experimental results using a 300 W prototype circuit for a 54-V, 35-F supercapacitor bank. The proposed converter improves power efficiency by 4 %, from 89 % to 93 % at the rated power.
Acknowledgements
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MISP) (2010-0028509).
BIO
Woo-Young Choi was born in Gwangju, South Korea, in 1979. He received his B.S. in Electrical Engineering from Chonnam National University, Gwangju, South Korea, in 2004, and his Ph.D. in Electronic and Electrical Engineering from the Pohang University of Science and Technology (POSTECH), Pohang, South Korea, in 2009. Since 2010, he has been with the Division of Electronic Engineering at Chonbuk National University, Jeonju, South Korea, where is currently working as an Assistant Professor. His current research interests include power electronics and controlfor high-efficiency switching power converter designs.
Min-Kwon Yang was born in Jeonju, South Korea, in 1987. He received his B.S. in Electronic Engineering from Chonbuk National University, Jeonju, South Korea, in 2012. He is currently working toward his Ph.D. in Electronic Engineering at Chonbuk Nation University.
His current research interests include digital power converters for high efficiency and renewable energies.
Yongsug Suh was born in Seoul, South Korea. He received his B.S. and M.S. in Electrical Engineering from Yonsei University, Seoul, South Korea, in 1991 and 1993, respectively, and his Ph.D. in Electrical Engineering from the University of Wisconsin, Madison, WI, USA, in 2004. From 1993 to 1998, he was an Application Engineer in the Power Semiconductor Division of Samsung Electronics Co. From 2004 to 2008, he was a Senior Engineer in the Power Electronics and Medium Voltage Drives Division of ABB, Turgi, Switzerland. Since 2008, he has been with the Department of Electrical Engineering, Chonbuk National University, Jeonju, South Korea, where he is currently an Associate Professor. His current research interests include the power conversion systems of high power for renewable energy sources and medium voltage electric drive systems.
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