This paper proposes a highefficiency supercapacitor charger. Conventional twoswitch forward converter can be used for charging supercapacitors. However, the efficiency of conventional converters is low because of their switching losses. This study presents a highefficiency twoswitch forward converter for supercapacitor chargers. The proposed converter improves power efficiency by 4 %, from 89 % to 93 %. The proposed converter has the advantages of reduced switch voltage stresses and minimized circulating current when compared to other converter topologies. The performance of the proposed converter is evaluated by experimental results using a 300 W prototype circuit for a 54V, 35F supercapacitor bank.
I. INTRODUCTION
Supercapacitors have been widely used for automotive and energy conversion systems
[1]

[3]
. The life and capacity of supercapacitors depend on several factors such as charge mode, maintenance, temperature, and age
[4]
. Among these factors, the charge mode has the greatest impact on battery life and capacity. Supercapacitors are charged with current and voltage levels by a supercapacitor charger
[5]
. The supercapacitor charger is designed by using switched mode power supplies. The basic requirements for supercapacitor chargers are small size and high efficiency. A high switching frequency is necessary to achieve a small size. However, as the switching frequency is increased, the efficiency of the supercapacitor chargers is reduced because the switching losses increase. Thus, selecting an optimal converter topology is important for the design of highefficiency supercapacitor chargers.
The forward converter is a popular DCDC converter topology for low voltage and high current applications
[6]
,
[7]
. In particular, the twoswitch forward converter in
Fig. 1
is a good candidate for supercapacitor chargers due to its simple structure and low switch voltage stress
[8]

[11]
. The two switches
S_{1}
and
S_{2}
are turned on and off simultaneously
[10]
. The magnetizing current
i_{Lm}
flows into the input source
V_{i}
through the reset diodes
D_{C1}
and
D_{C2}
. Thus, the twoswitch forward converter can eliminate the need for a separate demagnetizing winding, which is used in the conventional forward converter. However, when the switches are turned off, the energy stored in the leakage inductor
L_{lk}
causes high voltage spikes across the switches
[11]
. These voltage spikes increase the switching losses. Another drawback of the twoswitch forward converter is a duty cycle limitation
[12]
. The maximum duty cycle is limited to 0.5 to guarantee the transformer reset. This small duty cycle operation increases the output filter size and current stress. To cope with these problems, the activeclamping method has recently been applied to the twoswitch forward converter
[13]
,
[14]
. By using one more power switches in the primary side, zerovoltage switching of the power switches is achieved. However, the voltage stress of the auxiliary switch for the activeclamping circuit is still high. As a result, highcost switches are usually used.
Circuit diagram of the conventional twoswitch forward converter.
Circuit diagram of the proposed twoswitch forward converter.
To relieve the abovementioned drawbacks, a highefficiency twoswitch forward converter is proposed for supercapacitor chargers. The proposed converter in
Fig. 2
can reduce switching losses. The two reset diodes are replaced by two auxiliary switches
S_{3}
and
S_{4}
. As a result, all of the power switches operate without any voltage spikes. Switching losses can be reduced by zerovoltage switching of the power switches. The duty cycle range is also extended by using one clamping capacitor
C_{c}
. Thus, the proposed converter can be used for a high input voltage range of around 300 V ~ 400 V. In addition, the proposed converter has the advantages of reduced switch voltage stresses and minimized circulating current when compared to the other converter topologies. The supercapacitor charging strategy is presented by using a constant current and constant voltage charging control
[15]
. All of the control functions are implemented in software with a singlechip microcontroller. The proposed converter is realized with minimal hardware at a lowcost. The performance of the proposed converter is evaluated through experimental results by using a 300 W prototype circuit for a 54V, 35F supercapacitor bank. The proposed converter improves the converter efficiency by 4 %, from 89 % to 93 %.
II. PROPOSED CONVERTER
 A. Converter Operation
Fig. 2
shows a circuit diagram of the proposed converter.
V_{i}
is the input voltage.
V_{s}
is the supercapacitor voltage. The primary part consists of power switches (
S_{1}
,
S_{2}
,
S_{3}
,
S_{4}
), a clamping capacitor (
C_{c}
), and a transformer (
T
). The power switches are considered to be ideal switches except body diodes
D_{1}
~
D_{4}
and output capacitors
C_{1}
~
C_{4}
. The transformer
T
has a magnetizing inductor
L_{m}
and leakage inductor
L_{lk}
with a turns ratio of 1 :
N
where
N
=
N_{s}
/
N_{p}
. The secondary part consists of output diodes (
D_{o1}
,
D_{o2}
), an output filter inductor (
L_{s}
), and a supercapacitor bank (
C_{s}
).
Fig. 3
shows the switching waveforms of the proposed converter during one switching period
T_{s}
. The converter has four switching modes during
T_{s}
.
S_{1}
and
S_{2}
are turned on and off simultaneously.
S_{3}
and
S_{4}
are also turned on and off simultaneously. Then,
S_{1}
(
S_{2}
) and
S_{3}
(
S_{4}
) operate complementarily with a short dead time. When the duty cycle
D
is based on the ontime of
S_{1}
and
S_{2}
, the duty cycle of
S_{3}
and
S_{4}
is 1 –
D
. Before
t
=
t_{0}
,
S_{3}
and
S_{4}
are turned off. Voltages
V_{S1}
and
V_{S2}
are zero when the primary current
i_{p}
flows through body diodes
D_{1}
and
D_{2}
.
Switching waveforms of the proposed converter.
Mode 1 [t_{0}, t_{1}]:
At
t
=
t_{0}
,
S_{1}
and
S_{2}
are turned on at zero voltage.
L_{m}
and
L_{lk}
store energy from
V_{i}
. The magnetizing inductor current
i_{Lm}
increases linearly as
At the secondary side, output diode
D_{o1}
is turned on. The output inductor current
i_{s}
flows through output diode
D_{o1}
.
Mode 2 [t_{1}, t_{2}]:
At
t
=
t_{1}
,
S_{1}
and
S_{2}
are turned off. The primary current
i_{p}
charges
C_{1}
and
C_{2}
and discharges
C_{3}
and
C_{4}
.
V_{S1}
increases from zero to
V_{i}
while
V_{S2}
increases from zero to
V_{i}
+
V_{c}
.
V_{S3}
decreases from
V_{i}
+
V_{c}
to zero while
V_{S4}
decreases from
V_{i}
to zero. Since the switch output capacitor
C_{s}
(=
C_{1}
=
C_{2}
=
C_{3}
=
C_{4}
) is very small, the time interval during this mode is considered negligible when compared to
T_{s}
. The magnetizing current
i_{Lm}
is considered to be constant. Switch body diodes
D_{3}
and
D_{4}
conduct the primary current
i_{p}
at the end of this mode.
Mode 3 [t_{2}, t_{3}]:
At
t
=
t_{2}
,
S_{3}
and
S_{4}
are turned on at zero voltage. The energy stored in
L_{lk}
is recycled to the clamping capacitor
C_{c}
.
S_{3}
and
S_{4}
are turned on without any voltage spikes. The magnetizing inductor current
i_{Lm}
decreases linearly as:
At the secondary side, output diode
D_{o2}
is turned on. The output inductor current
i_{s}
freewheels through output diode
D_{o2}
.
Mode 4 [t_{3}, t_{4}]:
At
t
=
t_{3}
,
S_{3}
and
S_{4}
are turned off. The primary current
i_{p}
charges
C_{3}
and
C_{4}
and discharges
C_{1}
and
C_{2}
.
V_{S1}
decreases from
V_{i}
to zero while
V_{S2}
decreases from
V_{i}
+
V_{c}
to zero.
V_{S3}
increases from zero to
V_{i}
+
V_{c}
while
V_{S4}
increases from zero to
V_{i}
. Switch body diodes
D_{1}
and
D_{2}
conduct the primary current
i_{p}
. The next switching cycle begins when
S_{1}
and
S_{2}
are turned on at zero voltage again.
 B. Circuit Analysis
The voltage stress of
S_{1}
and
S_{4}
is clamped to the input voltage
V_{i}
. The voltage stress of
S_{2}
and
S_{3}
is clamped to the sum of
V_{i}
and
V_{c}
. For the voltsecond balance relation on
L_{m}
during
T_{s}
, the following relation between
V_{i}
and
V_{c}
is obtained as:
By rearranging (3), the clamp capacitor voltage
V_{c}
is derived as:
For the voltsecond balance relation on
L_{s}
during
T_{s}
, the following relation between
V_{i}
and
V_{s}
is obtained as:
Fig. 4
shows a graph of the normalized voltage gain between
V_{i}
and
V_{s}
. As the duty cycle
D
varies from zero to one, the normalized voltage gain increases linearly. When compared to the duty cycle of the previous twoswitch forward converter
[10]
, the proposed converter has a wide duty cycle range from zero to one. In particular, when the duty cycle
D
is below 0.5, the clamping capacitor voltage
V_{c}
can be lower than the input voltage
V_{i}
.
Graph for the normalized voltage gain between the input voltage V_{i} and supercapacitor voltage V_{s}.
 C. ZeroVoltage Switching Conditions
In order to achieve zerovoltage switching of
S_{3}
and
S_{4}
, the energy stored in
L_{m}
and
L_{s}
should be larger than the energy stored in the switch output capacitors, as suggested in
[16]
. The zerovoltage switching condition of
S_{3}
and
S_{4}
is:
Similarly, in order to achieve zerovoltage switching of
S_{1}
and
S_{2}
, the energy stored in
L_{m}
and
L_{s}
should be larger than the energy stored in the switch output capacitors. The zerovoltage switching condition of
S_{1}
and
S_{2}
is:
 D. Voltage and Current Stresses
In the proposed converter, the voltage stress of
S_{1}
and
S_{4}
is clamped to the input voltage. On the other hand, the voltage stress of
S_{2}
and
S_{3}
is the sum of the input voltage and the clamping capacitor voltage. The voltage stress of
S_{2}
and
S_{3}
can be changed with the duty ratio
D
. When the duty cycle
D
is below 0.5, the voltage stress of
S_{2}
and
S_{3}
can be lower than the input voltage
V_{i}
. This is one of the advantages of the proposed converter when compared to the other fullbridge (FB) converter topologies.
Table I
summarizes the voltage and current stresses of the proposed converter.
VOLTAGE AND CURRENT STRESSES OF THE RROPOSED CONVERTER
VOLTAGE AND CURRENT STRESSES OF THE RROPOSED CONVERTER
 E. Circulating Current
In the phaseshifted fullbridge (PSFB) converter
[17]
, a circulating current is inevitable during the freewheeling period. It is especially large at a high input voltage, causing the large conduction losses associated with the transformer and primary switches. This is because there exists a nonpowering period, as shown in
Fig. 5
(a), where a zero voltage is applied to the transformer winding. The power is not delivered to the secondary side even though the current is circulating at the primary side. On the other hand, in the proposed converter, there is no freewheeling period except for a small deadtime period, as shown in
Fig. 5
(b). The power can always be delivered to the secondary side. There is no zero voltage period across the transformer winding. This is another advantage of the proposed converter when compared to the FB converter topologies.
Comparison of key waveforms between the PSFB converter and proposed converter: (a) PSFB converter and (b) proposed converter.
 F. Averaged Model
In the proposed converter, the switch power stage, together with the transformers and rectifier, can be substituted with an equivalent pulse source
V_{g}
, as illustrated in
Fig. 6
. This pulsating source can be averaged to a constant dc voltage source
V_{d}
. Assume that the output filter inductor current is in the continuousconduction mode. The average model can then be derived as an equivalent buck converter topology, with an equivalent switching frequency. By using the statespace averaging method
[18]
, the statespace averaged dc model is expressed as:
Derivation of the average model.
where:
where
R_{s}
is the equivalent resistance of the supercapacitor bank. Solving (8), the following equations can be obtained as:
The statespace averaged ac model is expressed as:
where:
where
is the smallsignal duty ratio. Solving (11), the following equations can be obtained as:
III. CONTROL STRATEGY
Control block diagram of the supercapacitor charging controller.
Fig. 7
shows a control block diagram of the proposed converter. It is assumed that the output filter inductor current
i_{s}
flows continuously. When
S_{1}
and
S_{2}
are turned on, the inductor current
i_{s}
increases. The following voltage equation is obtained as:
On the other hand, when
S_{3}
and
S_{4}
are turned on, the inductor current
i_{s}
freewheels through diode
D_{o2}
. Then, the following voltage equation is obtained as:
Depending on the duty cycle
D
of
S_{1}
and
S_{2}
, the average inductor voltage for
T_{s}
gives the supercapacitor current variation Δ
i_{s}
as:
By rearranging (14):
Here, the duty cycle
D
is represented as:
D_{n}
is a nominal duty cycle.
D_{c}
is a controlled duty cycle. The nominal duty cycle
D_{n}
and the controlled duty cycle
D_{c}
can be represented as:
Then, the duty cycle
D
becomes
To force the supercapacitor current
i_{s}
to track its current command
i_{s}
^{*}
, a proportionalintegral (PI)type current controller is used for the controlled duty cycle
D_{c}
as:
The current error
i_{err}
is calculated by comparing the current command
i_{s}
^{*}
to the measured current
i_{s}
.
k_{p}
and
k_{i}
are the proportional and integral control gains, respectively. To regulate the supercapacitor voltage
V_{s}
, a PItype voltage controller is used. The voltage error
v_{err}
is calculated by comparing the reference supercapacitor voltage
V_{s}
^{*}
to the measured supercapacitor voltage
V_{s}
. The voltage controller generates the current command
i_{s}
^{’}
.
i_{s.limit}
is the maximum charging current of the supercapacitor. If
i_{s}
^{’}
is higher than
i_{s.limit}
, the supercapacitor is charged with a constant current. On the other hand, if
i_{s}
^{’}
is lower than
i_{s.limit}
, the supercapacitor is charged with a constant voltage.
IV. EXPERIMENTAL RESULTS
A 300 W prototype circuit has been built and tested to verify the operation principles and performance of the proposed converter. The input voltage ranges from 300 V to 400 V. The supercapacitor voltage ranges from 30 V to 48 V.
Table II
shows the values of the major circuit parameters. For the power switching devices,
S_{1}
=
S_{2}
=
S_{3}
=
S_{4}
= FQA24N50C3 (Fairchild) and
D_{o1}
=
D_{o2}
= DSEK6002A (IXYS) are used. The current stresses of the switching devices are different, as shown in
Table I
. The proposed converter adopts FQA24N50
C_{3}
s for all of the four switches by considering the maximum current stresses of the switches. The FQA24N50C3 (24 A, 500 V) can withstand the maximum allowable current stresses of all of the power switches. The power switches operate at a constant switching period of 20 μsec with a dead time of 330 nsec. The transformer has a primary winding turns of
N_{p}
= 20 and a secondary winding turns of
N_{s}
= 10. The controller is digitally implemented by using a singlechip microcontroller dsPIC30F3011 (Mircochip)
MAIN CIRCUIT PARAMETERS
The input voltage
V_{i}
, supercapacitor voltage
V_{s}
, and supercapacitor current
i_{s}
are measured by voltage and current sensing amplifiers. They are sensed through the 10bit A/D converter in the microcontroller. After the voltage and current signals are read, the duty cycle
D
is obtained by calculating
D_{n}
and
D_{c}
.
Fig. 8
shows a picture of the hardware prototype including the proposed converter. The designed prototype system includes a powerfactor correction circuit and the proposed dcdc converter.
Picture of the hardware prototype including the proposed converter.
In order to verify the proposed converter operation and its control method, simulation results are presented in
Fig. 9
through
Fig. 11
by using PSIM 9.0 software. In the simulation, the control block is implemented by Clanguagebased DLL blocks.
Fig. 9
shows the simulation waveforms when
D
is 0.4.
Fig. 9
(a) shows the primary current
i_{p}
and switch voltages
V_{S1}
and
V_{S4}
.
Fig. 9
(b) shows the primary current
i_{p}
and switch voltages
V_{S2}
and
V_{S3}
.
Fig. 10
shows the simulation waveforms when
D
is 0.6. It is shown that the proposed converter can operate when the duty cycle is over 0.5. It is also shown that all of the power switches are turned on at zerovoltage without any voltage spikes.
Fig. 11
shows the simulation waveforms of the proposed converter for charging the supercapacitor banks.
C_{s}
= 35F and
R_{s}
= 4.5 mΩ are used for the supercapacitor bank parameters. As shown in
Fig. 11
, as the proposed converter supplies a constant current of 15 A, the supercapacitor bank increases linearly. When the supercapacitor voltage reaches the maximum allowable voltage at 48 V, the supercapacitor voltage is regulated constantly and the current decreases.
Simulation results of the proposed converter when D is 0.4: (a) primary current i_{p} and switch voltages V_{S1} and V_{S4} and (b) primary current i_{p} and switch voltages V_{S2} and V_{S3}.
Simulation results of the proposed converter when D is 0.6: (a) primary current i_{p} and switch voltages V_{S1} and V_{S4} and (b) primary current i_{p} and switch voltages V_{S2} and V_{S3}.
Simulation waveforms of the proposed converter for charging the supercapacitor banks.
The conventional twoswitch forward converter in
[11]
has been designed and tested for a performance comparison with the proposed converter.
Fig. 12
shows the experimental waveforms of the conventional twoswitch forward converter. It shows the primary current
i_{p}
and switch voltages
V_{S1}
and
V_{S2}
of the conventional twoswitch forward converter. When the switches are turned off, high voltage spikes are observed in
Fig. 12
. These voltage spikes increase the switching losses.
Fig. 13
shows the experimental waveforms of the proposed converter when the duty cycle
D
is 0.4.
Fig. 13
(a) shows the primary current
i_{p}
and switch voltages
V_{S1}
and
V_{S4}
.
Fig. 13
(b) shows the primary current
i_{p}
and switch voltages
V_{S2}
and
V_{S3}
. As shown in
Fig. 13
(a) and (b), when the switches are turned off, voltage spikes are not observed across the switches.
Fig. 13
(c) shows switch voltages
V_{S1}
and
V_{S2}
and switch currents
i_{S1}
and
i_{S2}
.
Fig. 13
(d) shows switch voltages
V_{S3}
and
V_{S4}
and switch currents
i_{S3}
and
i_{S4}
. As shown in
Fig. 13
(c) and (d), before the primary current
i_{p}
changes its direction, the switch voltage is zero. Zerovoltage switching of the power switches is achieved, which significantly reduces the switching power losses.
Experimental waveforms of the conventional converter: primary current i_{p} and switch voltages V_{S1} and V_{S2}.
Experimental waveforms of the proposed converter when D is 0.4: (a) primary current i_{p} and switch voltages V_{S1} and V_{S4}, (b) primary current i_{p} and switch voltages V_{S2} and V_{S3}, (c) switch voltages V_{S1} and V_{S2} and switch currents i_{S1} and i_{S2} and (d) switch voltages V_{S3} and V_{S4} and switch currents i_{S3} and i_{S4}.
Fig. 14
shows the experimental waveforms of the proposed converter when the duty cycle
D
is 0.6.
Fig. 14
(a) shows the primary current
i_{p}
and switch voltages
V_{S1}
and
V_{S4}
.
Fig. 14
(b) shows the primary current
i_{p}
and switch voltages
V_{S2}
and
V_{S3}
. As shown in
Fig. 14
(a) and (b), zerovoltage switching of the power switches is achieved when the duty cycle
D
is 0.6. It can also be seen that the proposed converter can operate when the duty cycle is over 0.5.
Fig. 15
shows the experimental waveforms when the proposed converter charges the supercapacitor bank. A supercapacitor bank is used, which consists of 20 supercapacitors connected in series. The rated capacitance per capacitor is 700 F. Its rated voltage is 2.7 V. Its equivalent resistance is 4.5 mΩ. The total equivalent resistance of the supercapacitor bank is 90 mΩ. As shown in
Fig. 15
, the proposed converter charges the supercapacitor bank by controlling the output filter inductor current
i_{s}
. The supercapacitor voltage increases from 35 V to 40 V linearly when the current command
i_{s}
^{*}
is 3 A.
Experimental waveforms of the proposed converter when D is 0.6: (a) primary current i_{p} and switch voltages V_{S1} and V_{S4} and (b) primary current i_{p} and switch voltages V_{S2} and V_{S3}.
Experimental waveforms of the proposed converter for charging the supercapacitor bank: supercapacitor voltage V_{s} and output filter inductor current i_{s}.
Fig. 16
shows the experimental waveforms when the supercapacitor voltage
V_{s}
reaches a maximum voltage of 48 V. It also shows the supercapacitor voltage
V_{s}
and the output filter inductor current
i_{s}
. The output filter inductor current
i_{s}
flows continuously.
Fig. 17
shows the dynamic response of the proposed converter when it charges the supercapacitor bank with a constant current of 15 A. As the proposed converter supplies a constant current of 15 A, the supercapacitor bank increases linearly. At the moment that the supercapacitor voltage reaches the maximum allowable voltage at 48 V, the supercapacitor voltage is regulated constantly and the current decreases. In order to evaluate the efficiency, the conventional twoswitch forward converter
[11]
and the proposed converter have been tested for the same power level.
Fig. 18
shows the measured efficiencies of the converters for different power levels. The conventional twoswitch forward converter achieves an efficiency of 89 % for 300 W. On the other hand, the proposed converter achieves an efficiency of 93 % for 300 W. The proposed converter improves the converter efficiency by 4 % by achieving zerovoltage switching of the power switches. The duty cycle range is also extended for the use of the proposed converter at a high input voltage range of around 300 V to 400 V. In order to compare the efficiency of the proposed converter with that of the PSFB converter
[17]
,
Fig. 19
shows the measured efficiencies of the converters for different power levels. The PSFB converter achieves an efficiency of 92.5 % while the proposed converter achieves an efficiency of 93 % for 300 W. The proposed converter improves the converter efficiency by 0.5 % by reducing the voltage stresses and by minimizing the circulating currents.
Experimental waveforms of the proposed converter for charging the supercapacitor bank: supercapacitor voltage V_{s} and output filter inductor current i_{s}.
Experimental waveforms of the proposed converter for charging the supercapacitor bank: supercapacitor voltage V_{s} and output filter inductor current i_{s}.
Measured efficiencies for different power levels.
Measured efficiencies for different power levels.
V. CONCLUSIONS
This paper proposed a highefficiency twoswitch forward converter for supercapacitor chargers. The proposed converter reduces switching losses with an extended duty cycle. The power switches are turned on at zero voltage without any voltage spikes. Zerovoltage switching of the power switches is achieved. The power efficiency is increased by reducing the switching losses. The proposed converter has the advantages of reduced switch voltage stresses and a minimized circulating current when compared to the other converter topologies. The supercapacitor charging strategy has been also presented by using a constant current and constant voltage charging control. All of the control functions are implemented in software with a singlechip microcontroller. The performance of the proposed converter has been verified through experimental results using a 300 W prototype circuit for a 54V, 35F supercapacitor bank. The proposed converter improves power efficiency by 4 %, from 89 % to 93 % at the rated power.
Acknowledgements
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MISP) (20100028509).
BIO
WooYoung Choi was born in Gwangju, South Korea, in 1979. He received his B.S. in Electrical Engineering from Chonnam National University, Gwangju, South Korea, in 2004, and his Ph.D. in Electronic and Electrical Engineering from the Pohang University of Science and Technology (POSTECH), Pohang, South Korea, in 2009. Since 2010, he has been with the Division of Electronic Engineering at Chonbuk National University, Jeonju, South Korea, where is currently working as an Assistant Professor. His current research interests include power electronics and controlfor highefficiency switching power converter designs.
MinKwon Yang was born in Jeonju, South Korea, in 1987. He received his B.S. in Electronic Engineering from Chonbuk National University, Jeonju, South Korea, in 2012. He is currently working toward his Ph.D. in Electronic Engineering at Chonbuk Nation University.
His current research interests include digital power converters for high efficiency and renewable energies.
Yongsug Suh was born in Seoul, South Korea. He received his B.S. and M.S. in Electrical Engineering from Yonsei University, Seoul, South Korea, in 1991 and 1993, respectively, and his Ph.D. in Electrical Engineering from the University of Wisconsin, Madison, WI, USA, in 2004. From 1993 to 1998, he was an Application Engineer in the Power Semiconductor Division of Samsung Electronics Co. From 2004 to 2008, he was a Senior Engineer in the Power Electronics and Medium Voltage Drives Division of ABB, Turgi, Switzerland. Since 2008, he has been with the Department of Electrical Engineering, Chonbuk National University, Jeonju, South Korea, where he is currently an Associate Professor. His current research interests include the power conversion systems of high power for renewable energy sources and medium voltage electric drive systems.
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