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10 Gbps Transimpedance Amplifier-Receiver for Optical Interconnects
10 Gbps Transimpedance Amplifier-Receiver for Optical Interconnects
Journal of the Optical Society of Korea. 2013. Feb, 17(1): 44-49
Copyright ©2013, Optical Society of Korea
  • Received : September 09, 2012
  • Accepted : December 12, 2012
  • Published : February 25, 2013
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About the Authors
Jamshid Sangirov
jamshid@kaist.ac.kr
Ikechi Augustine Ukaegbu
Tae-Woo Lee
Mu Hee Cho
Hyo-Hoon Park
Abstract
A transimpedance amplifier (TIA)-optical receiver (Rx) using two intersecting active feedback system with regulated-cascode (RGC) input stage has been designed and implemented for optical interconnects. The optical TIA-Rx chip is designed in a 0.13 μm CMOS technology and works up to 10 Gbps data rate. The TIA-Rx chip core occupies an area of 0.051 mm 2 with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20 pA/√Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 GHzΩ /mW.
Keywords
I. INTRODUCTION
In an optical Rx design, the TIA plays the role of a front-end amplifier for amplifying the weak current signals generated from the photodiode (PD) and converting to voltage signal which would be fed to a subsequent block (limiting amplifier or clock and data recovery circuit). The conventional Rx consists of a TIA preamplifier block, limiting amplifier, and the output buffer. There are several works that have reported on 10 Gbps front-end optical receiver designs [1 - 7] . Bandwidth enhancement techniques using inductive peaking has been proposed [1 - 5] for designing high data rate operation of an optical Rx. However, an excessive size of the inductor makes the chip big and expensive. An inductorless TIA has been designed in [6] , where several shunt feedback TIAs connected in parallel were suggested for bandwidth improvement and chip size reduction. This design method has high power consumption due to the several TIAs deployed. The bandwidth enhancement technique for transimpedance amplifiers using capacitive peaking which has been realized using a single capacitor is a good candidate for small-area TIA design [7] . However, the negative capacitance is directly loading to the input of the TIA, therefore introducing high peaking at the transient response of TIA. We therefore propose an inductorless TIA that functions as an optical Rx, which does not require a limiting amplifier stage, thereby reducing total chip size. In our proposed design, the RGC input stage has been utilized with post amplifying active feedback amplifiers to lower the input capacitance of PD and for bandwidth improvement. A high gain-bandwidth product per DC power figure of merit of 408 GHzΩ/mW is achieved with the combination of passive (resistive) and active (NMOS transistor) feedback components. Thus, the absence of inductors in the proposed TIA-Rx results in a power efficient chip with small size. In this work, a 10 Gbps TIA-Rx chip that operates up to 10 Gbps have been designed and fabricated in a 0.13 μm CMOS technology.
II. THE TIA-Rx CIRCUIT DESIGN
The schematic of the TIA-Rx chip is shown in Fig. 1 . The RGC input stage reduces the input impedance by the amount of its own voltage gain, which prevents the input pole from dominating the TIA-Rx bandwidth and reduces the capacitive effect of the PD [8] . Thus, the RGC circuit can be used effectively for CMOS integration as a front-end amplifier.
Lager Image
Schematic of TIA-Rx circuit.
The input impedance of the RGC stage is given as [4] :
Lager Image
where 1 + gm 1 R 1 is the gain of the local feedback and with the product of the common gate stage, it behaves as a large transconductor Gm = gm 2 (1+ gm 1 R 1 ). Thus, the size of local feedback decides the amount of reduction of input parasitic capacitance effect for bandwidth determination. The RGC peaking frequency in frequency response is given as:
Lager Image
At low frequency, the open-loop transimpedance gain of the TIA-Rx is given as:
Lager Image
The TIA-Rx is made up of four stages, namely, an input stage (which consists of the RGC); an inter-stage; a gain stage with intercepting active feedbacks; and an output stage (which acts as the buffer). The RGC block is important in the TIA-Rx circuit as it affects the input noise and the stability of the whole TIA-Rx circuit while delivering the input photo current to the output with increased gain. Thus, the design parameters have to be carefully chosen not to interfere with the input impedance for high frequency operation. The transfer function of the RGC input stage is given as:
Lager Image
M 3 and M 4 make up the transconductance inter-stage stage of the TIA-Rx, where high frequency operation should be maintained for delivering the converted input current to output voltage for the gain stage. The impedance at the drain of M 2 and M 4 are reduced by factor of 1+ A by RF shunt feedback and correspondingly, the poles are sped up by the factor, 1+ A . A common-drain (CD) is placed at the drain of M 2 because the capacitive effect on bandwidth is small [8] . The inter-stage isolates the RGC input stage from the gain stage and also adjusts the input dc level from the RGC stage. The transfer function of the inter-stage is given as:
Lager Image
where R′F is represented by
Lager Image
To increase the overall transconductance of the TIA-Rx to higher output voltage levels, several stages of commonsource (CS) amplifying stages have been utilized. However, placing a gain stage consisting of several CS amplifying stages may reduce the bandwidth. Hence, adding the active feedback stages, Af 1 and Af 2 , compensate by peaking at high frequencies [9] . The negative active feedback utilized in the gain stage is different from the conventional resistive feedback which avoids the direct resistive load to the preceding transimpedance stage. Moreover, active devices suffer less process variation than passive devices during fabrication. The high-frequency peaking occurs at Af 1 and Af 2 active feedback. The peaking of the first and second active feedbacks is given as:
Lager Image
Lager Image
The negative active feedback increases the 3-dB bandwidth and thus, the active feedback effects of Af 1 and Af 2 has been included in the transfer function of the gain stage and the equation is given as:
Lager Image
where G 5 ( s )= G 6 ( s )= G 7 ( s )= GmR /(1+ sRC ), and G f 1 ( s )= G f 2 ( s )= G f( s )= Gm f R /(1+ sRC ). By combining equations (4), (5), (6), and (9),we can write the transfer function of the TIA-Rx as:
Lager Image
The transimpedance gain of the TIA-Rx can be obtained from equation (10) and is written as follows:
Lager Image
The 3-dB bandwidth of the TIA-Rx is affected by dominant poles at amplifying stages of gm 3 , gm 5 and gm 6 . Thus, the dominant poles can be described by the frequency response of gain stages with transconductance of the dominant poles given by equations (12) to (16):
Lager Image
Lager Image
Lager Image
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The 3-dB response of the TIA-Rx can be obtained with τeq from f3dB = 1/(2 πτeq ). Writing in terms of three dominant poles of TIA-Rx, the three major poles would be P 1 = τ 1 ; P 2 = τ 5 ; P 3 = τ 6 .
Figure 2 shows the transimpedance gain of the TIA and the bandwidth extension effect of the active feedbacks Af1 and Af 2 . The dotted line is the simulation result of TIA-Rx without active feedback which has a gain of 68 dBΩ at a 3-dB bandwidth of 2.71 Ghz; the dashed line is the result of TIA-Rx with active feedback, Af 1 , with 3-dB bandwidth of 5.01 GHz; and the solid line is the result of TIA-Rx gain with two feedbacks Af 1 and Af 2 , where the transimpedance gain reduced to 60 dBΩ with a 3-dB bandwidth of 7.36 GHz. The 3-dB bandwidth has been improved from a value of 2.71 GHz to 7.36 GHz after adding two active feedbacks.
The input-referred noise of TIA-Rx can be described as follows:
Lager Image
where k Boltzmann’s constant; T is the absolute temperature; Γ is the channel-noise factor of MOSFET; Cin is the input parasitic capacitance which includes the photodiode capacitance; bond-pad parasitic capacitance, and electrostatic discharge capacitances ( Cin = Cpd + CESD + Cpad ). From eq. (17), it can be observed that low frequency noise is dominated by resistor thermal noises and high frequency dominant noise occurs due to input parasitic capacitances. The dominant high-frequency noise is divided by (1+ gm 1 R 1 ) gain of the local feedback, and hence, the size of local feedback has been increased to reduce total equivalent noises. To reduce the overall noise current of TIA-Rx the resistors, Rs 1 , RF , R 2 , and gm 1 with gm 4 transistors sizes should be increased
Lager Image
The simulated result of TIA-Rx with and without active feedback.
Lager Image
The simulated input-referred noise of TIA-Rx.
to be as large as possible, and to reduce the parasitic capacitance the transistors, M 1 , M 2 and M 3 sizes should be reduced. However, increasing RF will result in bandwidth degradation from eq. (16) and increasing the gm 1 and gm 4 will result in W/L ratio and bias current of transistor M 1 and M 4 . Hence, in our proposed TIA-Rx design we have optimized the values of Rs 1 and M 1 to reduce the bias current by increasing the resistor value for the increase of W/L ratio of a transistor and achieved compensated input-referred noise. The values of RF , M 3 and M 4 have been carefully chosen to improve the frequency operation of the TIA-Rx while keeping the noise current minimum. Fig. 3 shows the simulated input-referred noise of TIA-Rx. The simulated input-referred noise of TIA-Rx is equal to 18 pA/√Hz at 3-dB bandwidth.
III. EXPERIMENTAL RESULTS
The proposed TIA-Rx circuit has been designed and fabricated in a 0.13 μm CMOS technology. The fabricated TIA-Rx chip core occupies an area of 0.051 mm 2 . The TIA-Rx chip is mounted on wire-bounded chip-on-board (COB) for frequency response, eye-diagram and integrated output noise measurements. The photograph of TIA-Rx chip is shown in Fig. 4 .
Figure 5 shows the integrated output noise measured from the output of the TIA-Rx chip with no input connected. The standard deviation of 0.52 mV is measured and by subtracting the oscilloscope noise of 0.1 mV, the corrected integrated noise is 0.42 mV.
The frequency response is measured using an Agilent 8703B lightwave component analyzer. The measured 3-dB bandwidth of the TIA-Rx chip is 6.9 GHz and a transimpedance gain of 60 dBΩ, as shown in Fig. 6 , which were obtained with 1 kΩ shunt passive feedback, RF , and 0.24 pF photodiode capacitance, Cpd . Fig. 7 shows the input-referred noise, where 3-dB bandwidth input-referred noise equals to 20 pA/√ Hz. From Fig. 6 and Fig. 7 , the measured results are in agreement with the simulated results. However, the slight
Lager Image
Die photograph of the fabricated TIA-Rx chip.
Lager Image
Measured integrated output noise of the proposed TIA-Rx.
Lager Image
Transimpedance gain (ZT) of the proposed TIA-Rx chip: the solid and dotted lines show the measured and simulated results, respectively.
Lager Image
The input-referred noise of the proposed TIA-Rx chip: the solid and dotted lines show the measured and simulated results, respectively.
The comparison of the proposed TIA-Rx chip performance with other worksGain bandwidth product per DC power (GBP/PDC), bandwidth (BW).
Lager Image
The comparison of the proposed TIA-Rx chip performance with other works Gain bandwidth product per DC power (GBP/PDC), bandwidth (BW).
Lager Image
The measured eye-diagrams of the TIA-Rx chip with PRBS of 231-1 at 10 Gbps data rate: (a) Iin=20 μA and Vout,pp=20 mV, 20 ps/div, (b) Iin=120 μA and Vout,pp=120 mV, 16.3 ps/div and (c) Iin=850 μA and Vout,pp=750 mV, 23.4 ps/div.
discrepancy between the measured and simulated results may have been attributed by process variation during the fabrication process.
Table 1 shows a comparison of the TIA-Rx performance with other works. From Table 1 , it can be seen that the size of the proposed TIA-Rx is smaller than the other TIA circuits, where passive inductor peaking have been utilized for bandwidth extension. In our proposed TIA-Rx, using active feedback system achieves comparatively high gain-bandwidth product per DC power (GBP/PDC) figure of merit of 408 GHzΩ/mW with reduced chip area.
To evaluate optical TIA-Rx dynamic response, 2 31 -1 pseudorandom binary sequence (PRBS) input signal, generated from Anritsu MP1736 pulse-pattern generator was applied, while the output was measured with an Agilent 8610A oscilloscope. The eye-diagrams of TIA-Rx are shown in Fig. 8 . The applied input current 20 μA, 120 μA and 850 μA results in 20 mV, 120 mV and 750mV TIA-Rx output, respectively. The eye-diagrams of TIA-Rx show rise/fall times with root-mean square (RMS) jitter of 86.7/90ps with 13 ps for Iin = 20μA, 75.1/129ps with 6.91ps for Iin = 120μA and 71.4/118.2ps with 6.76 ps for Iin = 750μA at 10 Gbps. The measured bit error rate (BER) as a function of
Lager Image
The measured BER using 231-1 PRBS input signal as a function of input current at 10 Gbps data rate.
the input current is presented in Fig. 9 . This BER measurement is done at 10 Gbps data rate using 2 31 -1 PRBS input signal, and a BER of less than 10 -12 is achieved with input current of about ~120 μA. The power dissipation of the TIA-Rx is 16.9 mW at 1.3 V.
Besides reducing input impedance of TIA-Rx, the RGC block with local (resistive) feedback increases the input referred noise as well. The addition of post amplifying transconductance stages adds extra noise. The increase in input-referred noise leads to degradation of input sensitivity. As a result, the dynamic characteristics (eye diagram) of the TIA-Rx chip shows better performance with slightly higher input current than the TIA-Rx with lower input current. From the eye-diagrams and BER measurement results are shown in Figs. 8 and Fig. 9 , with increase of an input current, the output voltage of the TIA-Rx increases. Thus, our proposed TIA-Rx design requires higher input current of about ~120μA and above to be able to provide sufficient output signal to the next stages such as De-serializer, PLL, and clock data recovery (CDR) circuitry. Hence, our proposed TIA-Rx can be applied as a front-end optical Rx to convert the input photo current to the output voltage signal in order to feed to the De-serializer, PLL and CDR circuits.
IV. CONCLUSION
A TIA-Rx has been designed and implemented in 0.13 μm CMOS technology for optical interconnect applications operating up to 10 Gbps. The TIA-Rx shows a good eye performance up to 10 Gbps with BER of less than 10 -12 . The TIA-Rx chip core is 0.051 mm 2 with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of the TIA-Rx is 20pA/√Hz with a 3-dB BW of 6.9 GHz. The TIA-Rx chip utilizes two intersecting active feedback systems with RGC input stage and occupies a small chip area with an efficient GBP/PDC figure of merit of 408 GHzΩ/mW. Our proposed TIA-Rx can be applied as a front-end optical Rx to convert the input photo current to output voltage signal, high enough to feed to the next stages such as the De-serializer, PLL, and/or CDR circuits, and it is applicable for chip-to-chip optical interconnects.
Acknowledgements
This work was supported by the IT R&D program ofMKE/KEIT [10039230, Development of bidirectional 40 Gbps optical link module with low power in Green DataCenter for Smart Working Environment] and it was alsosupported by the Center for Integrated Smart Sensorsfunded by the Ministry of Education, Science and Technologyas Global Frontier Project (CISS-2012366054191).
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