This paper proposes a design and control method for a highvoltage direction current modular multilevel converter (HVDCMMC) considering the capacitor voltage ripple of the submodule (SM). The capacitor voltage ripple consists of the line frequency and doublelinefrequency components. The double line frequency component does not fluctuate according to the active power, whereas the linefrequency component is highly influenced by the gridside voltage and current. If the grid voltage drops, a conventional converter increases the current to maintain the active power. A grid voltage drops, current increment, or both occur with a capacitor voltage ripple higher than the limit value. In order to reliably control an MMC within a limit value, the SM capacitor should be designed on the basis of the capacitor voltage ripple. In this paper, the capacitor voltage ripple according to the grid voltage and current are analyzed, and the proposed control method includes a current limitation method considering the capacitor voltage ripple. The proposed design and control method are verified through simulation using PSCAD/EMTDC.
1. Introduction
Highvoltage direct current (HVDC) systems have several advantages: these systems are cheaper than an AC network for longdistance power transmission, do not affect the ac grid for AC/DC power conversion, are able to handle highcapacity power transmission, and are able to connect with other grid systems that have different frequencies. HVDC systems can be classified into current source converterbased HVDC (CSCHVDC) with a thyristor and voltage source converterbased HVDC (VSCHVDC) with an insulatedgate bipolar transistor (IGBT). CSSHVDC systems were used in the majority of systems prior to 2010. However, recent VSCHVDC systems have been actively studying the connection of offshore wind form systems as well as longdistance power transmission. A multilevel converter is widely used to configure VSCHVDC systems
[1
,
2]
.
Multilevel converters are classified into diodeclamped multilevel converters (DCMCs), flyingcapacitor multilevel converters (FCMCs), cascaded Hbridge converters (CHBCs), and modular multilevel converters (MMCs). MMCs have been widely adopted in VSCHVDC systems.
Fig. 1
shows the structure of an MMC consisting of six arms. Each arm is composed of an inductor and a series of connected halfbridge submodules (SMs). HVDCMMC systems require several design techniques. (1) System parameter design includes inductance and capacitance design and switching device current capacity design. (2) System control design includes power (DClink voltage) control, ACside current control, circulating current control, and SM voltage balancing
[2

6]
.
Basic structure of MMC.
A design method for the SM capacitance of the MMC was introduced in
[7]
. This design method calculated the difference in input energy according to the amplitude of the grid voltage and the active power. The SM capacitance is designed by the input energy and the SM capacitor voltage ripple on the basis of the limit value. The SM capacitor voltage ripple has linefrequency and doublelinefrequency components. However, this design method did not separate linefrequency and doublelinefrequency components; the capacitor voltage ripple was only calculated using integrated components.
Reference
[8]
introduced the design method of the arm inductors. An MMC possesses a voltage difference between the dc link and each arm with SMs, which leads to a problem in the circulating current in each arm. Therefore, reference
[8]
proposed a design method for the arm inductors considering the amplitude of the circulating current.
Reference
[9]
proposed a control method for an MMC under unbalanced voltage conditions. This control method proposed a dualvector current control (DVCC) for the acside current controller in order to eliminate circulating currents and the dclink voltage ripple. However, this control method has the disadvantage of the inclusion of a doublelinefrequency ripple in acside active power by controlling acside negativesequence currents to zero under unbalanced voltage conditions, and increasing the SM capacitor voltage ripple because it did not consider the capacitor voltage ripple.
Reference
[10]
proposed a control method for the circulating current and inner unbalanced current for an MMC under unbalanced voltage conditions. This control method consisted of DVCC for the acside current controller and had an advantage in that the active power did not fluctuate under the unbalanced voltage conditions. This method can also simultaneously control with positive, negative, and zerosequence circulating currents. However, this method has the disadvantage of increasing the SM capacitor voltage ripple because of injection of the acside negativesequence current.
A conventional design method of the SM capacitor was created by considering only the steady state, and a control method was designed by not considering the SM capacitor voltage ripple. Therefore, this paper proposes a design and control method for the SM capacitor for HVDCMMCs considering the SM capacitor voltage ripple. For the design of the SM capacitor, it calculates the energy according to the acside rated voltage and current. The input energy has DC, linefrequency, and doublelinefrequency components. The input energy is calculated. Among these, the input energy is calculated, the injected energy into the SM capacitor is extracted, and the SM capacitance is designed within the limit value of the capacitor voltage ripple according to the difference in the SM voltage by the energy variation.
The SM capacitor voltage ripple has linefrequency and doublelinefrequency components. The doublelinefrequency component corresponds with the amount of active power. Even if the linefrequency component is equal to the amount of active power, however, the linefrequency component has a different value because of the amplitude of the acside voltage and current. When the converter is maintained at a constant value, the active power is less than the undervoltage condition, and consequently, the doublelinefrequency component is equal to the amplitude of the normal voltage condition, but the linefrequency component exceeds the capacitor voltage limit value. An SM capacitor voltage ripple higher than the rated value places stress on the switching elements and the SM capacitor, and a large overload can lead to destruction of the switching elements and SM capacitor. Accordingly, the HVDCMMC must control the system while considering the SM capacitor voltage ripple in undervoltage conditions. Therefore, this paper configures the maximum current limit value considering the grid voltage and the maximum voltage limit value. The converter restricts SM capacitor voltage ripple to be less than the acside current limit in the undervoltage conditions. The proposed methods are simulated using PSCAD/EMTDC.
2. Basic Structure of the MMC
Fig. 2
shows a singlephase equivalent circuit of a gridconnected threephase MMC.
V_{k}
is the grid voltage.
i_{pk}
and ink are the upper and lower arm currents, respectively.
i_{diffk}
is the inner unbalanced current.
e_{k}
is the converter output voltage.
e_{pk}
and
e_{nk}
(k = a, b, c) are the upper and lower arm voltages, respectively, where the subscripts p and n denote the upper and lower arms, respectively. According to
Fig. 2
and
[11]
, the corresponding acside voltage equation can be expressed as:
where
V_{dc}
is the dc bus voltage.
L
and
R
are the arm inductance and equivalent arm resistance, respectively.
Singlephase equivalent circuit of the threephase MMC.
As shown in
Fig. 2
, the voltages of the upper arm and lower arm are expressed as:
The currents of the upper arm and lower arm are expressed in (6) and (7), respectively, and the inner unbalanced current is expressed in (8).
where
i_{zk}
is the circulating current.
3. SM Capacitor Parameter Design
From (4) and (5), R can be neglected because it is very small, and L can be neglected because it is designed by the amplitude of the SM capacitor and the circulating current and is smaller than the grid voltage. Eqs. (4) and (5) may be simplified to (9) and (10), respectively.
where
V_{m}
is the peak value of gridside phase voltage.
The current equations of the arm (6)(8) include the circulating current. However, the circulating current is neglected for simplification. Eqs. (6)(8) may be simplified to (11) and (12).
where
I_{m}
is the peak value of the phase current.
The SM capacitor voltage ripple is determined by the input energy into the SM capacitor according to the amount of acside power. Instantaneous power of the arm can be expressed by multiplication of the voltage and current as follows:
The instantaneous power has dc and ac components. Among these components, only the ac component is stored in the arm
[9]
; hence, only the ac component in (13) is represented as (14). In (14), α is zero because in the MMC, assuming a unit power factor control, the gridside voltage and current have identical phase. Therefore, (14) may be rearranged to (15). In (15), the first term is the linefrequency component, and second term is the doublelinefrequency component. The stored energy in the arm, which is calculated by (15), may be expressed as (16), and the peak value may be expressed as (17).
The stored energy in the SM capacitor is expressed in (18), and difference in the SM capacitor energy is equal to the stored energy in the arm. Eq. (18) can replace the difference in the capacitor energy with the difference in the SM capacitor voltage; thereby, (18) can be expressed as (19):
where
C_{Arm}
is the SM capacitance,
N
is the number of SMs,
V_{SM_total}
is the sum of the SM capacitor voltage,
V_{total}
is the sum of the SM capacitor voltage per arm at steady state, which is equal to the dc bus voltage, and
ΔV_{total}
is the difference in the total SM capacitor voltage.
The difference in the arm capacitor voltage can be expressed as (20) from (19), and the capacitance of the SM capacitor can be also expressed as (21) from (19). Therefore, the SM capacitance is calculated by substituting the main circuit parameters (standard design specification) of the MMC in (21). The main circuit parameters and operating condition are listed in
Table 1
.
Main circuit parameters
Fig. 3
shows the simulation results of the difference in the arm capacitor voltage according to the SM capacitance.
Table 2
shows the result of both the calculated difference in the arm capacitor voltage and the simulated difference in the arm capacitor voltage. In order to restrict the arm voltage ripple to less than 1000 V under the rated power condition, a value of more than 0.0015 F must be chosen for the SM capacitor. Therefore, a value of 0.002 F for the SM capacitance considering the voltage ripple margin is selected.
Simulation results of the arm capacitor voltage ripple varying the SM capacitance.
Arm capacitor voltage ripple varying the SM capacitance.
Arm capacitor voltage ripple varying the SM capacitance.
Fig. 4
shows the result of a fast Fourier transform (FFT) of the arm voltage when the SM capacitance is 0.002 F. The amplitude of the calculated capacitor voltage ripples and the results of the FFT in the simulation of the ripple components are shown in
Table 3
. There are similar results which compare the calculated capacitor voltage ripple and the result of the FFT in the simulation. Therefore, not only the total arm capacitor voltage ripple but also the linefrequency and doublelinefrequency components can be calculated.
FFT analysis of the arm capacitor voltage ripple.
Arm capacitor voltage ripple component of line frequency and doubleline frequency.
Arm capacitor voltage ripple component of line frequency and doubleline frequency.
4. Current Limit Method
 4.1 ACside current reference
If the grid voltage is at steady state, the gridside voltage and current have only positive sequences. The acside active power and reactive power can be expressed as (22) and (23).
where
P_{AC}
is the acside active power,
Q_{AC}
is the acside reactive power, superscript
p
is the positive sequence component, and subscripts
d
and
q
are the rotational reference frame d and qaxes, respectively.
If the positivesequence daxis voltage is determined to be zero through the phaselocked loop (PLL), the acside current reference according to the active power and reactive power reference can be expressed as (24) and (25).
 4.2 Current limit method considering current capacity of switching elements
In the case of the twolevel converter, the injected current into the switching device is equal to the acside current. However, in the MMC, the current is injected into the switching elements, not only the ac component but also the dc component into the switching device, because this current is equal to the arm current. Hence, we have to restrict the current considering the dc component. The arm current of the MMC is expressed as (6) to (8), and if the circulating current is controlled to zero, the acside current can be expressed as (26) and (27).
In (26) and (27), if the arm current is restricted to the current capacity of the switching device, the allowed acside maximum current can be expressed as (28).
 4.3 Current limit method considering SM capacitor voltage ripple
The SM capacitor voltage ripple in (14) to (20) is determined according to the amplitude of the gridside voltage, current, and dclink current. In (15), the doublelinefrequency component is multiplied by the gridside voltage and current. If the active power does not fluctuate, the doublelinefrequency component has constant amplitude. However, the fundamental frequency component fluctuates depending on the gridside voltage and current, even though the active power does not fluctuate. Hence, the control method considering the SM capacitor voltage ripple under the undervoltage conditions is needed because the SM capacitor voltage ripple increases in the undervoltage conditions.
The SM capacitor voltage ripple is determined by the input energy. Therefore, it has to restrict the injected energy into the SM capacitor within the acceptable range to restrict the ripple of the SM capacitor voltage. The injected energy into the SM capacitor consists of the function of the gridside voltage, current, and dclink current as in (17). The gridside voltage is determined by external factors, and the dclink current is determined by the gridside voltage and current. Hence, the gridside current must be restricted to limit the ripple of the SM capacitor voltage because the controllable variable is the gridside current. Because (17) includes the dclink current component, this is converted to the gridside current component and may be simplified. If no regard is given to the loss of the MMC, then the active power of the acside and dcside of the MMC may be expressed as (29).
where subscripts
d
and
q
denote the
d
 and
q
axis components in the rotational reference frame, respectively.
If the positivesequence daxis voltage is determined to be zero through the PLL, the amplitude of the qaxis current that is equal to the peak value of the phase current may be defined as in (30).
Hence, the peak value of the energy is derived by a function of the gridside voltage, current, and the dclink voltage by substituting (30) into (17). The peak of the phase current may be expressed as (32) with respect to the gridside current in (31). Therefore, when the acside current reference is restricted to the current limitation value, the SM capacitor voltage ripple can be restricted within the limit value.
Fig. 5
shows the rated current of the switching elements and the current limitation method considering the arm capacitor voltage ripple. The d and qaxis current references are determined by the initial values of the active power and reactive power, respectively, and the control method consists of part of the current limit considering the restriction of the current reference and the arm capacitor voltage ripple.
Proposed current limitation method scheme considering the current capacity and the arm capacitor voltage ripple.
5. Simulation Results
Fig. 6
shows the system structure of the simulations using PSCAD/EMTDC. The parameters used in the simulation are listed in
Table 1
. The PWM method and balancing algorithm of the SM capacitor voltage are used in the modified PSCPWM method in
[11]
.
System structure of simulations.
Fig. 7
shows the simulation results, which show the rated current of the switching elements and the ripple of the arm capacitor voltage considering the current limitation method. The simulation conditions are as follows:

(1)Mode 1(0.3–0.4 s): zero power control under the rated voltage condition.

(2)Mode 2(0.4–0.7 s): active power is 4MW load, and reactive power is 0MVA load under the rated voltage condition.

(3)Mode 3(0.7–0.9 s): reactive power is 0 MVA, and active power is limited by current limit considering the voltage ripple of the arm capacitor under the lowvoltage condition in which the voltage is reduced by 50%.
Simulation results of the proposed control method under the lowvoltage condition: (a) gridside voltage; (b) gridside current; (c) i_{dc}/3 component; (d) current limit value considering the current capacity of the switching element, and (e) current limit value considering the arm capacitor voltage ripple.
Fig. 7(a)
and
(b)
shows the gridside voltage and current. The gridside current is increased to maintain the active power at 0.7 s in undervoltage conditions. However, in order to restrict the switching element ripple and arm capacitor voltage, the gridside current is confirmed to have a constant value by the current limit value.
Fig. 7(c)
shows the
i_{dc}/3
component. It can be confirmed that the dclink current is reduced by the current limit condition to restrict the active power at 0.7 s.
Fig. 7(d)
shows the limited current value considering the rated current of the switching elements. According to the increase in the dclink current in the mode2 section to increase the active power, it can be confirmed that the peak of the acside current reference is reduced by the current limit condition of (23). In the case of the mode3 section to the gridside undervoltage conditions, the active power is reduced by the current limitation condition considering the arm capacitor voltage ripple. It can be confirmed that the current limit value is increased by the reduced amplitude of dclink current.
Fig. 7(e)
shows the current limit value considering the arm capacitor voltage ripple. The current limit value is constant under the rated voltage condition. However, in case of the mode3 section for the gridside undervoltage conditions, it can be confirmed that the current limit value is reduced in order to restrict the ripple of the arm capacitor voltage.
Fig. 8
shows results of simulation according to the current limit control method.
Fig. 8(A)
shows the results of the simulation of the conventional control method without the current limit control method,
Fig. 8(B)
shows the results of the simulation of the current limit control method considering the current capacity of the switching device, and
Fig. 8(C)
shows the results of the simulation of the current limit control method considering the current capacity of the switching device and the arm capacitor voltage ripple. At first, the active power reference is 4 MV, and reactive power reference is 0 MVA. The acside voltage in the undervoltage condition is reduced from 1.0 to 0.5 pu for 0.05 s at 0.7 s.
Fig. 8(a)
,
(b)
, and
(c)
show the acside voltage, current, and qaxis current. As shown in
Fig. 8(A)
, it can be confirmed that the acside current is increased to maintain a 4MW active power during the undervoltage conditions. As shown in
Fig. 8(B)
, the acside current is increased by the undervoltage conditions, but this acside current is less than that in
Fig. 8(A)
because the controlled current is restricted within the current capacity range of the switching elements. As shown in
Fig. 8(C)
, the acside current is increased by the undervoltage conditions, but when compared with other methods, this acside current is less than the other current because of the current limit condition to restrict the arm capacitor voltage ripple.
Fig. 8(d)
shows the flowing arm current in the switching elements and the rated current of system. As shown in Fig. 8(A), the arm current exceeds the current capacity of the switching elements because it does not contain the current limit method. As shown in
Fig. 8(B)
, however, the flowing arm current in the switching element is controlled to the same amplitude of the current capacity of the switching elements because this arm current has been restricted to the current limit value of the current capacity of the switching elements. As shown in
Fig. 8(C)
, the arm current is controlled to be less than the current capacity of the switching elements because this arm current is restricted to be within the arm capacitor voltage ripple that is less than the current capacity of the switching elements.
Fig. 8(e)
shows the acside active power: As shown in
Fig. 8(A)
, the acside active power is controlled to 4 MW because there is no current limit method. As shown in
Fig. 8(B)
, however, the active power is reduced because this arm current is restricted to be less than the current limit value considering the current capacity of the switching elements. As shown in
Fig. 8(C)
, the active power is similarly reduced because this arm current is restricted to less than the current limit values considering both the current capacity of the switching elements and the arm capacitor voltage ripple.
Fig. 8(f)
and
(g)
shows the arm capacitor voltage and the upper arm SM voltage. As shown in
Fig. 8(A)
, the arm capacitor voltage exceeds the limit value of 1000 V because it does not contain the current limit method. As shown in
Fig. 8(B)
, the arm current is restricted to be within the current capacity of the switching elements, but the arm capacitor voltage ripple still exceeds the limit value of 1000 V. As shown in
Fig. 8(C)
, the arm capacitor voltage ripple does not exceed the limit value of 1000 V. Therefore, in order to restrict the arm capacitor voltage ripple and the acside current to within the limit values, it can be confirmed that the current limit method must consider not only the current capacity of switching elements but also the arm capacitor voltage ripple.
Simulation results of various control methods under the lowvoltage condition: (a) gridside voltage; (b) gridside current; (c) acside qaxis current; (d) arm current; (e) acside active power; (f) SM capacitor voltage ripple limit value; (g) upper arm SM capacitor voltage; (h) lower arm SM capacitor voltage. (A) Conventional method [9], (B) conventional method [10], and (C) proposed method.
Fig. 9
shows the result of Fourier transform of the arm capacitor voltage in
Fig. 8
. Table IV shows the calculated respective components using (20) and the results of the simulation. The doublelinefrequency component is proportional to the product of the acside voltage and current in (20). As shown in
Fig. 9(A)
, in order to maintain the active power, the amplitude of the acside current was increased proportionally to the reduction ratio, and thereby, the amplitude of the doublelinefrequency component is equal to that in
Table 3
, whereas the fundamental frequency component was increased three times compared with the value in
Table 3
. As shown in
Fig. 9(B)
, the total voltage ripple is reduced by the current limit method considering the current capacity of the switching elements, but the voltage ripple exceeds the tolerance. As shown in
Fig. 9(C)
, however, the total voltage ripple is restricted to less than 1000 V by the current limit method considering both the current capacity of the switching elements and the arm capacitor voltage ripple. Therefore, the proposed control method can control the arm capacitor voltage ripple within the limit value in undervoltage conditions, and when designing the arm capacitor of the MMC, this method has advantages for the estimated arm capacitor voltage ripple that can be considered in a design.
FFT analysis of the arm capacitor voltage ripple under the lowvoltage condition.
Arm Capacitor Voltage Ripple Component of Various Control Methods Under the Lowvoltage Condition.
Arm Capacitor Voltage Ripple Component of Various Control Methods Under the Lowvoltage Condition.
5. Conclusion
In this paper, a design method for the SM capacitance and a control method considering the SM capacitance and voltage ripple are proposed for an MMC. In order to design the SM capacitance, the arm capacitor voltage ripple is calculated and analyzed according to the acside voltage and current. In order to restrict the arm capacitor voltage ripple to within the limit value, we have proposed a current limit method considering the arm capacitor voltage ripple. The proposed control method can stably control an HVDCMMC in undervoltage conditions. The arm capacitor voltage ripple was restricted to be within a constant value, which was verified through simulation, and was compared with the control method considering the current capacity of the switching element.
Acknowledgements
This work was supported by BK21PLUS, Creative Human Resource Development Program for IT Convergence.
BIO
JinSu Gwon He received the B.S. and M.S. degrees in Information and Communication Engineering from Kyungnam University, Masan, Korea, in 2009 and 2011, respectively, and is currently pursuing the Ph.D. degree in electrical engineering at Pusan National University, Busan, Korea. From 2009 to 2015, he was a Researcher in KERI, Changwon, Korea. Since 2015, he has been with Hyundai Elevator, Icheon, Korea. His present interests include control of HVDC, multilevel converters, renewable energy, Motor Drive and control.
JungWoo Park He received the B.S. and M.S. degrees in electronic engineering from Chungnam National University, Chungnam, Korea, in 1986 and 1988, respectively, and the Ph.D. degree in electrical engineering from Kyungpook National University, Kyungpook, Korea. Since 1998, he has been a Principal Researcher with KERI, Changwon, Korea. His present interests include control of HVDC, multilevel converters, wind energy generation, and renewable energy.
DaeWook Kang He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Hanyang University, Seoul, Korea, in 1998, 2000, and 2004, respectively. Since 2004, he has been a Senior Researcher with KERI, Changwon, Korea. His interests include control of HVDC, multilevel converters, renewable energy, and the application of power electronics to power systems.
Sungshin Kim He received the B.S. and M.S degrees in electrical engineering from Yonsei University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, in 1996. He is currently a Professor in the School of Electrical Engineering, Pusan National University, Busan, Korea. His research interests include intelligent control, intelligent robot, hierarchical learning structures, and fault diagnosis and prognosis.
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