This paper focuses on the engineering tradeoffs in designing capacitor voltage balancing schemes for modular multilevel converters (MMC) HVDC: regulation performance and switching loss. MMC is driven by the on/off switch operation of numerous submodules and the key design concern is balancing submodule capacitor voltages minimizing switching transition among submodules because it represents the voltage regulation performance and system loss. This paper first introduces the stateoftheart MMCHVDC submodule capacitor voltage balancing methods reported in the literatures and discusses the tradeoffs in designing these methods for HVDC application. This paper further proposes a submodule capacitor balancing scheme exploiting a control signal to flexibly interchange between the onstate and the offstate submodules. The proposed scheme enables desired performancebased voltage regulation and avoids unnecessary switching transitions among submodules, consequently reducing the switching loss. The flexibility and controllability particularly fit in highlevel MMC HVDC applications where the aforementioned design tradeoffs become more crucial. Simulation studies for MMC HVDC are performed to demonstrate the validity and effectiveness of the proposed capacitor voltage balancing algorithm.
1. Introduction
This paper investigates a crucial engineering tradeoff in designing capacitor voltage balancing schemes for a modular multilevel converter (MMC) HVDC: voltage regulation performance and switching loss. The MMC has numerous stacks of identical converters called submodules
[1

5]
. For the half bridge configuration, a submodule has two switching devices implemented by antiparallel connections of a fully controllable insulatedgate bipolar transistor (IGBT) and capacitor to generate the output voltage
[6]
(See
Fig. 1(b)
). As the level of the MMC or the number of submodules increases to enable higher power transmission, the capacitor voltage balancing task becomes the primary technical challenge because the balancing scheme may adversely impact on system loss, device ratings as well as control performance, if not properly designed
[7]
. As conceptually illustrated in
Fig. 1(a)
, there is a tradeoff between voltage regulation performance and loss. The higher switching frequency generates the lower voltage ripple (∆
V
) leading to better capacitor voltage regulation for a given capacitance notwithstanding the higher switching loss. Large capacitance should allow for small voltage ripple and reduced loss due to reduced switching needs among submodules for the purpose of voltage balancing. It is worth noting that an ideal point in
Fig. 1(a)
provides the perfect voltage regulation and minimum loss comprising inherent conduction loss dominantly. However, the ideal point is prohibitively uneconomical for the high voltage applications because the ideal point can be achieved in extremely large submodule capacitance. The tradeoff between voltage regulation and loss is balanced on the dotted line in practice. Ranking and switching all submodules by their capacitor voltages, often named ‘Full Sorting’ at every switching instant should provide the highest voltage regulation for the designed number of submodules and capacitance at the cost of highest switching loss. Thus, an operating point should be determined in technically and economically feasible operation range.
(a) Engineering Tradeoff in Designing MMC System. (b) MMC Topology
Because the capacitor voltage balancing should be the most basic yet critical functionality of the MMC, various balancing techniques of the capacitor voltage have been discussed in
[1

18]
. Reference
[1]
deals with two types of pulse width modulated MMC (PWMMMC), focusing on their circuit configurations and voltage balancing control. Combining both averaging and balancing controls enables the PWMMMC to achieve voltage balancing and the results are verified by simulation and experiment. In
[2]
, three capacitor voltage balancing strategies are proposed and investigated: 1) a slowrate balancing strategy based on the conventional sorting method; 2) a hybrid balancing strategy that combines a predictive method with the conventional sorting method; and 3) a fundamental frequency balancing strategy. A computationally efficient voltage balancing algorithm without arm current measurements has been proposed
[3]
. The method reduces the number of the sensors and decreases the costs. A reduced switching frequency voltage balancing algorithm is developed for MMC, and a circulating currentsuppressing controller is proposed for the threephase MMC in
[6]
. This voltage balancing algorithm reduces the average device switching frequency and distributes the energy equally among the submodule capacitors. The combination of Nearest Level Modulation (NLM) and optimized capacitor voltage balancing control using a maintaining factor reduces the switching frequency as well as the switching losses of semiconductors in
[7]
. Closed loop control for the submodule voltage balancing is introduced with Carrier Phase Shifted Pulse Width Modulation (CPSPWM) in
[8]
and
[9]
. The submodule capacitor voltage balancing with phase disposition PWM (PDPWM) for MMC is used in
[10

13]
. The submodule capacitor voltages within each arm are measured and sorted, and the number of submodules to be switched on/off is determined. These methods have to be executed at the equivalent switching frequency of one arm, posing a heavy computational burden as the number of submodules becomes increasing to a real high voltage system. The balancing methods in
[14

16]
are based on a sorting method and individual measurement of submodule capacitor voltages, selecting the process based on the direction of the arm current for charging/discharging the selected submodule. It is obvious, however that the heavy computational intensity may hamper their applications to high voltage (or level) systems. It is also interesting to note methods of using extra switching devices and capacitors for the selfbalancing of voltages among modules in
[17]
and the prediction of each capacitor voltage as a function of the arm current and the states of the submodule switches
[18]
. A reduced the switching frequency based on the full sorting are proposed
[6
,
7]
. The methods help reduce the system loss as illustrated in
Fig. 1(a)
while possibly compromising the voltage regulation.
The voltage balancing performance, however, has been investigated and validated for MMC with a small number of levels using high switching frequency modulation schemes. Higher switching frequency allows for better regulation at the cost of higher loss, which becomes the critical constraint for a high voltage application requiring a large number of levels. Therefore, a modulation method should be designed to generate a waveform with a large number of levels with minimal switching frequency that still guarantees the desired balancing performance. This research develops an effective balancing scheme based on the Group Sorting where submodules are grouped and sorted by prior switching states (on or off)
[19]
with supplementary adhoc switchings. These ‘adhoc’ switchings are commanded to interchange the highest voltage capacitor with the lowest voltage capacitor based on the current direction in order to maintain the desired voltage regulation performance. The low switching frequency modulation such as NLM is set as a basis to minimize system loss and it changes the on/off state of submodules based on the current direction that overrides the charge and discharge condition of the submodule to keep the desired voltage regulation. As the qualifier, adhoc implies, the method can adjust the switching frequency and should bring significant benefits of system controllability and flexibility to comply with dynamically changing grid condition. The paper comprehensively addresses the design tradeoffs encountered in designing the highlevel MMC with desired low switching frequency modulation, and further presents the advantages of the proposed voltage balancing method with numerous simulation studies in terms of total harmonic distortion (THD), switching frequency and submodule voltage waveforms. Understanding of these tradeoffs should be highly beneficial for system planners.
This paper is organized as follows: Section 2 presents theoretical background on the design tradeoff between the desired voltage regulation and switching loss. Section 3 describes balancing schemes based on the namely, Full Sorting, Advanced Full Sorting, and Group Sorting methods for MMC in respect to the design tradeoff followed by an effective capacitor voltage balancing control method proposed in Section 4. Section 5 demonstrates the validity and effectiveness of the proposed method through simulation studies for MMC, in particular for HVDC based on PSCAD/EMTDC. Finally, conclusions are provided in Section 6.
2. Design Tradeoff between the Voltage Regulation and Switching Loss
This section briefly provides a theoretical overview on the switching frequency and its impacts on the converter loss and voltage regulation performance, i.e. voltage ripple.
Semiconductor switching devices such as MOSFETs, and IGBTs inherently dissipate power during the switchings.
Fig. 2
illustrates the switching characteristics of the generic switching device and the switching loss due to voltage and current present simultaneously during the turnon crossover interval
t
_{c(on)}
, where
and
t
_{c(off)}
, where
The energy dissipated in the switch during this turnon and off transition can be approximated from
Fig. 2(c)
as
where any energy dissipation during the turnon and turnoff delay interval
t
_{c(on)}
and
t
_{c(off)}
are ignored since they are much smaller than
W
_{c(on)}
and
W
_{c(off)}
. It should also be noted that there are
f_{s}
such turnon and turnoff transitions per second. Hence, the average switching power loss
P_{s}
in the switch due to these transitions can be approximated from (3) and (4) as
This fundamental relationship between the loss and the switching frequency surely indicates that the average switching loss can be controlled by the switching frequency
[20]
.
Genericswitch switching characteristics: (a) switch waveforms; (b) voltage and current waveforms according to switch; (c) instantaneous switch power loss (adapted from [20])
Further, the dissipated energy by a submodule capacitor as its voltage drops from
V_{peak}
to
V_{min}
is expressed as follows
[21]
:
where
C_{sm}
is submodule capacitance and
P
∆
t
is energy consumed (based on the assumption of constant power at
P
) during that time interval. Eq. (6) can be described the voltage term by
Small ripple approximation allows for the expression of voltage term on the right side as below:
∆
t
can also be expressed as ∆
t
≈
T
/2. Since
T
is 1/
f_{s}
, Eq. (9) can further be arranged as in the following:
It is obvious that the lower the switching interval, the lower the
V_{peaktopeakripple}
as concisely presented below:
Combining the observations above in (5) and (12), the relationship among frequency, voltage variation, and the loss can be summarized below:
3. Capacitor Voltage Balancing Control
This section discusses three well reported methods for balancing the submodule capacitor voltage balancing control: Full Sorting, Advanced Full Sorting and Group Sorting. It then presents an effective balancing based on Group Sorting with a supplementary adhoc switching signal incorporating the design tradeoff of voltage regulation and loss for each balancing method.
 3.1 Full sorting
Full Sorting may be the most basic but intuitive method for ranking all the measured voltages of the submodule capacitors at every switching instant and sequencing an order for turning on or off switches. The governing law states that the onstate submodules charge the corresponding capacitors for positive arm current and discharge the capacitors for negative arm current. The offstate submodules are bypassed regardless of the current direction. If the arm current is in the positive direction, then the onstate submodules in an upper or lower arm with the lowest voltages are selected to be turned on. The corresponding capacitor voltages then increase due to the charging process. If the arm current is negative, then the onstate submodules with the highest voltages are selected to be turned off and the corresponding capacitor voltages decrease. The balancing control using this Full Sorting scheme is shown in
Fig. 3
. In order to reduce the sensing cost, the current direction information can be derived from the voltage difference of two subsequently measured voltage samples
[22]
.
The Full Sorting: (a) Schematic of Full Sorting; (b) Arrangement and operation of each submodule.
Since it determines the onstate by checking the voltage of each submodule capacitor at each sampling time, on/off switching of the submodule occurs frequently.
Therefore, voltage regulation of the capacitor performs best and harmonics of the generated voltage waveforms could be minimal; a method focusing on the improvement of voltage regulation performance represented on the yaxis in
Fig. 1(a)
. However, the undesired high loss due to frequent switching is a critical constraint for high voltage applications as detailed with numerical data and graphs in Section 5.
 3.2 Advanced full sorting
The Advanced Full Sorting optimizes the designing capacitor voltage balancing schemes by adjusting the measured submodule capacitor voltages before the next sorting process. At each sampling time, if the offstate (onstate) submodule capacitor voltage is smaller (greater) than the onstate (offstate) submodule capacitor voltage with the current direction, the submodule of the on/off state exchanges. Multiplying the actual capacitor voltage of the onstate submodule by a maintaining factor (greater than one) increases the likelihood of maintaining the present state and thus avoids the unnecessary switching
[7]
as illustrated in
Fig. 4
. The Advanced Full Sorting method may be understood as a way to move towards less loss on the xaxis of
Fig. 1(a)
while not compromising the voltage regulation too much; balancing a tradeoff between the voltage regulation and the switching loss.
Diagram of the switching state changes: (a) Positive arm current without virtual voltage; (b) Positive arm current with virtual voltage; (c) Negative arm current without virtual voltage; (d) Negative arm current with virtual voltage.
 3.3 Group sorting
In order to avoid successive switching of the same submodule, the previous gate signal of the submodule can be considered. The first step of the Group Sorting scheme is classification of the groups by the previous state (onstate and offstate) of the submodules at the switching instant. Each group is sorted independently by its submodule capacitor voltages. Also, the
n_{on}
(
t
), which is the number of submodules, must be turned on at the current time step (See
Fig. 3
), and the arm current is then used to determine the individual gate signals at the current time step. As shown in
Fig. 5
, the number of difference onstate submodules in an arm (
Diff
) at the previous time step (
t
∆
t
) and that of the current time step (
t
) is positive, one of the offgroup submodules is commanded to be turned on. A submodule with the highest (lowest) voltage value in the offgroup is selected to discharge (charge) the submodule when the arm current is flowing negative (positive). When the sign of the
Diff
is negative, one of the onstate group submodules has to be turned off. Depending on the arm current direction, either the highest or lowest submodule is selected. In order to deal with numerous
Diff
in a single time step, the above process is repeated for each
Diff
. This scheme produces equally distributed capacitor voltage and switching commutation, which increases the mechanical reliability of power devices and reduces the power losses for the installed device
[23]
.
The group sorting: (a) Schematic of group sorting [5]; (b) Arrangement and operation of each submodule.
Group Sorting focuses on reducing the switching loss. By switching the highest or lowest submodule depending on the current direction at each sampling time, successive on/off switching of the same submodule occurs rarely. Therefore, the switching frequency of the submodule device and switching loss is the lowest compared with the above algorithms. However, the performance of the capacitor voltage can be compromised as detailed in Section 5.
4. Proposed ADHOC Switching Method for Voltage Balancing
The aforementioned Group Sorting complements the disadvantages of the Full Sorting method and improves the converter efficiency remarkably. As discussed in the previous Section 3.3, by dividing into two groups from the gate signal at previous time step (
t
∆
t
) and operating only the submodules in one group depending on
Diff
, all submodules can have one or less than one time state change denoted as
N
during the half period of the output waveform. Since the output waveform is synthesized by switching in or out submodule capacitor, the output voltage step transition is mostly one submodule capacitor voltage in the steadystate operation. The submodule that maintains each on or off state at the current time step does not participate in the switching until state variation of the total switching number occurs, which may adversely impact on the capacitor voltage balancing. The proposed method is designed to overcome these weaknesses.
The balancing is improved by augmenting the switching of the submodules determined from the Group Sorting. Additional switching is fired by actuating a signal whose frequency is determined according to the external variable as distinct from firing due to
N
change. The frequency of the actuating signal in this paper is calculated as (14).
where
f_{as}
is the actuating signal frequency,
k
is the number of exchange submodules for balancing,
N
is the number of submodules in an arm and
f_{s}
is the system frequency.
The basic operating strategy is illustrated in
Fig. 6
and is described as follows:
• Under positive
Diff
condition, the second lowest (second highest) module in offstate is turned on if the current direction is positive (negative) because the highest (lowest) module is already turned on. Then, in order to synchronize the number of onstate submodules with
N
change, the highest (lowest) submodule in onstate is turned off.
• Under negative
Diff
condition, the second highest (second lowest) module in onstate is turned on if the current direction is positive (negative) because the highest (lowest) module is already turned on. Then, in order to synchronize the number of offstate submodules with state variation, the lowest (highest) submodule in offstate is turned.
• In all cases, the number of on/off submodule for improving the voltage balance can be flexibly set or adjusted in either direction by an external command as needed.
Proposed balancing method: (a) Schematic of additional switching method; (b) Arrangement and operation of each submodule.
Compared with the Group Sorting method, the proposed balancing algorithm may remarkably reduce the THD by reducing the voltage ripple. As described in
[19]
, this method brings the desired computational efficiency for high voltage applications and flexibility in providing additional switching signal adaptive to the changing grid condition.
5. Simulation Results
The performance of proposed capacitor voltage balancing method is evaluated for an MMCHVDC using PSACD/ EMTDC. As depicted in
Fig. 7
, the HVDC transmission system benchmarked the Trans Bay Cable project
[24]
designed as a monopolar structure with DC voltage of ± 200 kV and submodule capacitance of 4.5 mF
[25]
, and number of submodules per arm of 200. The system is designed to transmit 400 MW from MMC 1 to MMC 2. The main circuit parameters are listed in
Table 1
. The NLM and desired system control functionalities (
P
control and
V_{dc}
control, etc.) are commonly implemented in the simulation system. In order to evaluate the performance of the proposed capacitor voltage balancing scheme, the capacitor voltages of 20submodules among the 200submodules in the upper arm of phase A are selected and compared with those of three conventional voltage balance methods.
Schematic diagram of MMCHVDC system.
Main Circuit Parameters of the Simulation System
Main Circuit Parameters of the Simulation System
For the convenience of presenting the results, Full Sorting, Advanced Full Sorting, Group Sorting and finally the proposed adhoc switching method are referred to be Methods I – IV, respectively in the following.
Figs. 8
and
9
illustrate the capacitor voltage waveforms and corresponding gate signals to the switching submodules.
Fig. 8
compares the submodule capacitor voltages of the upper arm in phaseA during 6cycles of period for four different balancing methods (Full Sorting, Advanced Full Sorting, Group Sorting and proposed Adhoc switching method are referred to Method I – IV in this section).
Fig. 8(a)
shows that the capacitor voltages become perfectly balanced with the Method I: the voltages performance should be the best among four different methods.
Comparison of submodule capacitor voltage with each balancing method: (a) Method I; (b) Method II; (c) Method III; (d) Method IV.
Gating signal of one switching device in submodule with each balancing method: (a) Method I; (b) Method II; (c) Method III; (d) Method IV.
However, the switching loss is the highest compared with the others due to the higher average switching frequency.
Fig. 8(b)
is presented for the result of Method II with a switching frequency of 169 Hz.
Fig. 8(b)
shows that the capacitor voltages are well balanced, but the capacitor voltage ripple is larger than Method I because the average switching frequency is lower than Method I.
Fig. 8(c)
is the result employing the Method III. The switching frequency is calculated to be 50 Hz, which is the lowest among four methods. However, the submodule capacitor voltages are not well balanced and the peaktopeak voltages are remarkable. In comparison with
Fig. 8(a)
, this figure shows that the capacitor voltages become unstable and the magnitude of the capacitor ripple is very large because of the low switching frequency.
Fig. 8(d)
illustrates the result of Method IV, similar to
Fig. 8(b)
. This resulted in the same 169 Hz switching frequency as the Method II and the proposed adhoc switching method successfully balances the capacitor voltages and the peaktopeak capacitor voltage ripples are compared to
Fig. 8(c)
.
Fig. 9(a)

(d)
compare the gate signals of one phase on the upper arm submodules under the four different modulation during 3cycles to illustrate the switching operation or switching frequency mentioned above.
Table 2
summarizes the study results in terms of the switching frequency, THD, switching, conduction and total losses for mentioned voltage balancing methods. The estimated switching and conduction losses are calculated as the percentage of transferred active power based on the datasheet of 5SNA1200G330100 insulatedgate bipolar transistors (IGBTs)
[26

28]
. For accurate comparison, we set the same switching frequency to the proposed adhoc switching method (Method IV) and the Advanced Full Sorting (Method II). As presented in
Table 2
, the same switching frequency leads to the same loss: Compare Methods II and IV. However, the THD of Method II is higher than that of the Method IV because the use of virtual voltage does not allow for uniformly distributed switchings. The Method IV is computationally efficient as mentioned in the previous Section 4.
Characteristic of each Balancing Method
Characteristic of each Balancing Method
6. Conclusions
This paper has presented a key design tradeoff in designing capacitor voltage balancing schemes for MMCHVDC: voltage regulation performance vs. converter switching loss. We have presented theoretical basis on these coupled attributes and further investigated the performance of three wellreported submodule capacitor voltage balancing methods (Full Sorting, Advanced Full Sorting and Group Sorting) from the perspective of design tradeoff. We have then proposed a new balancing scheme designed for balancing the design tradeoff flexibly in operations as well.
The method allows for additional switching of the submodules adaptive to changing grid condition and reinforces the benefit (minimal loss) of using the Group Sorting while not compromising the voltage regulation performance. We have demonstrated the flexibility and effectiveness of the proposed balancing scheme through simulation studies for a practical system using PSCAD/EMTDC with reference to the selected conventional schemes. The study presents that the proposed balancing method can significantly reduce the switching loss (as compared with the Full Sorting), THD (as compared with the Advanced Full Sorting and Group Sorting schemes), and submodule capacitor ripple (as compared with the Group Sorting). The flexibility built upon the high efficiency of the proposed method should help relieve the aforementioned design concerns and maximize the performance of the MMCHVDC.
Acknowledgements
This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government (MSIP) (No.20100028509) and also supported by the Yonsei University Research Fund of 2015.
BIO
Taesik Nam received his B.S. and Ph.D. degrees in electrical engineering from Yonsei University, Seoul, Korea in 2008 and 2015. Since 2015, he has been with LSIS Co. Ltd., Gyeonggido, Korea. Currently, he is the Associate Research Engineer of the HVDC System Research Team, LSIC. His research interests are highvoltage directcurrent systems, static var compensation and multilevel voltage source converter.
Heejin Kim received the B.S. degree in electrical engineering from Yonsei University, Seoul, Korea, in 2010 and the Ph.D. degree in electrical engineering from Yonsei University, Seoul, Korea, in 2015. Currently, he is a Postdoctoral Fellow at the Yonsei University, Seoul, Korea. His research interests include flexible AC transmission systems/high voltage direct current (FACTS/HVDC) and power electronics applications in power systems.
Sangmin Kim received the B.S. degree in Electrical Engineering from Yonsei University, Seoul, Korea, in 2013. He is currently working on the M.S. and Ph.D. combined degree in Yonsei University, Seoul, Korea. His research interests include high voltage direct current (HVDC) and modular multilevel converter (MMC) control.
Gum Tae Son received the B.S. and Ph.D. degrees from the School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea, in 2007 and 2013 respectively. He is currently an Associate Research Engineer in the LSIS Co. Ltd., Gyeonggido, Korea. His research interests include flexible ac transmission system, CSC highvoltage directcurrent system, VSC highvoltage directcurrent system, windturbine generator system and modular multilevel systems design.
Yong Ho Chung received the master degree and Ph.D. for Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Korea in 1985 and 1990, respectively. He was the visiting researcher at the University of WisconsinMadison in U.S.A. during 1994 to 1995. Since 1985, he is working for LSIS Co. Ltd., in Korea. Currently, he is the research fellow /V.P. and the head of HVDC research lab. His main research areas are Static Power Converter, UPS, Photovoltaic Inverter, Active Power Filter, Power Quality, Microgrid System, Dynamic Voltage Restorer, FACTS and HVDC applications.
JungWook Park was born in Seoul, Korea. He received the B.S. degree (summa cum laude) from the Department of Electrical Engineering, Yonsei University, Seoul, Korea, in 1999, and the M.S.E.C.E. and Ph.D. degrees from the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA in 2000 and 2003, respectively. He is currently an Associate Professor in the School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea. His current research interests are in power system dynamics, renewable energies based distributed generations, power control of electric vehicle, and optimization control algorithms.
ChanKi Kim obtained his M.Sc. and Ph.D. degrees in Electrical Engineering from ChungAng University, Korea in 1993 and 1996, respectively. Since 1996, he has been with KEPRI, the R&D center of KEPCO (Korea Electric Power Corporation). His research interests are HVDC and Power Electronics; he developed the HVDC simulator, HVDC commissioning technology and HVDC control algorithms. He received the Technical Award from the Ministry of Science and Technology of the Korean Government and Excellent Paper Awards from KIEE in 2002, 2004 and 2014 respectively. He is a senior member of IEEE and KIEE.
Kyeon Hur received his B.S. and M.S. degrees in electrical engineering from Yonsei University, Seoul, Korea, in 1996 and 1998, respectively, and the Ph.D. degree in electrical and computer engineering from The University of Texas at Austin in 2007. He has rejoined Yonsei University since 2010 and leads a smartgrid research group. His current research interests include FACTS/HVDC, PMUbased analysis and control, integration of variable generation and controllable load, and load modeling. He is an associate editor of Journal of Power Electronics and Journal of Electrical Engineering and Technology.
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