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An Efficient High Voltage Level Shifter using Coupling Capacitor for a High Side Buck Converter
An Efficient High Voltage Level Shifter using Coupling Capacitor for a High Side Buck Converter
Journal of Electrical Engineering and Technology. 2016. Jan, 11(1): 125-134
Copyright © 2016, The Korean Institute of Electrical Engineers
This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
  • Received : May 07, 2015
  • Accepted : August 01, 2015
  • Published : January 01, 2016
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About the Authors
Kwang-Su Seong
Corresponding Author: Dept. of Electronic Engineering, Yeungnam University, Korea. (kssung@ynu.ac.kr)

Abstract
We propose an efficient high voltage level shifter for a high side Buck converter driving a light-emitting diode (LED) lamp. The proposed circuit is comprised of a low voltage pulse width modulation (PWM) signal driver, a coupling capacitor, a resistor, and a diode. The proposed method uses a property of a PWM signal. The property is that the signal repeatedly transits between a low and high level at a certain frequency. A low voltage PWM signal is boosted to a high voltage PWM signal through a coupling capacitor using the property of the PWM signal, and the boosted high voltage PWM signal drives a p-channel metal oxide semiconductor (PMOS) transistor on the high side Buck converter. Experimental results show that the proposed level shifter boosts a low voltage (0 to 20 V) PWM signal at 125 kHz to a high voltage (370 to 380 V) PWM signal with a duty ratio of up to 0.9941.
Keywords
1. Introduction
Direct current (DC) power distribution is an effective solution considering the properties of DC-preferred loads. Many household appliances and office machines such as digital TVs, computers, facsimiles, copy machines, and solid-state lighting are DC-preferred loads. DC distribution has no alternating current (AC) losses and no reactive power issues [1 , 2] . DC distribution also helps eliminate the power factor correction (PFC) stages in the appliances and machines [2] .
Energy management in smart buildings with DC distribution that supplies power to DC electrical appliances such as lighting has recently attracted increasing interest from the research community [3] . Integrated lighting controls for demand-side energy management in a building can significantly improve energy efficiency, and enhance occupant comfort and satisfaction with the built environment [3] . In [4] , a DC-level dimmer supplies variable DC voltage to ballasts powering light emitting diode (LED) lamps, as shown in Fig. 1(a) . The DC-level dimmer sets its output voltage according to a dimming level, and ballasts adjust the brightness of their LED lamps according to the level of the DC voltage. The simplicity of this configuration, which requires no communication lines between the dimmer and ballasts, is a strong point. But this system is not appropriate for implementing a smart lighting system due to the lack of a bidirectional communication channel between the dimmer and the ballasts. In [3 , 5] , wireless or wired communication is applied to an intelligent smart lighting system. Fig. 1(b) shows a communication channel between the main controller and ballasts. The main controller can control the dimming level of the lamps through a communication channel, and supply optimal DC voltage to the ballasts using the information collected from the ballasts. The system shown in Fig. 1(b) was used in this study.
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(a) DC-level dimming system [4], (b) smart lighting system with variable DC voltage and dedicated communication channel, and (c) high side Buck converter.
A conventional 20 W LED tube that is retrofittable for a fluorescent tube uses 132 LEDs when 0.2 W LEDs are used. In the LED tube, 12 LED strings are connected in parallel, with 11 LEDs connected in series in an LED string [6 , 7] . There are deviations of the currents among the 12 LED strings connected in parallel, which gives deviations of the light intensities of the strings [7] . In this study, we adopted a high side Buck converter as shown in Fig. 1(c) . The converter drives an LED string where 100 LEDs are connected in series. In this case, the turn-on voltage of the LED string is about 300 V. As the LEDs are connected in series, the current flowing into each LED is the same, and the intensity of each LED is the same.
There are two options to implement the switch in Fig. 1(c) . One is to use an NMOS transistor, and the other is to use a PMOS transistor. An NMOS transistor is appropriate for a high-power and high-efficiency Buck converter because the on-resistance of the transistor is lower than that of a PMOS transistor. However, the driving circuit for the NMOS transistor is more complex than that for the PMOS transistor because the source voltage of the NMOS transistor is not fixed [8 , 9] . The on-resistance of a PMOS transistor is relatively high compared with that of an NMOS transistor, but the driving circuit for the PMOS transistor is relatively simple compared with that for the NMOS transistor because the source of the PMOS transistor is connected to a constant voltage. Thus, a PMOS transistor is appropriate for a low-power and low-cost Buck converter, especially when the output current of the converter is low. In this study, we chose the PMOS transistor because the Buck converter drives a 20 W LED lamp, and the output current of the converter is less than 100 mA.
In a Buck converter, the current flowing into an LED string can be controlled to reach a target by increasing the duty ratio of a pulse width modulation (PWM) control signal while appropriately decreasing the input voltage of the converter if the input voltage is controllable. In this case, the efficiency of the Buck converter can be increased. The high side Buck converter shown in Fig. 1(c) can exactly measure and control the current flowing into an LED string even if the input voltage is widely changed [10] . However, this structure requires a high side switch. Therefore, we must convert a low voltage PWM signal into a high voltage PWM signal. Many high voltage level shifter circuits have been proposed. The previous works were usually implemented using high voltage semiconductor process technology. The manufacturing cost of a level shifter usually increases as the target voltage of the level shifter is increased. Thus, the previous works are not appropriate for application in a low cost ballast circuit driving an LED sting when the target voltage of the level shifter is high. The previous works are described in Section 2.
We propose an efficient high voltage level shifter circuit for a high side Buck converter that drives an LED string. The proposed method uses the property of a PWM signal that repeatedly transits between a low and high level at a certain frequency. The circuit boosts a low voltage PWM signal to a high voltage PWM signal through a coupling capacitor using the property of the PWM signal. The high voltage PWM signal drives a p-channel metal oxide semiconductor (PMOS) transistor on the high side Buck converter. Although the proposed circuit consists of a low voltage PWM signal driver, a coupling capacitor, a resistor, and a diode, the circuit can provide enough high voltage PWM signal to drive the PMOS transistor. Experimental results show that the proposed level shifter was successfully applied to the high side Buck converter with an input voltage of 380 V, and boosts the low voltage (0 to 20 V) PWM signal at a frequency of 125 kHz to a high voltage (370 to 380 V) PWM signal with a duty ratio of up to 0.9941.
The remainder of this paper is organized as follows. Section 2 describes previous works. Section 3 explains the proposed circuit and its behavior. Section 4 describes our experimental results. Our conclusions are given in Section 5.
2. Previous Works
Fig. 2(a) shows a simple level shifter whose output is determined by the ratio of the two resistors and VDDH . The level shifter consumes static power when the input is high level, and the output driving capability is low due to the two resistors. This type of level shifter is usually used in low cost and low VDDH applications.
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(a) Simple level shifter; (b) latch-type CMOS level shifter; (c) DMOS cascade high voltage level shifter; (d) high voltage level shifter using coupling capacitors, and (e) pulse transformer coupled gate driver with DC restore circuit.
Fig. 2(b) shows a latch-type complementary MOS (CMOS) level shifter. The circuit has a cross-coupled PMOS latch on the top, and converts a low voltage input signal to a high voltage output signal by driving two n-channel MOS (NMOS) transistors on the bottom [11] . The level shifter has no static power consumption and a high driving capability, and can be integrated into a microcontroller unit (MCU) and other controllers based on CMOS semiconductor process technology. In a CMOS process technology, the maximum allowed source to gate voltage and source to drain voltage of PMOS are less than two times of VDDL , respectively. This level shifter circuit is limited in its ability to increase voltage VDDH because the voltage between the source and the gate of the PMOS can reach to VDDH , and the voltage between the source and the drain of the PMOS can also reach to VDDH . Improved versions of this type of level shifter have been reported, wherein VDDH is about two to five times higher than VDDL [12 , 13] .
Fig. 2(c) shows a high voltage version of Fig. 2(b) that uses a drain-extended MOS (DMOS). The structure of a DMOS is similar to that of a MOS except the drain of the DMOS is extended. The maximum allowed voltage between the gate and the source of the DMOS is the same as that of a conventional MOS, but high voltage can be applied across the drain and the source of the DMOS. In Fig. 2(c) , two n-channel DMOS (NDMOS) devices protect NMOS M 3 and M 4 . In the same way, two p-channel DMOS (PDMOS) devices protect PMOS M 1 and M 2 , thus M 1 and M 2 are placed between VSSH and VDDH [11 , 14] . Many improved versions of the level shifter shown in Fig. 2(b) have been reported [11 , 15 , 16] . However, the manufacturing cost of a level shifter using DMOS semiconductor process technology is higher than that of the level shifter using CMOS semiconductor process technology. Furthermore, the level shifter based on DMOS technology is not appropriate for integration into an MCU and other controllers based on CMOS technology. Thus, this type of level shifter is used as a stand-alone off-chip device.
Fig. 2(d) shows a level shifter circuit using coupling capacitors, wherein the initialization circuit for the drain nodes of the two PMOS transistors is omitted. The level shifter is an appropriate way to increase VDDH , because most of the value of VDDH exists across the coupling capacitors. However, the level shifter requires an initialization circuit and a cross-coupled PMOS latch [8 , 17] . Thus, the whole circuit of the level shifter in [8] was implemented on a single chip including two power switches (not shown in Fig. 2(d) ), the initialization circuit, the cross-coupled PMOS transistors, and the coupling capacitors (several pF). In many semiconductor processes, high voltage capacitors can be constructed only with normal routing metals, requiring large silicon area to obtain reasonable capacitance values and increasing the manufacturing cost [11] .
Fig. 2(e) shows a pulse transformer coupled gate driver with DC restore circuit. The advantages of the method are that it does not require isolated power supplies to drive the secondary-side NMOS transistor and maintains electrical isolation between the control and gate drive electronics. However, a problem can occur when a large transient drive current flowing in the inductive coils causes ringing. This can switch the gate on and off when not intended and damage the NMOS transistor. The transformer can deliver only AC signals with maintaining a volt-second balance, thus the transformer coupled gate driver needs a DC restore circuit to increase duty cycle capability. Fig. 2(e) shows a commonly used DC restore circuit that consists of C 2 and D 2 . The effective duty cycle range of the transformer coupled gate driver with the circuit is from 5 to 95% [18] .
3. Proposed Level Shifter
Fig. 3 shows the proposed level shifter circuit that consists of a low voltage pulse width modulation (PWM) signal driver, a coupling capacitor Cc , a resistor R 1 , and a diode D 1 . Capacitance Cg is the equivalent gate capacitance of the PMOS transistor. During the power-on period, the gate voltage of the PMOS is charged to VDDH through resistor R 1 . If the voltage of the PWM control signal vc ( t ) changes from VDDL to zero, the gate voltage changes from VDDH to VDDH – ( Cc / CA ) VDDL and is then continuously increased due to the current flowing through R 1 , where CA = Cc + Cg . Then, if the voltage of vc ( t ) changes from zero to VDDL , the gate voltage changes to VDDH + VD and then slightly decreases toward VDDH due to the voltage difference across resistor R 1 , where VD is the forward bias voltage of the diode.
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Proposed level shifter circuit.
Fig. 4(a) shows the timing of the control signal vc ( t ), whose duration is T and duty ratio is T 1 / T . When the control signal shown in Fig. 4(a) is applied to the proposed circuit in Fig. 3 , the voltage of the gate and the voltage difference between the gate and the source of the PMOS are as shown in Figs. 4(b) and (c) , respectively. As 0 ≤ T 1 < T , the maximum value of T 1 goes toward T . Eq. (1) can be obtained by applying Kirchhoff’s current law (KCL) to the gate node, where vG is the gate voltage of the PMOS.
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(a) Low voltage PWM control signal vc(t), (b) the gate voltage of the PMOS, and (c) the voltage difference between the gate and the source of the PMOS, where k is defined as the deviation ratio.
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When the control signal vc ( t ) transits from VDDL to zero at t = 0 as shown in Fig. 4(a) (i.e., vc ( t ) = VDDL u (– t )), the gate voltage at t = 0 + becomes vG ( t = 0 + ) = VDDH + VD - ( Cc / CA ) VDDL and the solution of Eq. (1) is given by Eq. (2) for 0 ≤ t < T 1 , where τ = R 1 CA and CA = Cc + Cg .
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Thus, the voltages of V 1 , V 2 , VA , and VB in Fig. 4 are expressed as Eqs. (3), (4), (5), and (6), respectively:
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We define the deviation ratio k of the gate voltage as Eq. (7), which is depicted in Fig. 4(c) . By applying Eqs. (5) and (6) to Eq. (7), we obtain Eqs. (8) and (9). Eq. (9) shows that the time constant of the proposed circuit depends on the deviation ratio k .
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In a PMOS transistor, VT means the threshold voltage at which the channel of the transistor starts to be created. VGS (TYP) means a typical turn-on voltage of the transistor, at which the transistor is in a sufficiently turn-on state. The manufacturer of the transistor usually uses VGS (TYP) to represent the performance of the transistor on the data sheet. VGS (MIN) is the minimum allowed voltage of VGS that can be applied to the transistor. The relation among the three voltages is given by VGS (MIN) < VGS (TYP) < VT < 0. In Eq. (5), if we set VA = VGS (TYP) , then we can obtain Eq. (10):
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By using Eqs. (8) and (10), we can obtain the capacitance of Cc as shown by Eq. (11). We can also obtain the resistance of R 1 as given by Eq. (12) by using Eqs. (9) and (11). Thus,
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Now, we calculate the power consumption of R 1 and D 1 . From Eqs. (2) and (6), the voltage difference between the source and the gate of the PMOS transistor is expressed as vSG ( t ) = − VBe t/τ in 0 ≤ t < T 1 . Thus, the average power consumption P R1 of resistor R 1 is expressed as Eq. (13).
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The diode D 1 can be approximated as a piecewise-linear model, as shown in Fig. 5 . As the diode is turned on during T 1 t < T , the average power consumption P D1 of the diode is expressed as Eq. (14).
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Approximation of diode D1 with piecewise-linear model.
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By applying KCL to the gate node, we can express the gate node voltage as Eq. (15), where τd = CA rd . We assume that the current flowing through R 1 is negligible because the voltage difference across the resistor is about VD when the diode is turned on.
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Thus, the diode current id ( t + T 1 ) is expressed as Eq. (16).
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The voltage difference VA - VB is due to the current flowing through R 1 during 0 ≤ t < T 1 , and is expressed as Eq. (17).
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Now, we can solve Eq. (14) by applying Eqs. (16) and (17) to Eq. (14). The solution is expressed as Eq. (18).
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The PWM signal driver also consumes power because it drives a capacitive load CL , where CL Cc Cg / ( Cc + Cg ) if R 1 is large enough for its effect on the circuit to be negligible. If ( VA VB ) / (− VB ) << 1 is satisfied in Fig. 4(c) , we can say the resistor gives little effect on the circuit. Because ( VA VB ) is expressed as Eq. (17), ( VA VB ) / (− VB ) < T / τ is satisfied, and we can use T / τ << 1 instead of ( VA VB ) / (− VB ) << 1. Thus the power consumption of the driver is expressed as Eq. (19) if T / τ << 1. On the other hand, CL is expressed as CL Cc if T / τ >> 1.
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During the power-on period, the PMOS transistor should be turned off. To satisfy this condition, the voltage between the gate and the source of the PMOS transistor should be larger than VT ; i.e., vGS ( t ) > VT . In Fig. 1(b) , if the output voltage of the DC-DC converter is programmable, the converter can also control the rise time of the output voltage. In this case, we can turn the PMOS off during the power-on period. Now, we will explain a necessary condition to turn off the PMOS during the power-on period if the output voltage of the DC-DC converter is not programmable.
Fig. 6 shows the timing diagram of supply voltage vDDH ( t ) during the power-on period where VDDH is the steady-state value of the supply voltage and tr is the rising time of the supply voltage. In this analysis, we assumed that the voltage of the control signal vc ( t ) is zero during the power-on period. By applying KCL to the gate node of the PMOS, we obtain Eq. (20):
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Supply voltage during the power-on period.
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In the power-on period (i.e., t tr ), the supply voltage is expressed as vDDH ( t ) = ( VDDH / tr ) t . Thus, the voltage of the gate node during the power-on period is expressed as Eq. (21) by solving Eq. (20):
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Thus, vGS ( t ) is expressed as Eq. (22) using Eq. (21):
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Eq. (22) has minimum value when t = tr for t tr . Thus, vGS ( tr ) should be larger than VT ; i.e., Eq. (23) should be satisfied in order to turn off the PMOS transistor during the power-on period.
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We can obtain the approximate rise time tr that satisfies Eq. (23). If tr / τ has large value,
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becomes very small compared to 1, and Eq. (23) is arranged as follows:
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Eq. (24) can be arranged as
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and
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if VDDH =380 V and VT = –3 V. Thus, the assumption that tr / τ has a large value and
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becomes significantly small compared to 1 is valid if VDDH is relatively high compared to – VT . Eq. (24) is arranged as Eq. (25) using Eq. (9). During the power-on period, Eq. (25) should be satisfied in order to turn off the PMOS transistor:
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In the analysis of the proposed circuit, we used parameter T 1 . The range of T 1 is 0 ≤ T 1 < T , and the maximum value of T 1 goes toward T . Thus T is used instead of T 1 when designing the proposed circuit, i.e., T is used instead of T 1 when determining the values of resistor R 1 and the coupling capacitor Cc . If the frequency of the PWM signal is 125 kHz ( T = 8 µs), VDDH is 380 V, VT is –3 V, Cg is 0.55 nF, k is 10%, V GS(TYP) is –10 V, VDDL is 20 V, and VD is 0.7 V, then we can obtain Cc = 0.78 nF and R 1 = 63.3 KΩ by using Eqs. (11) and (12). From Eq. (13) and (18), the power consumption of the resistor R 1 and that of the diode D 1 are expressed as P R1 < 1.92 mW and P D1 < 0.21 mW, respectively. The time constant ( τ = 84.2 us) is about 10 times larger than the duration ( T = 8 us), thus we can use Eq. (19) to calculate the power consumption of the PWM signal driver as PPWM ≈ 16.1 mW. PPWM is a major part of the total power consumption of the proposed circuit, and the sum of P R1 and P D1 represents only about 12 % of the total power consumption. The rise time of the high voltage vDDH ( t ) during the power-on period should be greater than 10.6 ms based on Eq. (25). Fig. 7 shows the simulation results of the proposed circuit using the parameters selected above when the duty ratio is 0.5. The wave form of the voltage of the gate node is quite similar to the wave form shown in Fig. 4(b) .
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Simulation results of the voltage of the gate node.
Until now, we assumed that a resistor and capacitor have fixed values, but the values vary with the temperature and tolerance. We set the error rates of the resistance and capacitance as p and q , respectively. When the resistance R 1 and capacitance Cc are respectively changed to R 1 (1+ p ) and Cc (1+ q ), the deviation ratio k is also changed according to Eq. (26) that is derived from Eq. (9), where τ ' = (1 + p ) R 1 ( Cg + (1 + q ) Cc ) = (1 + p ) ( τ + qR 1 Cc ).
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Table 1 shows the variation of k when p and q are within ±20% using T = 8 μs, R 1 = 63.3 KΩ, Cg = 0.55 nF, and Cc = 0.78 nF. The values of the parameters were used in the previous design example. When there are no errors in the resistance and capacitance, (i.e., p = q = 0%), the deviation ratio k is 10% that is the same as the value set in the previous example. In this case, VGS ( t ) < V GS(TYP) is satisfied in 0 ≤ t < T . When k is less than 10%, (i.e., τ' > τ), the voltage of the gate node is slowly charged compared with the case of k =10%. In this case, VGS ( t ) < V GS(TYP) is also satisfied in 0 ≤ t < T . However, the voltage of the gate node is rapidly charged when k > 10% compared with k = 10%, because τ' < τ. In this case, there are some ranges where VGS ( t ) < V GS(TYP) is not satisfied and the on-resistance of the PMOS transistor is increased. We need a new design guideline that ensures the proposed circuit works correctly even though k is varied, i.e., we have to choose R 1 and Cc such that the time constant is larger than τ in the worst case.
Variation ofkwith change ofpandq
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Variation of k with change of p and q
Now, we set
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as the adjusted resistance of R 1 . If p is within ± pMAX , then
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(1 – pMAX ) = R 1 should be satisfied to ensure R 1 ' ≥ R 1 . Thus, R 1 ' is expressed as Eq. (27).
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In the same way, we can obtain the adjusted capacitance Cc ' as Eq. (28), where q is within ± qMAX .
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The adjusted resistance R 1 ' and capacitance Cc ' are used instead of R 1 and Cc .
4. Experiments
The proposed level shifter was applied to the high side Buck converter as shown in Fig. 3 , where an inductor L of 82 mH and a capacitor C 1 of 0.5 μF are used, and a Fairchild FQD2P40 PMOS transistor is selected. The specification of the PMOS is as follows: the maximum gate capacitance C g(max) = 0.55 nF, the maximum threshold voltage V T(max) = −3 V, the minimum threshold voltage V T(min) = −5 V, the typical turn-on voltage V GS(TYP) = −10 V, and the minimum allowed gate-to-source voltage V GS(MIN) = −30 V. In this design, we set the parameter k = 10%, VDDH = 380 V, and VDDL = 20 V. With these parameters, the capacitance Cc and the resistance R 1 were determined to be Cc = 0.78 nF and R 1 = 63.3 kΩ as described in Section 3. The resistor used in this experiment has a tolerance of ±1% and temperature coefficient of ±100 ppm/℃, so we set the maximum error rate of the resistor as pMAX = 2%. The capacitor used in this experiment (ECWU type from Panasonic) has a tolerance of ±5% and capacitance variation of ±1% in the range of −30 ℃ − 80 ℃, so we set the maximum error rate of the capacitor as qMAX = 6%. The adjusted capacitance and resistance from Eq. (28) and (27) are Cc ' = 0.83 nF and R 1 ' = 64.6 KΩ, respectively. In this experiment, we selected available capacitor and resistor as Cc ' = 1 nF and R 1 ' = 68 kΩ. In this case, the voltages of VA and VB were calculated to be VA = −11.3 V and VB = −12.2 V based on Eqs. (5) and (6), respectively.
Fig. 8 shows the experimental configuration. An N5752A high voltage power supply (Agilent Technology) was used to generate 380 V, and IWS-S5552 LEDs (Itswell) were used in the LED string where 100 LEDs are connected in series. Fig. 9 shows the implemented circuit board whose size is 90 mm × 58 mm.
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Experimental configuration.
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Implementation of the proposed circuit.
In the first experiment, we measured the level-shifted high voltage PWM signal without connecting the LED string; i.e., the current flowing into the LED string was zero, and the drain node was floated. Fig. 10 shows the voltage of the PWM control signal vc ( t ) and the voltage of the gate node signal that is the level-shifted high voltage PWM signal. The frequency of the control signal is 125 kHz and the duty ratio of the signal is 0.762.
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Low voltage PWM signal and level-shifted high voltage PWM signal without connecting LED string.
The theoretical voltage of V 1 is 368.5 V from Eq. (3). Our experimental results show that V 1 is 367.4 V ( Fig. 10 ). There is a voltage difference of 1.1 V between the theoretical voltage and the experimental voltage. When a MOS transistor operates in linear mode, Cgs and Cgd have the same capacitance of C g(max) / 2 if the source and the drain are connected at the same potential [19] . In this experiment, the PMOS transistor was operated in linear mode when the transistor was in the turn-on state, but Cgd was less than C g(max) / 2 because the drain node was floated. Thus, the gate capacitance was less than C g(max) , which gave a lower value of V 1 than the theoretical voltage.
In the second experiment, we measured the level-shifted PWM signal with the connecting LED string. Fig. 11 shows the voltage of the gate node that was measured under the same conditions as the first experiment, except for the connecting LED string. In Fig. 11 , V 1 is 368.5 V, which is the same as the theoretical value calculated by using Eq. (3). The voltage VA = −11.5 V ( VA = V 1 VDDH ) was lower than V GS(TYP) . Thus, the PMOS transistor was in a sufficiently turn-on state at low level of the gate node voltage.
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Low voltage PWM signal and level-shifted high voltage PWM signal with connecting LED string.
When the control signal was increased from 0 to 20 V, the voltage of the gate node became 381 V, which is about VDDH plus VD . Then, the voltage of the gate node decreased by more than the expected value and became 378.6 V. The phenomenon is due to the voltage change of the PMOS drain node from 380 to 0 V with the small capacitance of several pF between the gate and the drain when the PMOS transistor is turned off. However, the lowest voltage of the gate node is 378.6 V at high level, and this gives VGS = −1.4 V, which is higher than the worst-case threshold voltage V T(max) = −3 V. Thus, the PMOS transistor kept the turn-off state at high level of the gate node voltage. This phenomenon can be reduced by connecting one or two diodes with diode D 1 in series, or by increasing the capacitance of Cc . Fig. 12 shows the current of the LED string, which is about 80 mA.
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Current flowing into the LED string.
The proposed method uses the property of a PWM signal, which transits between a low and high level repeatedly at a frequency. Theoretically, the proposed circuit can work in 0 ≤ T 1 < T . In the third experiment, we measured the maximum duty ratio wherein the proposed circuit works correctly. We then define that V A(with) = VA when the LED string is connected, and V A(without) = VA when the LED string is not connected. If V A(with) V GS(TYP) is satisfied, the circuit works correctly at the duty ratio because the PMOS transistor is sufficiently switched on for 0 ≤ t < T 1 and off for T 1 t < T . However, it is quite difficult to increase the duty ratio in the high side Buck converter when the LED string is connected, because the current flowing into the LED string is exponentially increased as the duty ratio is increased.
In this experiment, we used V A(without) instead of V A(with) . However, there is a voltage difference between V A(with) and VA(without), and the difference is 1.1 V at a duty ratio of 0.762 from the first and second experiments shown in Figs. 10 and 11 ; i.e., V A(with) = V A(without) +1.1 V. By considering the voltage difference, we approximately determined that the proposed circuit works correctly at the given duty ratio if V A(without) +1.1 ≤ V GS(TYP) is satisfied. Fig. 13 shows the high voltage PWM signal at a duty ratio of 0.9941. V A(without) is − 11.6 V (=368.4−380 V) that satisfies V A(without) + 1.1 ≤ V GS(TYP) . Thus, the proposed circuit works correctly at a duty ratio of 0.9941. However, V A(without) is −10.45 at a duty ratio of 0.9961, thus the proposed circuit does not work correctly at a duty ratio of 0.9961 because V A(without) + 1.1 ≤ V GS(TYP) is not satisfied. Thus, the proposed circuit works correctly up to a duty ratio of 0.9941.
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High voltage PWM signal without the connecting LED string at a duty ratio of 0.9941.
Now we will compare the proposed method with the gate driver using pulse transformer in Fig. 2(e) . The gate driver using pulse transformer addressed in Section 2 has the advantages that the driver can drive an NMOS transistor and it does not require isolated power supplies to drive the secondary-side NMOS transistor. However, the driver usually takes more components and requires the design of the transformer or at least the understanding of its operation and specification. The proposed method is very simple and easy to design, and works correctly up to a duty ratio of 99.5%, but the method is not applicable to an NMOS transistor. Another limitation of the proposed circuit is that the circuit may not work correctly if the frequency of the PWM signal applied to the circuit is lower than the target frequency.
5. Conclusion
We propose a high voltage level shifter using a coupling capacitor. Although the proposed circuit is a simple structure consisting of a low voltage PWM signal driver, a coupling capacitor, a resistor, and a diode, the proposed circuit can level a low voltage PWM signal up to high voltage PWM signal. The behavior of the level shifter was mathematically analyzed and a method to determine the capacitance of the coupling capacitor Cc and the resistance of the resistor R 1 is proposed. The proposed level shifter was applied to a high side Buck converter to drive the LED string. In the experiment, the input voltage of the converter was 380 V and the LED string consists of 100 LEDs connected in series. Our experimental results show that the proposed circuit converts a low voltage (0 to 20 V) PWM signal to a high voltage (370 to 380 V) PWM signal with a duty ratio of up to 0.9941.
Acknowledgements
This work was supported by a 2014 Yeungnam University research grant.
BIO
Kwang-Su Seong He received the B.S. degree in electronic engineering from Hanyang University, Seoul, Korea in 1990, and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1992 and 1997, respectively. He is currently an Associate Professor with the Department of Electronic Engineering, Yengnam University, Gyeong-buk, Korea. His current research interests include capacitive sensors, MCU design, and wireless power transmission for mobile devices.
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