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Analytic Model of Four-switch Inverter-fed Driving System for Wye or Delta-connected Motor with Current Ripple Reduction Scheme
Analytic Model of Four-switch Inverter-fed Driving System for Wye or Delta-connected Motor with Current Ripple Reduction Scheme
Journal of Electrical Engineering and Technology. 2016. Jan, 11(1): 109-116
Copyright © 2016, The Korean Institute of Electrical Engineers
This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
  • Received : May 06, 2015
  • Accepted : July 26, 2015
  • Published : January 01, 2016
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About the Authors
Dong-Myung Lee
School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea.
Jin-Woo Jung
Division of Electronics and Electrical Engineering, Dongguk University, Seoul, Korea.
Seo Weon Heo
School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea.
Tae Heoung Kim
Corresponding Author: Dept. of Electrical Engineering, ERI, Gyeongsang National University, Jinju, Korea. (ktheoung@gnu.ac.kr).

Abstract
This paper proposes an analytic model for four-switch inverter (FSI)-driven wye ( Y ) or delta ( Δ )-connected motors with a current ripple reduction algorithm. FSIs employ four switches in controlling three-phase load instead of using six switches. They have split dc-link stage, and due to this inherent structure there exists the voltage difference between upper and lower capacitors, which results in distortion of the inverter output voltage. To study characteristics of FSIs, this paper presents an advanced simulation models of FSI-driven control system for 3-phase motor that can has a wire connection either Y or Δ . In addition, this paper introduces a current ripple reduction scheme that mitigates degradation of control performance due to the voltage difference between the dc-link capacitors. The validity of the proposed method and the analytic model is verified by simulations and experiments carried out with 1-HP induction machine with Y or Δ -connection
Keywords
1. Introduction
Application of variable speed system by using inverters is expanding [1 - 3] . Adaption of inverters has advantages such as high energy efficiency and superior performance, but it has the disadvantage of price rise. For cost reduction, much research is actively underway, and the scheme that uses only four switches for controlling three-phase motors or loads instead of employing six switches has been introduced [4] . Hereinafter, this type inverter is referred to Four-Switch Inverter (FSI). FSIs have a structurally separated dc-link, and the middle point of the split dc-link is connected to one of 3-phase to get balanced 3-phase voltage outputs by two inverter legs [4] . Voltage generation methods of FSIs were presented through some papers [5 - 6] . Even FSIs has a merit of cost-reduction due to less number of switching devices compared with six-switch inverters (conventional 2-level inverters), FSIs may suffer from performance degradation because of the split dc-link causing voltage discrepancy between reference voltage and output voltage of FSIs. This problem does not exist in conventional 2-level inverters having a single dc-link capacitor. Many studies have been conducted to overcome this problem [7 - 10] . In [7] , switching times are calculated by using measured dc-link voltages to take into account the voltage difference between upper and lower capacitors in the split dc-link. However, the calculation process of switching time or equations presented in [7] is relatively complicated. [8] suggested a simple method for voltage fluctuation compensation by modification of switching time. In [8] , switching time was adjusted with consideration of the voltage difference between upper and lower capacitors in dc-link, and the scheme required to know location (position) of the reference voltage vector. In [9] , for compensating the neutral point potential fluctuation, the capacitance of the dc-link should be known.
Initially, FSIs have been devised for low cost drive systems. Nowadays, this scheme is widely studied for emergency operation [11 - 12] , and application of FSIs is enlarging to 3-phase induction motors as well as PMSMs and BLDC motors [13 - 14] . Therefore, the research about FSIs is highly required, especially the scheme of current ripple reduction due to their inherent characteristic by split dc-link. One of this paper’s authors suggested a current ripple reduction method in [10] . However, [10] presented only simulation results by using models provided in the library of Matlab/Simulink. The motor model from the library was a Y-connected motor. In order to apply FSIs to Y as well as Δ -connected motors, developing analytic model for both types is necessary. Hence, this paper presents an analytic model, which includes inverter block, rectification block, and motor block and so on. The validity of the proposed model and current ripple reduction method is demonstrated throughout simulation and experimental results.
2. Four-Switch Inverters (FSIs) and Operational Principle
Typical 2-level inverters used for controlling 3-phase load have six switches in their three arms. On the other hand, FSIs have four switches in two legs, i.e. one leg is missing. Dc-link of FSIs is split and one of terminals of 3-phase load is connected to the middle point of the split dc-link as shown in Fig. 1 . In Fig. 1 , c-phase is wired to the neutral point of the dc-link. Hereinafter based on this configuration, algorithm and an analytic model are explained. For generating balanced 3-phase voltages by FSIs, u and v pole voltages ( vuo, vvo ) are formed by adding - vcs to each pole voltage as shown in Fig. 2 and expressed as (1).
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Configuration of four-switch inverters.
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Voltage phasor diagrams of FSI with (a) Y-connection and (b) Δ-connection.
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where, vas , vbs , or vcs represent phase voltage.
The resultant pole voltages ( vuo and vvo ) consist of balanced 3-phase voltage ( vas , vbs, vcs ) and zero sequence voltages (- vcs ) as illustrated in Fig. 2 . Magnitude of pole voltage is
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times of the phase voltage for Y -case. Whereas, in the case of Δ -connection, magnitudes of phase and pole voltage are the same each other. Regardless of the connection type, the angle difference of the two pole voltages is 60 0 as displayed in Fig. 2 . Pole voltages, vuo and vvo , expressed by switching function can be written as (2). As w - (or c -) phase is connected to the neural point, c -pole voltage is zero, i.e. vwo =0.
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where, q 1 or q 3 stands for switching function of S 1 or S 3 , respectively. 1 denotes the upper switch in the arm is on, and 0 means the lower switch is on. Vdc is the magnitude of the dc-link voltage.
3. Proposed Current Ripple Compensation Method
- 3.1 Voltage fluctuation in FSI
Before describing an analytic model, a compensation method for phase current is explained first. The proposed method is based on [10] . In [10] , the performance of the scheme has been verified only by simulation results, and no simulation models were given. Fig. 3 illustrates four voltage vectors of FSI with referred to u1 (0, 0) that is aligned with the real axis. In the ideal case, i.e. V1 (potential of the upper capacitor) and V2 (potential of the lower capacitor) are equal to each other, four vectors are orthogonal each other as illustrated in Fig. 3 . However, when V1 > V2 , the orthogonal vectors are slant to the left. For the opposite case, V1 < V2 , voltage vectors are inclined to the right. If the voltage magnitude of the upper and lower dc-link capacitors is not equal to each other (i.e. V1 V2 ), there exists the voltage difference between the reference voltage and the generated voltage formed by (1). For getting more detailed analysis and explanation, please refer to [8] or [10] .
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Voltage vector diagram in case of (a) V1=V2 and (b) V1>V2.
- 3.2 The proposed scheme for mitigating voltage deviation
V1 and V2 in Fig. 1 can be given as (3) with making use of △V (= V1 –V2 ), respectively.
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When q1 =1, u -pole voltage ( vuo ) is V1 and the magnitude should be Vdc /2 for the ideal case, i.e. V1=V2=Vdc /2. If V1 V2 , vuo is not Vdc /2 and expressed as Vdc / 2 + Δ V / 2 as shown in Table 1 .
Generated pole voltages for the cases ofV1=V2andV1≠V2
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Generated pole voltages for the cases of V1=V2 and V1V2
In (3), Vdc represents the summation of V1 and V2 . It differs from the desired dc-link voltage, in other words
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. As summarized in Table 1 , vvo corresponding to q3 can be expressed as the same as the equation for vuo corresponding to q1 . Table 1 shows that regardless of the value of switching function (i.e. 0 or 1 for q1 or q3 ) the generated output voltage by FSIs is different from the reference as much as Δ Vdc / 2 [= ( V1-V2 )/ 2 ].
In the proposed scheme, to eliminate the voltage deviation of the generated vector, the new reference
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is modified as (4). As shown in (4), △V /2 is subtracted from the original pole-voltage reference (referred as vold ), and
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is multiplied to consider the fact that V1 +V2 Vdc .
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4. Modeling of FSI-drivenYorΔ-connected Motor Driving Systems
To study the characteristics of FSI and develop a new algorithm, simulation study is essential. Simulations for the proposed algorithm have been carried out by using Matlab/Simulink. The library named Simpowersystems in Matlab/Simulink possess passive and active elements such as a capacitor, motors, and power devices like IGBTs. However, as far as the authors know, the second generation Simpowersystems does not have Δ -connected motors, hence to do research of FSIs for Y as well as Δ -connected one, this paper proposes simulation models that can deal with Y and Δ -connected load as well, and is based on the differential equations. The entire proposed simulation block diagram is illustrated in Fig. 4 . The description of each block is as follows.
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Overall simulation blocks for the FSI system.
Block ① generates amplitude and angle ( θ ) for phase voltage references corresponding to modulation index ( ma ). The phase angle is updated as θ ( n )= θ ( n-1 )+ ω ( n )∙ T . In the formula, ω ( n )= 2πf ( n )∙ ma , and T represents the sampling time. Phase voltage references are generated by Block ②, and that for an induction motor with V/F control are expressed as (5), and realized by function block of Simulink.
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It should be noted that the proposed method is also applicable to the vector control of 3-phase motor as the following manner. By coordinate transformation, vas, vbs , and vcs can be obtained from α-β or d-q voltage references. After getting vuo and vvo by (1), the scheme shown in (4) is applied, and this manner has been demonstrated in [10] .
Fig. 5 illustrates the block diagram inside Block ③. In Block ③, (4) is implemented. After getting modified pole voltages, comparing them with carrier waveforms, switching state of the each arm is determined. As a result, there exist four modes corresponding to q1 and q3 such as (0,0), (0,1), (1,0), and (1,1), named mode 1~4 for each case. Phase voltages are determined by Block ⑤ with respect to the mode. Each phase voltage for Y or Δ -connected load is summarized in Table 2 .
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Compensated voltage and switching function generation block.
Phase voltages forYorΔ-connected motor
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Phase voltages for Y or Δ-connected motor
Fig. 6 shows implementation blocks of generating phase voltages corresponding to each mode. One of f ( u ) blocks, which is the input of multiport switch, is selected as the output corresponding to the mode. Inside the f ( u ) block, the phase voltage equation summarized in Table 2 for each mode is written.
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Phase voltage generation block inside Block ⑤.
The FSI having split dc-link with a diode rectifier and its equivalent circuit are illustrated in Fig. 7 .
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FSI system having: (a) dc-link with a diode rectifier and (b) its equivalent circuit.
Block ④ has a role to determine the dc-link voltage of upper and lower capacitors corresponding to the mode. In this research, a single phase diode bridge shown as Fig. 7(a) is used for rectification. Equ. (7) represents the numerical equations of Fig. 7(b) . Where, Ll stands for the stray inductance, and iret is the input current of the diode rectifier. R1 and R2 are the equivalent series resistances (ESR) of the capacitors. Equ. (6) is implemented as Fig. 8 .
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Simulink model inside Block ④ for dc-link part consisted with a diode bridge and split capacitor.
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Because of using the diode bride, there is no power regeneration. Hence, the magnitude of iret is always positive, and that characteristic is modeled in the top portion of Fig. 8 by using the simulation blocks that never allow the iret going below zero. First idc1 and idc2 for each mode are determined, and then by integrating dc-link capacitor currents ( ic1 and ic2 ) the magnitudes of voltage in upper and lower capacitor ( V1 and V2 ) are decided. The idc1 and idc2 varied with mode are summarized in Table 3 for Y and Δ -connections. In Table 3 , ixs means phase current.
Current components in the dc-link expressed by phase currents
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Current components in the dc-link expressed by phase currents
Modelling of motors with Simulink is well-known and it is able to find out various motor models from many textbooks such as [15] . Hence, inside of Block ⑥ is not displayed in this paper due to the lack of space. Similar to the model shown in [15] , an induction motor has been modelled based on equations of voltages and flux-linkage in the α-β (stationary) reference frame. Some equations involved in Block ⑥ are summarized in (7). In (7), superscript s represents the stationary reference frame. The q -axis is aligned with a -phase axis. s, r , and m denote stator, rotor, and airgap, respectively. P represents number of poles.
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Block ⑦ implementing the mechanical equation expressed in (8) is also well known so that inside of Block ⑦ is not illustrated. Where, J, B , and TL represent the inertia, coefficient of friction, and load torque, separately.
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5. Simulation Results
- 5.1 Simulation study using Matlab/Simulink®
To verify the effective of the proposed scheme, simulations have been carried out. V/F control of an induction motor has been performed. One horse power induction motor used in simulation study has the specifications as Rs (stator resistance)= Rr (rotor resistance) =8Ω, Lm (magnetizing inductance) = 200 m H, and Lls (stator leakage inductance)= Llr (rotor leakage inductance)= 10 m H.
Fig. 9 illustrates simulation results carried out with Y -connected induction motor operated at 500rpm. From the top to the bottom, waveforms of vas (or vus ), vbs (or vvs ), and phase currents are shown. The magnitude of motor phase voltages has the level of ± Vdc /6≈±50V, ± Vdc /2 ≈±150V with Vdc =300V. These values of phase voltages can be found from Table 2 . Compensation algorithm is applied in the period from t =0.75 seconds to t =1.2 seconds. As displayed in Fig. 9 , before applying compensation algorithm, the phase current unbalance is a significant amount but after applying the proposed scheme, the unbalance of the phase currents is significantly reduced.
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Simulation results of Y-connected motor with operation at 500 rpm: From top to bottom vas, vbs (200V/div.), and phase currents (ias, ibs, and ics 2A/div.).
Fig. 10 shows simulation results for Δ -connected motor operated by V/F control with and without the current ripple reduction scheme. 470 μ F capacitors are used for the dc-link for the simulation studies of Y as well as Δ -connected motors. As the same as the result of Y -case, the proposed scheme considerably reduces the amount of unbalance in the phase current. In Fig. 10 from top to bottom, vas (or vus ), vbs (or vvs ), and phase currents are shown. vas or vbs has the different voltage level of Y -case, and it has the level of ± Vdc ≈±300V, or ± Vdc /2≈±150V, respectively. These phase voltages are generated by using Block ④~⑥ based on Table 2 . As the line current of Δ -connected motors is bigger than that of Y -connected one, effect of the error between the generated voltage and the reference voltage are severe for Δ -case.
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Simulation results of Δ-connected motor with operation at 500rpm: From top to bottom vas, vbs (200V/div.), and phase currents (ias, ibs, and ics 5A/div.).
- 5.2 FEM analysis results
Study using Finite Element Method (FEM) has been carried out for a FSI-driven induction motor. To get the accurate results, time-stepped voltage source finite element method with the current ripple reduction algorithm was used. The non-linear characteristics of the iron (stator and rotor) were also considered. Fig. 11 shows the waveform of air-gap flux density at rated load using finite element analysis. Br and Bseta stand for the radial and the tangential component of the air-gap flux density, respectively.
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Air-gap flux density waveform of Y-connected motor driven by FSI at rated load.
Fig. 12 and Fig. 13 illustrate the flux line and the distribution of flux density with Y -connected induction motor driven by a FSI, respectively. From these figures, it can be known that the FSI with the current ripple reduction scheme shows the same ability as the conventional six-switch inverters
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Flux lines controlled by FSI at rated load.
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The distribution of flux density driven by FSI at rated load.
6. Experimental Results
Experiments using an induction motor were performed to verify the validity of the proposed scheme and the simulation model. The proposed algorithm for reducing ripples of phase currents was implemented by TMS320-F28335 digital signal processor. Switching frequency is 8kHz, and voltages of upper and lower dc-link capacitors, which have 470 μ F for each one, are measured. To compare the experimental results with simulation results especially phase voltages, a motor with 6 terminals, which can be connected with Y or Δ connection was used. 4-pole 0.75kW induction motor for experiments has rated speed of 1690rpm, and 3.8A/2.2A rated current for 220V/ 380V operation.
Fig. 14 shows experimental result done at 500rpm for (a) without and (b) with the proposed method for Y -case, respectively. Each figure illustrates b-, c -phase currents (equivalent to line current in Y -connection) and pole voltage references ( vuo and vvo ). Same as the simulation results of Fig. 9 , it can be seen that the magnitude difference between each phase current is reduced by the proposed method. The distortion of current level is reduced a lot after applying the proposed scheme, and the levels of a - and b -phase voltages, which are around ±50V and ±100V, well agree with the simulation result of Y -case illustrated in Fig. 9 .
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Experimental result for Y-connected motor: (a) without and (b) with the proposed algorithm operated at 500rpm. From top to bottom phase currents (ibs, ics 2A/div.), and phase voltages (vbs, vcs 200V/div.).
Fig. 15 shows the experimental waveforms for a Δ -connected motor rotated at 500rpm (a) without and (b) without the proposed algorithm, respectively. The magnitude of phase current unbalance is bigger than that of Y -connection. Fig. 15(b) demonstrates that after applying the compensation algorithm, the difference between each line current is reduced, and line currents become to have the same peak to peak values. The level of a - and b -phase voltages ( vas, vbs ) coincide with the simulation results as illustrated in Fig. 10 . Same as the voltage levels summarized in Table 2 , the experimental results has the voltage levels of ± Vdc ≈±300V, or 0V for vas and vbs . From Fig. 14 and 15 , it can be known that experimental results confirm the validity of the analytic model and the proposed scheme.
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Experimental result for Δ-connected motor: (a) without and (b) with the proposed algorithm operated at 500rpm. From top to bottom line currents (ib, ic 5A/div.), and phase voltages (vas, vbs 350V/div.).
7. Conclusion
In this paper, analytic models made by Matlab/Simulink for FSI-driven Y and Δ -connected motors were presented and the distribution of flux density of motor driven by FSI was illustrated. In addition, the simple current ripple compensation method for FSIs was proposed. In order to do research and/or develop an algorithm for Y as well as Δ -connected motors or loads, an analytic model based on differential equations was developed. The compensation method based on modification of pole voltage references was applied to both connection types and tested. The simulation and experimental results applied in an induction motor with Y or Δ-connection have verified the validity of the proposed current ripple reduction method and analytic models. All or portion of the proposed model will contribute to the future research in this field.
Acknowledgements
This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education, Science and Technology(NRF-2013R1A1A2007739)
BIO
Dong-Myung Lee received his B.S. and M.S. in Electrical Engineering from Hanyang University, Seoul, Korea, in 1994 and 1996, respectively, and his Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology, Atlanta, Georgia, USA, in2004. From 1996 to 2000, he worked for LG Electronics Inc., Seoul, Korea. From 2004 to 2007, he was employed by the Samsung SDI R&D Center, Yongin, Korea, as a Senior Engineer. From 2007 to 2008, he was with the Department of Electrical Engineering, Hanyang University, as a Research Professor. Since 2008, he has been an Associate Professor with the School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea. His current research interests include variable speed drives, power quality compensation devices, and power conversion systems for renewable energy sources.
Jin-Woo Jung received the B.S. and M.S. degrees in Electrical Engineering from Hanyang University, Seoul, Korea in 1991 and 1997, respectively, and the Ph.D. degree in Electrical and Computer Engineering from The Ohio State University, Columbus, Ohio, USA, in 2005. From 1997 to 2000, he was with the Home Appliance Research Laboratory, LG Electronics Co., Ltd., Seoul, Korea. From 2005 to 2008, he was a Senior Research Engineer with the R&D Center and PDP Development Team, Samsung SDI Co., Ltd., Korea. Since 2008, he has been an Associate Professor with the Division of Electronics and Electrical Engineering, Dongguk University, Seoul, Korea. His current research interests include DSP-based electric machine drives, distributed generation systems using renewable energy sources, and power conversion systems and drives for electric vehicles (EVs).
Seo Weon Heo received the B.S. and M.S. degrees in electronic engineering from Seoul National University, Seoul, Korea in 1990 and 1992, respectively, and the Ph.D. degree in electrical engineering from the Purdue University, West Lafayette, Indiana, in 2001. From 1992 to1998, he was with the Digital Media Research Laboratory, LG Electronics Co., Ltd., Korea. From 2001 to 2006, he worked at the Telecommunication R&D Center, Samsung Electronics Co., Ltd., Korea. Since 2006, he has been an Associate Professor with the School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea. His current research interests are in the area of wireless communication, advanced signal processing, and embedded system HW/SW design.
Tae Heoung Kim received his B.S., M.S., and Ph.D. in Electrical Engineering from Hanyang University, Seoul, Korea, in 1993, 1995, and 2005, respectively. From 1995 to 2002, he worked for LG Electronics as a Senior Research Engineer. Since 2005, he has been a Professor in the Department of Electrical Engineering, Gyeongsang National University, Jinju, Korea. His research interests include the design of electric machines and control systems.
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