This paper proposes an analytic model for fourswitch inverter (FSI)driven wye (
Y
) or delta (
Δ
)connected motors with a current ripple reduction algorithm. FSIs employ four switches in controlling threephase load instead of using six switches. They have split dclink stage, and due to this inherent structure there exists the voltage difference between upper and lower capacitors, which results in distortion of the inverter output voltage. To study characteristics of FSIs, this paper presents an advanced simulation models of FSIdriven control system for 3phase motor that can has a wire connection either
Y
or
Δ
. In addition, this paper introduces a current ripple reduction scheme that mitigates degradation of control performance due to the voltage difference between the dclink capacitors. The validity of the proposed method and the analytic model is verified by simulations and experiments carried out with 1HP induction machine with
Y
or
Δ
connection
1. Introduction
Application of variable speed system by using inverters is expanding
[1

3]
. Adaption of inverters has advantages such as high energy efficiency and superior performance, but it has the disadvantage of price rise. For cost reduction, much research is actively underway, and the scheme that uses only four switches for controlling threephase motors or loads instead of employing six switches has been introduced
[4]
. Hereinafter, this type inverter is referred to FourSwitch Inverter (FSI). FSIs have a structurally separated dclink, and the middle point of the split dclink is connected to one of 3phase to get balanced 3phase voltage outputs by two inverter legs
[4]
. Voltage generation methods of FSIs were presented through some papers
[5

6]
. Even FSIs has a merit of costreduction due to less number of switching devices compared with sixswitch inverters (conventional 2level inverters), FSIs may suffer from performance degradation because of the split dclink causing voltage discrepancy between reference voltage and output voltage of FSIs. This problem does not exist in conventional 2level inverters having a single dclink capacitor. Many studies have been conducted to overcome this problem
[7

10]
. In
[7]
, switching times are calculated by using measured dclink voltages to take into account the voltage difference between upper and lower capacitors in the split dclink. However, the calculation process of switching time or equations presented in
[7]
is relatively complicated.
[8]
suggested a simple method for voltage fluctuation compensation by modification of switching time. In
[8]
, switching time was adjusted with consideration of the voltage difference between upper and lower capacitors in dclink, and the scheme required to know location (position) of the reference voltage vector. In
[9]
, for compensating the neutral point potential fluctuation, the capacitance of the dclink should be known.
Initially, FSIs have been devised for low cost drive systems. Nowadays, this scheme is widely studied for emergency operation
[11

12]
, and application of FSIs is enlarging to 3phase induction motors as well as PMSMs and BLDC motors
[13

14]
. Therefore, the research about FSIs is highly required, especially the scheme of current ripple reduction due to their inherent characteristic by split dclink. One of this paper’s authors suggested a current ripple reduction method in
[10]
. However,
[10]
presented only simulation results by using models provided in the library of Matlab/Simulink. The motor model from the library was a Yconnected motor. In order to apply FSIs to
Y
as well as
Δ
connected motors, developing analytic model for both types is necessary. Hence, this paper presents an analytic model, which includes inverter block, rectification block, and motor block and so on. The validity of the proposed model and current ripple reduction method is demonstrated throughout simulation and experimental results.
2. FourSwitch Inverters (FSIs) and Operational Principle
Typical 2level inverters used for controlling 3phase load have six switches in their three arms. On the other hand, FSIs have four switches in two legs, i.e. one leg is missing. Dclink of FSIs is split and one of terminals of 3phase load is connected to the middle point of the split dclink as shown in
Fig. 1
. In
Fig. 1
, cphase is wired to the neutral point of the dclink. Hereinafter based on this configuration, algorithm and an analytic model are explained. For generating balanced 3phase voltages by FSIs,
u
and
v
pole voltages (
v_{uo}, v_{vo}
) are formed by adding 
v_{cs}
to each pole voltage as shown in
Fig. 2
and expressed as (1).
Configuration of fourswitch inverters.
Voltage phasor diagrams of FSI with (a) Yconnection and (b) Δconnection.
where,
v_{as}
,
v_{bs}
, or
v_{cs}
represent phase voltage.
The resultant pole voltages (
v_{uo}
and
v_{vo}
) consist of balanced 3phase voltage (
v_{as}
,
v_{bs}, v_{cs}
) and zero sequence voltages (
v_{cs}
) as illustrated in
Fig. 2
. Magnitude of pole voltage is
times of the phase voltage for
Y
case. Whereas, in the case of
Δ
connection, magnitudes of phase and pole voltage are the same each other. Regardless of the connection type, the angle difference of the two pole voltages is 60
^{0}
as displayed in
Fig. 2
. Pole voltages,
v_{uo}
and
v_{vo}
, expressed by switching function can be written as (2). As
w
 (or
c
) phase is connected to the neural point,
c
pole voltage is zero, i.e.
v_{wo}
=0.
where,
q
_{1}
or
q
_{3}
stands for switching function of
S
_{1}
or
S
_{3}
, respectively. 1 denotes the upper switch in the arm is on, and 0 means the lower switch is on.
V_{dc}
is the magnitude of the dclink voltage.
3. Proposed Current Ripple Compensation Method
 3.1 Voltage fluctuation in FSI
Before describing an analytic model, a compensation method for phase current is explained first. The proposed method is based on
[10]
. In
[10]
, the performance of the scheme has been verified only by simulation results, and no simulation models were given.
Fig. 3
illustrates four voltage vectors of FSI with referred to
u_{1}
(0, 0) that is aligned with the real axis. In the ideal case, i.e.
V_{1}
(potential of the upper capacitor) and
V_{2}
(potential of the lower capacitor) are equal to each other, four vectors are orthogonal each other as illustrated in
Fig. 3
. However, when
V_{1}
>
V_{2}
, the orthogonal vectors are slant to the left. For the opposite case,
V_{1}
<
V_{2}
, voltage vectors are inclined to the right. If the voltage magnitude of the upper and lower dclink capacitors is not equal to each other (i.e.
V_{1}
≠
V_{2}
), there exists the voltage difference between the reference voltage and the generated voltage formed by (1). For getting more detailed analysis and explanation, please refer to
[8]
or
[10]
.
Voltage vector diagram in case of (a) V_{1}=V_{2} and (b) V_{1}>V_{2}.
 3.2 The proposed scheme for mitigating voltage deviation
V_{1}
and
V_{2}
in
Fig. 1
can be given as (3) with making use of
△V
(=
V_{1} –V_{2}
), respectively.
When
q_{1}
=1,
u
pole voltage (
v_{uo}
) is
V_{1}
and the magnitude should be
V_{dc}
/2 for the ideal case, i.e.
V_{1}=V_{2}=V_{dc}
/2. If
V_{1}
≠
V_{2}
,
v_{uo}
is not
V_{dc}
/2 and expressed as
V_{dc} / 2
+ Δ
V / 2
as shown in
Table 1
.
Generated pole voltages for the cases ofV1=V2andV1≠V2
Generated pole voltages for the cases of V_{1}=V_{2} and V_{1}≠V_{2}
In (3),
V_{dc}
represents the summation of
V_{1}
and
V_{2}
. It differs from the desired dclink voltage, in other words
. As summarized in
Table 1
,
v_{vo}
corresponding to
q_{3}
can be expressed as the same as the equation for
v_{uo}
corresponding to
q_{1}
.
Table 1
shows that regardless of the value of switching function (i.e.
0
or
1
for
q_{1}
or
q_{3}
) the generated output voltage by FSIs is different from the reference as much as Δ
V_{dc} / 2
[= (
V_{1}V_{2}
)/
2
].
In the proposed scheme, to eliminate the voltage deviation of the generated vector, the new reference
is modified as (4). As shown in (4),
△V
/2 is subtracted from the original polevoltage reference (referred as
v^{old}
), and
is multiplied to consider the fact that
V_{1} +V_{2}
≠
V_{dc}
.
4. Modeling of FSIdrivenYorΔconnected Motor Driving Systems
To study the characteristics of FSI and develop a new algorithm, simulation study is essential. Simulations for the proposed algorithm have been carried out by using Matlab/Simulink. The library named Simpowersystems in Matlab/Simulink possess passive and active elements such as a capacitor, motors, and power devices like IGBTs. However, as far as the authors know, the second generation Simpowersystems does not have
Δ
connected motors, hence to do research of FSIs for
Y
as well as
Δ
connected one, this paper proposes simulation models that can deal with
Y
and
Δ
connected load as well, and is based on the differential equations. The entire proposed simulation block diagram is illustrated in
Fig. 4
. The description of each block is as follows.
Overall simulation blocks for the FSI system.
Block ① generates amplitude and angle (
θ
) for phase voltage references corresponding to modulation index (
m_{a}
). The phase angle is updated as
θ
(
n
)=
θ
(
n1
)+
ω
(
n
)∙
T
. In the formula,
ω
(
n
)=
2πf
(
n
)∙
m_{a}
, and
T
represents the sampling time. Phase voltage references are generated by Block ②, and that for an induction motor with
V/F
control are expressed as (5), and realized by function block of Simulink.
It should be noted that the proposed method is also applicable to the vector control of 3phase motor as the following manner. By coordinate transformation,
v_{as}, v_{bs}
, and
v_{cs}
can be obtained from
αβ
or
dq
voltage references. After getting
v_{uo}
and
v_{vo}
by (1), the scheme shown in (4) is applied, and this manner has been demonstrated in
[10]
.
Fig. 5
illustrates the block diagram inside Block ③. In Block ③, (4) is implemented. After getting modified pole voltages, comparing them with carrier waveforms, switching state of the each arm is determined. As a result, there exist four modes corresponding to
q_{1}
and
q_{3}
such as (0,0), (0,1), (1,0), and (1,1), named mode 1~4 for each case. Phase voltages are determined by Block ⑤ with respect to the mode. Each phase voltage for
Y
or
Δ
connected load is summarized in
Table 2
.
Compensated voltage and switching function generation block.
Phase voltages forYorΔconnected motor
Phase voltages for Y or Δconnected motor
Fig. 6
shows implementation blocks of generating phase voltages corresponding to each mode. One of
f
(
u
) blocks, which is the input of multiport switch, is selected as the output corresponding to the mode. Inside the
f
(
u
) block, the phase voltage equation summarized in
Table 2
for each mode is written.
Phase voltage generation block inside Block ⑤.
The FSI having split dclink with a diode rectifier and its equivalent circuit are illustrated in
Fig. 7
.
FSI system having: (a) dclink with a diode rectifier and (b) its equivalent circuit.
Block ④ has a role to determine the dclink voltage of upper and lower capacitors corresponding to the mode. In this research, a single phase diode bridge shown as
Fig. 7(a)
is used for rectification. Equ. (7) represents the numerical equations of
Fig. 7(b)
. Where,
L_{l}
stands for the stray inductance, and
i_{ret}
is the input current of the diode rectifier.
R_{1}
and
R_{2}
are the equivalent series resistances (ESR) of the capacitors. Equ. (6) is implemented as
Fig. 8
.
Simulink model inside Block ④ for dclink part consisted with a diode bridge and split capacitor.
Because of using the diode bride, there is no power regeneration. Hence, the magnitude of
i_{ret}
is always positive, and that characteristic is modeled in the top portion of
Fig. 8
by using the simulation blocks that never allow the
i_{ret}
going below zero. First
i_{dc1}
and
i_{dc2}
for each mode are determined, and then by integrating dclink capacitor currents (
i_{c1}
and
i_{c2}
) the magnitudes of voltage in upper and lower capacitor (
V_{1}
and
V_{2}
) are decided. The
i_{dc1}
and
i_{dc2}
varied with mode are summarized in
Table 3
for
Y
and
Δ
connections. In
Table 3
,
i_{xs}
means phase current.
Current components in the dclink expressed by phase currents
Current components in the dclink expressed by phase currents
Modelling of motors with Simulink is wellknown and it is able to find out various motor models from many textbooks such as
[15]
. Hence, inside of Block ⑥ is not displayed in this paper due to the lack of space. Similar to the model shown in
[15]
, an induction motor has been modelled based on equations of voltages and fluxlinkage in the
αβ
(stationary) reference frame. Some equations involved in Block ⑥ are summarized in (7). In (7), superscript
s
represents the stationary reference frame. The
q
axis is aligned with
a
phase axis.
s, r
, and
m
denote stator, rotor, and airgap, respectively.
P
represents number of poles.
Block ⑦ implementing the mechanical equation expressed in (8) is also well known so that inside of Block ⑦ is not illustrated. Where,
J, B
, and
T_{L}
represent the inertia, coefficient of friction, and load torque, separately.
5. Simulation Results
 5.1 Simulation study using Matlab/Simulink®
To verify the effective of the proposed scheme, simulations have been carried out.
V/F
control of an induction motor has been performed. One horse power induction motor used in simulation study has the specifications as
R_{s}
(stator resistance)=
R_{r}
(rotor resistance) =8Ω,
L_{m}
(magnetizing inductance) = 200
m
H, and
L_{ls}
(stator leakage inductance)=
L_{lr}
(rotor leakage inductance)= 10
m
H.
Fig. 9
illustrates simulation results carried out with
Y
connected induction motor operated at 500rpm. From the top to the bottom, waveforms of
v_{as}
(or
v_{us}
),
v_{bs}
(or
v_{vs}
), and phase currents are shown. The magnitude of motor phase voltages has the level of ±
V_{dc}
/6≈±50V, ±
V_{dc}
/2 ≈±150V with
V_{dc}
=300V. These values of phase voltages can be found from
Table 2
. Compensation algorithm is applied in the period from
t
=0.75 seconds to
t
=1.2 seconds. As displayed in
Fig. 9
, before applying compensation algorithm, the phase current unbalance is a significant amount but after applying the proposed scheme, the unbalance of the phase currents is significantly reduced.
Simulation results of Yconnected motor with operation at 500 rpm: From top to bottom v_{as}, v_{bs} (200V/div.), and phase currents (i_{as}, i_{bs}, and i_{cs} 2A/div.).
Fig. 10
shows simulation results for
Δ
connected motor operated by
V/F
control with and without the current ripple reduction scheme. 470
μ
F capacitors are used for the dclink for the simulation studies of
Y
as well as
Δ
connected motors. As the same as the result of
Y
case, the proposed scheme considerably reduces the amount of unbalance in the phase current. In
Fig. 10
from top to bottom,
v_{as}
(or
v_{us}
),
v_{bs}
(or
v_{vs}
), and phase currents are shown.
v_{as}
or
v_{bs}
has the different voltage level of
Y
case, and it has the level of ±
V_{dc}
≈±300V, or ±
V_{dc}
/2≈±150V, respectively. These phase voltages are generated by using Block ④~⑥ based on
Table 2
. As the line current of
Δ
connected motors is bigger than that of
Y
connected one, effect of the error between the generated voltage and the reference voltage are severe for
Δ
case.
Simulation results of Δconnected motor with operation at 500rpm: From top to bottom v_{as}, v_{bs} (200V/div.), and phase currents (i_{as}, i_{bs}, and i_{cs} 5A/div.).
 5.2 FEM analysis results
Study using Finite Element Method (FEM) has been carried out for a FSIdriven induction motor. To get the accurate results, timestepped voltage source finite element method with the current ripple reduction algorithm was used. The nonlinear characteristics of the iron (stator and rotor) were also considered.
Fig. 11
shows the waveform of airgap flux density at rated load using finite element analysis.
B_{r}
and
B_{seta}
stand for the radial and the tangential component of the airgap flux density, respectively.
Airgap flux density waveform of Yconnected motor driven by FSI at rated load.
Fig. 12
and
Fig. 13
illustrate the flux line and the distribution of flux density with
Y
connected induction motor driven by a FSI, respectively. From these figures, it can be known that the FSI with the current ripple reduction scheme shows the same ability as the conventional sixswitch inverters
Flux lines controlled by FSI at rated load.
The distribution of flux density driven by FSI at rated load.
6. Experimental Results
Experiments using an induction motor were performed to verify the validity of the proposed scheme and the simulation model. The proposed algorithm for reducing ripples of phase currents was implemented by TMS320F28335 digital signal processor. Switching frequency is 8kHz, and voltages of upper and lower dclink capacitors, which have 470
μ
F for each one, are measured. To compare the experimental results with simulation results especially phase voltages, a motor with 6 terminals, which can be connected with
Y
or
Δ
connection was used. 4pole 0.75kW induction motor for experiments has rated speed of 1690rpm, and 3.8A/2.2A rated current for 220V/ 380V operation.
Fig. 14
shows experimental result done at 500rpm for (a) without and (b) with the proposed method for
Y
case, respectively. Each figure illustrates
b, c
phase currents (equivalent to line current in
Y
connection) and pole voltage references (
v_{uo}
and
v_{vo}
). Same as the simulation results of
Fig. 9
, it can be seen that the magnitude difference between each phase current is reduced by the proposed method. The distortion of current level is reduced a lot after applying the proposed scheme, and the levels of
a
 and
b
phase voltages, which are around ±50V and ±100V, well agree with the simulation result of
Y
case illustrated in
Fig. 9
.
Experimental result for Yconnected motor: (a) without and (b) with the proposed algorithm operated at 500rpm. From top to bottom phase currents (i_{bs}, i_{cs} 2A/div.), and phase voltages (v_{bs}, v_{cs} 200V/div.).
Fig. 15
shows the experimental waveforms for a
Δ
connected motor rotated at 500rpm (a) without and (b) without the proposed algorithm, respectively. The magnitude of phase current unbalance is bigger than that of
Y
connection.
Fig. 15(b)
demonstrates that after applying the compensation algorithm, the difference between each line current is reduced, and line currents become to have the same peak to peak values. The level of
a
 and
b
phase voltages (
v_{as}, v_{bs}
) coincide with the simulation results as illustrated in
Fig. 10
. Same as the voltage levels summarized in
Table 2
, the experimental results has the voltage levels of ±
V_{dc}
≈±300V, or 0V for
v_{as}
and
v_{bs}
. From
Fig. 14
and
15
, it can be known that experimental results confirm the validity of the analytic model and the proposed scheme.
Experimental result for Δconnected motor: (a) without and (b) with the proposed algorithm operated at 500rpm. From top to bottom line currents (i_{b}, i_{c} 5A/div.), and phase voltages (v_{as}, v_{bs} 350V/div.).
7. Conclusion
In this paper, analytic models made by Matlab/Simulink for FSIdriven
Y
and
Δ
connected motors were presented and the distribution of flux density of motor driven by FSI was illustrated. In addition, the simple current ripple compensation method for FSIs was proposed. In order to do research and/or develop an algorithm for
Y
as well as
Δ
connected motors or loads, an analytic model based on differential equations was developed. The compensation method based on modification of pole voltage references was applied to both connection types and tested. The simulation and experimental results applied in an induction motor with Y or Δconnection have verified the validity of the proposed current ripple reduction method and analytic models. All or portion of the proposed model will contribute to the future research in this field.
Acknowledgements
This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education, Science and Technology(NRF2013R1A1A2007739)
BIO
DongMyung Lee received his B.S. and M.S. in Electrical Engineering from Hanyang University, Seoul, Korea, in 1994 and 1996, respectively, and his Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology, Atlanta, Georgia, USA, in2004. From 1996 to 2000, he worked for LG Electronics Inc., Seoul, Korea. From 2004 to 2007, he was employed by the Samsung SDI R&D Center, Yongin, Korea, as a Senior Engineer. From 2007 to 2008, he was with the Department of Electrical Engineering, Hanyang University, as a Research Professor. Since 2008, he has been an Associate Professor with the School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea. His current research interests include variable speed drives, power quality compensation devices, and power conversion systems for renewable energy sources.
JinWoo Jung received the B.S. and M.S. degrees in Electrical Engineering from Hanyang University, Seoul, Korea in 1991 and 1997, respectively, and the Ph.D. degree in Electrical and Computer Engineering from The Ohio State University, Columbus, Ohio, USA, in 2005. From 1997 to 2000, he was with the Home Appliance Research Laboratory, LG Electronics Co., Ltd., Seoul, Korea. From 2005 to 2008, he was a Senior Research Engineer with the R&D Center and PDP Development Team, Samsung SDI Co., Ltd., Korea. Since 2008, he has been an Associate Professor with the Division of Electronics and Electrical Engineering, Dongguk University, Seoul, Korea. His current research interests include DSPbased electric machine drives, distributed generation systems using renewable energy sources, and power conversion systems and drives for electric vehicles (EVs).
Seo Weon Heo received the B.S. and M.S. degrees in electronic engineering from Seoul National University, Seoul, Korea in 1990 and 1992, respectively, and the Ph.D. degree in electrical engineering from the Purdue University, West Lafayette, Indiana, in 2001. From 1992 to1998, he was with the Digital Media Research Laboratory, LG Electronics Co., Ltd., Korea. From 2001 to 2006, he worked at the Telecommunication R&D Center, Samsung Electronics Co., Ltd., Korea. Since 2006, he has been an Associate Professor with the School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea. His current research interests are in the area of wireless communication, advanced signal processing, and embedded system HW/SW design.
Tae Heoung Kim received his B.S., M.S., and Ph.D. in Electrical Engineering from Hanyang University, Seoul, Korea, in 1993, 1995, and 2005, respectively. From 1995 to 2002, he worked for LG Electronics as a Senior Research Engineer. Since 2005, he has been a Professor in the Department of Electrical Engineering, Gyeongsang National University, Jinju, Korea. His research interests include the design of electric machines and control systems.
Soreshjani M.H.
,
Heidari R.
,
Ghafari A.
2014
“The application of classical Direct Torque and Flux Control (DTFC) for linestart permanent magnet synchronous and its comparison with permanent magnet synchronous motor,”
Journal of Electrical Eng. and Tech.
9
(6)
1954 
1959
DOI : 10.5370/JEET.2014.9.6.1954
Kim T.H.
,
Lee J.
2004
“Influence on brushless DC motor performance due to signal distortion of the position sensor and DC link voltage ripple,”
Inter. Journal of Applied Electro. and Mech.
19
287 
291
Lee D.M.
,
Lee W.C.
2008
“Analysis of relationship between abnormal current and position detection error in sensorless controller for interior permanent magnet BLDC motors,”
IEEE Trans. Magnetics
44
(8)
2074 
2081
DOI : 10.1109/TMAG.2008.923203
Broeck H.
,
Wyk J.
1984
“A comparative investigation of a threephase induction machine with a component minimized voltagefed inverter under different control options,”
IEEE Trans. Industry Appli.
20
(2)
309 
320
Blassbjerg F.
,
Kragh H.
,
Neacsu D.O.
,
Pedersen J.K.
1997
“Comparison of modulation strategies for B4inverters,”
Euro. Power Electr. and Drives Assoc.
2
378 
385
Jacobina C.B.
,
Correa B.R.
1999
“Induction motor drive system for lowpower applications,”
IEEE Trans. Industry Appli.
35
(1)
52 
61
DOI : 10.1109/28.740845
Blaabjerg F.
,
Neacsu D. O.
,
Pederson J. K.
1999
“Adaptive SVM to compensate dclink voltage ripple for fourswitch threephase voltagesource inverter,”
IEEE Trans. Power Elect.
14
(4)
743 
752
Lee D.M.
,
Park J.B.
,
Toliyat H.A.
2013
“A simple current ripple reduction method for B4 inverters,”
Journal of Electrical Eng. and Tech.
8
(5)
1062 
1069
DOI : 10.5370/JEET.2013.8.5.1062
Kim J. H.
,
Hong J. S.
,
Nam K. H.
2009
“A current distortion compensation scheme for fourswitch inverters,”
IEEE Trans. Power Elect.
24
(4)
1032 
1040
DOI : 10.1109/TPEL.2008.2011552
Lee D.M.
2013
“Motor control method for fourswitch inverters with dclink voltage ripple compensation algorithm,”
Journal of Korean Institute of Illum. and Elect. Instal. Engineers
27
(7)
59 
66
Welchko B.A.
,
Lipo T.A.
,
Jahns T.M.
,
Schulz S.E.
2004
“Fault tolerant threephase AC motor drive topologies: a comparison of features, cost, and limitations,”
IEEE Trans. Power Elect.
19
(4)
1108 
1116
DOI : 10.1109/TPEL.2004.830074
Hu Y.
,
Zhang L.
,
Huang W.
,
Bu F.
2010
“A faulttolerantinduction generator system based on instantaneous torque control,”
IEEE Trans. Energy Conv.
25
(2)
412 
421
DOI : 10.1109/TEC.2009.2038898
Hoang K.D.
,
Zhu Z.Q.
,
Foster M.P.
2011
“Influence and compensation of inverter voltage drop in direct torquecontrolled fourswitch threephase PM brushless AC drives,”
IEEE Trans. Power Elect.
26
(8)
2343 
2357
DOI : 10.1109/TPEL.2010.2096561
Dasgupta S.
,
Mohan S.N.
,
Sahoo S.K.
,
Panda S.K.
2013
“Application of fourswitchbased threephase grid connected inverter to connect renewable energy source to a generalized unbalanced microgrid system,”
IEEE Trans. Industrial Elect.
60
(3)
1204 
1215
DOI : 10.1109/TIE.2012.2202350
Ong C.H.
1998
“Dynamic simulation of electric machinery,”
Prentice Hall
New Jersey
224 
229