In this paper, digital peak current mode control for single phase Hbridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cyclebycycle current limitation. Unlike the DCDC converter where the output voltage always remains in the positive region, the output of DCAC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of subharmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constantsloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.
1. Introduction
As the demand for smallscale renewable energy systems is rapidly growing, the need for well regulated power electronic controllers also increases
[1]
. The inverter is an essential component in the system which produces sinusoidal waveforms to supply the ac load or to connect to the grid. The dc/ac single phase inverters are used to interface the power sources with the singlephase grid. The singlephase Hbridge inverter is a simple circuit topology with a small number of components. The inverter is a bidirectional device capable of handling both real and reactive power. Control of the inverter is achieved by varying the turn on time of the upper and lower power switches of each inverter leg. Careful measurements have to be taken not to turn on both the switches in one leg at the same time, to avoid short circuit of the DC supply. The gate driver output should also contain enough dead time to prevent overlapping of conduction periods in each leg.
Current mode control methods have several advantages over voltage mode control methods, such as faster control dynamics, better audiosusceptibility, simple compensation and overcurrent protection
[2

3]
. In case of smallscale inverters, PI controller is one of the most preferred forms of inverter controllers due to its simplicity and well defined design procedures. However, this kind of controller has relatively poor performance due to the steadystate error with tracking the sinusoidal reference. Furthermore, this controller is unable to reject the noise in the current signal due to its poor dynamics. Hysteretic controllers have very fast and stable dynamics, however there would be a high bandwidth of the harmonic spectrum. This makes designing and implementation of the filters a tedious process. Whereas, in peak current mode control, the duty cycle is controlled by comparing the instantaneous peak of the inductor current to the sinusoidal reference in a cyclebycycle basis. Hence, implementing peak current controller is the better option based on control perspective. However, peak current mode controllers have an inherent problem of the presence of subharmonic oscillations
[4

5]
. This problem can be solved by the addition of slope compensation.
So far, most of the implementations of peak current control for DCAC inverters have been exclusively analog in nature. Previous analog implementation has been used for buck converter topology with an unfolding circuit for photovoltaicsourced standalone applications
[6]
. Analog implementation lacks flexibility and durability which can be offered in digital implementation. With radical improvements in the processing speed and cost reduction of digital signal controllers (DSC), digital implementation of control circuits becomes a more practicallyviable option
[7

11]
. For gridconnected singlestage PV inverters, predictive methods of the peak current control have been digitally implemented in a simple manner
[12]
. In the predictive method using one or two samples during each switching cycle, the duty cycle is predicted using the mathematical models of the inverter for unipolar switching. Therefore, a variant of the peak current control with predictive slope compensation is achieved by this method. Systems with predictive methods lack real time cyclebycycle current limitation and also have computational delays which results in degraded audiosusceptibility
[13]
.
To achieve the dynamics of cyclebycycle current limiting for singlephase Hbridge inverter with a digital compensation and peakvalley mode change is the objective of this paper. Using a DSC with very high bandwidth analogtodigital converter (ADC) for high frequency sampling of inductor current is not an efficient method of control. Furthermore, it becomes impossible to achieve this for high frequency applications. A solution using a mixedsignal implementation for DCDC converters has been discussed in
[14].
However, for DC  AC applications, the inverter requires a peaktovalley controlmode transition in every swing cycle. This paper proposes the implementation strategy for DCAC single phase inverters, employing significant improvements by an efficientlyorganizing method. The chosen DSC for this work is TMS320F28335 from Texas Instruments. The device is available to control multiple highfrequency power stages for power electronics industrial applications
[15

18]
.
Section II discusses the operating principles of the newly developed digital peakvalley current mode controller in detail. Section III explains how to analyze and design the digital slope compensation required in order to nullify the oscillations of the peak current mode controller. Section IV describes an adaptive slope compensation for a unipolar switching method of Hbridge inverter. Section V explains the hardware verification followed by conclusion in Section VI.
2. Operating Principle
 2.1 Circuit configuration
The main purpose of the peak current controller is to limit the instantaneous peak of the inductor current according to the given reference in cyclebycycle basis.
Fig. 1
depicts the proposed circuit which includes the power stage and control logic circuit for implementing peakvalley currentmode control of singlephase Hbridge inverter with bipolar switching. In a typical analog controller the inductor current is sensed by a current sensor with gain (R
_{i}
) in
Fig. 1(a)
. In conventional analog controllers, the peak (valley) value of the sensed current signal is detected with respect to the reference signal using a comparator, and then accordingly the duty cycle is changed with the help of the SR flip flop. The current loop becomes an inner loop when multiple feedback control loops are used. Then a compensator present only in the voltage loop known as the outer loop. In order to effectively implement this in the digital mode, the comparator which detects the peak of the sensed current is kept outside the DSC. This is a more efficient method which saves the computing power necessary for the implementation of outer loop and also to control other plants in a multiplant system if necessary. The EPWM2 module in the DSC which provides the PWM signals to the inverter switches is programmed to operate in a cyclebycycle basis and changes the dutycycles based on the trip signal when it goes low.
Peakvalley current mode control circuit of singlephase Hbridge inverter with digital slope compensation.
The distinct challenge for implementing peak current mode control in DCAC inverters is the AC movement of output waveforms in both of the positive and the negative regions. The controller should be able to track the reference perfectly in both regions. To achieve the AC control in positive and negative regions, a novel control circuit has been proposed in this paper. In
Fig. 1
, the sensing signal (I
_{sense}
) with offset is compared with the AC reference (I
_{ref}
) coming from the DSC. The reference is generated by combining the sine reference with slope compensation. The DSC provides the reference in a form of 150 kHz PWM signal (see
Fig. 1(b)
).
The reference signal from the DSC must be converted into an analog signal before connecting it to the comparator. This is achieved by an external 12bit DAC IC chip. The reference signal in the DSC is scaled in a way that the slope compensation ramp at the input of the comparator is active. The reference PWM produced by the DSC ranges from 0 to 3.3V. Therefore, an offset voltage which exactly matches the offset present in the reference is added to the sensed current before comparing it to reference. In addition to the comparator, which serves to detect the peak of the inductor current an XOR gate is inserted between the lines. The purpose of adding XOR logic is to ensure the peak current mode operation during the positive region and the valley current mode operation during the negative region by the trip signal. If peak current mode operation is implemented during both the positive and the negative regions, it will result in an undesirable DC offset in the inductor current. A PWM signal based on the polarity of the reference waveform (‘polarity’ in
Fig. 1
) is connected to the other input of XOR gate, which helps to detect the valley point during the negative region. Cyclebycycle trip action is enabled for the EPWM2 module. Unlike dc/dc converter, the output of the Hbridge inverter swings from positive to negative region continuously. So the trip action is setup in such a way that during the positive region it commands EPWM2A to go low and EPWM2B to go high and viceversa. This ensures peak current limitation occurs during the positive region and valley current limitation occurs during the negative region. In this method of digital implementation, bipolar switching is applied to the single phase HBridge inverter.
3. Slope Compensation
 3.1 Operating principles
In this paper, the peakcurrent mode control modulation strategy is referred as a kind of constantfrequency, trailingedge type modulation.
Fig. 2(a)
and
2(b)
show the sensor outputs compared to the reference signal, with and without slope compensation respectively. As shown in the
Fig. 2(a)
the dotted line is the perturbation given to the instantaneous inductor current waveform. Initially, the inductor current is perturbed by the amount of ΔI
_{0}
and the perturbation amount increases during consecutive switching cycles as denoted by ΔI
_{1}
and ΔI
_{2}
. If no external ramp is added to the reference signal, the current in the circuit will oscillate at half the switching frequency. These oscillations are commonly referred as subharmonic oscillations. These subharmonic oscillations are produced due to the sampleandhold effect inherent with the peak current mode control
[19]
.
Fig. 2(b)
shows the effect of external ramp compensation. With the same amount of initial perturbation ΔI
_{0}
applied to the inductor current, the amount perturbation decreases during consecutive cycles. As in the case of DCDC converters, application of the slope compensation can be used to reduce the sub harmonic oscillations in fullbridge DCAC inverters, as well. When the duty cycle is greater than 0.5, subharmonic oscillations are formed in the DCDC converter circuits. Besides, the inductor current is influenced by the input voltage and the output voltage, which makes the PWM modulator highly nonlinear and hard to model
[20]
. Actually, the previous DCDC criterion for buckconverter is not applicable for HBridge inverter with bipolar switching, because the subharmonics happen throughout the whole cycle, different from a buck converter. The oscillating principle is as follows.
Ontime and offtime slopes of the inductor current waveform: (a) without external slope compensation; (b) with external slope compensation.
As discussed in
[5]
, in the discrete time domain, the equation representing the stability criteria is given by:
When no external ramp is added to the system, it is considered stable if the parameter
α
, which is defined as the ratio of offtime slope (s
_{f}
) to the ontime slope (s
_{n}
), is less than unity. For a bipolarswitching Hbridge inverter, the magnitude of the inductor current slope during ontime (s
_{n}
) is given by:
Similarly, the magnitude of the inductor current slope during offtime (s
_{f}
) is given by:
which is totally different from the equation of the buck.
From the above mentioned equations, it is clear that α is always greater than the unity except during zerocrossing of output voltage. Hence, the slope compensation is an absolute necessity for stable operation in the HBridge inverter with bipolar switching. It is shown that the benefits of peak current mode control are not significantly affected even with application of large external ramps
[4]
.
 3.2 Hbridge inverter slope compensator design
According to the mathematical model developed to analyze the stability of slope compensation in
[6]
, the parameter k which is the ratio of inductor current downslope to the downslope of the current reference for single phase Hbridge inverter is given by
where
and δ is the angle of current reference with slope compensation. The stability criterion in order to make the system unconditionally stable is derived as:
where, θ is angle between inductor current and the horizontal line in the model. Since the output filter inductor is very small, the parameter k must be equal to or greater than 0.5. In order to make the system unconditionally stable the external slope compensation (s
_{e}
) applied must be equal to or greater than half of s
_{f}
[21]
. This can be theoretically verified by plotting the frequency response curve for the current loop gain in HBridge inverter.
Fig. 3
depicts the small signal model for the closedloop currentmode control. Using this model and implementing smallsignal analysis for the HBridge inverter, current loop gain for the system can be derived as follows:
Smallsignal block diagram for the closed current loop.
where
Using statespace averaging technique, the expressions for frequencydomain transfer functions for controltooutput voltage (G
_{vd}
) and controltoinductor current (G
_{id}
) of the Hbridge topology are derived as follows:
In case of constantfrequency, trailingedge modulation, the feedforward gain from the ontime inductor voltage to control (k
_{f}
’) is derived as:
Similarly, the feedforward gain from the offtime voltage across the inductor to control (kr’) is derived as:
From (12) and (13), the feedforward gain from output voltage to control (k
_{r}
) for fullbridge inverter is derived as:
The expression for F
_{m}
is dependent on the currentmode control which is used in the circuit. In case of the constantfrequency, trailing edge modulation is,
From the above equations, the frequency response of current loop gain is plotted as shown in
Fig. 4
. The simulation parameters are the same as those of the hardware prototype used in next section. From the frequency response plot, it is evident that without slope compensation, there is no cross over frequency for current loop gain, therefore resulting in an unstable system. The current loop gain can be reduced with an addition of the external slope compensation in the system. The cross over frequency of the current loop with slope compensation is 3.3 kHz with a good phase margin of 65°.
Fig. 5
shows the frequency response of the current loop gain with the exact model by PSIM. The exact plot with slope compensation exactly matches with the derived average model, therefore it proves the accuracy of the derived average model.
Frequency response of a current loop gain from the averaged analytic model without and with compensation (where s_{e} = s_{f}/2).
Frequency response of a current loop gain with slope compensation from the exact PWM switching model by PSIM.
4. Compensation with Unipolar PWM Switching
 4.1 Hbridge inverter slope compensator design
Unipolar PWM switching method has several inherent advantages compared to the bipolar switching. Apart from the cancellation of even order harmonics in the output, unipolar switching has a unique advantage in peak current mode control with regards to subharmonic oscillation. In case of unipolar switching, the 50% duty cycle criterion is applicable for the presence of subharmonic oscillations. The downslope of inductor current in unipolar PWM switching is given by,
This downslope is similar to buck converter topology. This results in system characteristics similar to the DCDC converters when peak current controller is implemented. This also helps in reduction in the application of external slope compensation, therefore resulting in better loop gain compared to bipolar switching method. Also in unipolar switching method two of the inverter switches operate in line frequency, therefore total switching losses are reduced in the power stage.
In case of unipolar switching method, the top switches in the both legs of the inverter operate in the switching frequency, while the bottom switches operate in fundamental frequency of the output. Hence the PWM strategy used in DSC coding becomes complicated compared to bipolar method. In unipolar method, the tripzone feature is activated only in the top switches of the inverter leg.
Fig. 6
shows the circuit diagram of the twoloop peakcurrent controller (PCC) with a unipolar switching scheme using the DSC. The changes from bipolar switching scheme are evident from the signals given to the switches in the fullbridge circuit. Instead of using just two PWM signals (2A and 2B), three PWM signals (2A, 2B and 3A. 3B is inversion of 3A) are used to control the switches. An outer feedback loop of the load voltage is also realized in the same digital controller. The output of the outer loop PI compensator is merged to the slope compensator to make the inner loop reference.
Fig. 7
shows the simulation file of the singleloop PCC using unipolar switching in PSIM, which differs from the bipolar in terms of the PWM switching signals.
Fig. 8
also shows the simulation results of unipolar implantation. It can be seen that subharmonics does not appear in the region of low dutycycle, but only around the peak, which is a clear difference from the result of the bipolar.
Circuit diagram of twoloop PCC using unipolar switching which includes PWM 3A.
Singleloop PCC circuit diagram using a unipolar switching.
Results for singleloop PCC using unipolar switching without slope compensation, inductor current and the reference (top), PWM switching waveform (bottom).
 4.2 Adaptive slope compensation
As aforementioned, the slope compensation required to remove subharmonic oscillations from the output is greater than the half of the inductor current down slope. From equation (17), it can be seen that the down slope of inductor current is proportional to the output voltage. Therefore, by the feedback of the output voltage through ADC channel, we can calculate the exact value of the down slope of inductor current. This value is used to instantaneously change the compensation of external slope in every switching cycle, based on the output voltage. This method of implementing slope compensation is known as adaptive slope compensation. In case of the unipolar switching scheme, the adaptive slope compensation is preferred to the previous constantslope compensation, because the slope compensation is not necessary in unipolar when the dutycycle is less than 50%. Since the constant slope throughout the full cycle affects the current loopgain of the peak current controller, it would be better to remove or attenuate the compensation whenever it is allowed.
Fig. 9
shows the frequency response of the current loop gain with the adaptive slope compensation versus the unified slope compensation when the output (load) voltage is 10V, around zerocrossing. Unlike the constant slope compensation, the low voltage loopgain is higher than the peak voltage conditions due to the change of the external slope compensation parameter.
Current loop gain with unified and adaptive slope compensation.
Not only the degradation of loop gain, there is a critical reason that the adaptive is preferred. When the constant slope is used in this digital implementation, the external slope compensation near the zero crossing region becomes equal to the downslope of inductor current such as:
Under this condition, the trip signal in the switching cycle stays low and it causes the PWM signals to stay low during the several consecutive cycles. This causes low frequency oscillations near zero crossing regions as shown in
Fig. 10
. From the aforementioned reasons, implementing adaptive slope compensation is one of the optimal solutions for unipolar switching scheme.
Constant slope compensation, Ireference (C1), Ifeedback (C2).
5. Hardware Implementation
The circuit shown in
Fig. 1
was developed and tested for the verification of the analysis. The chosen parameters were Vin =75V, L = 2.8mH, C=10µF, RL=12Ω, Ri = 0.2, Iref = 4A and switching frequency 20 kHz. In order to implement the digital to analog conversion (DAC) for the reference, a 12bit R2R ladder circuit DAC IC AD7247 was used. The output is connected to the comparator where it is compared with the feedback current. The output of the comparator is combined with EPWM3 using an XOR gate. This final signal is connected to the trip zone pin GPIO12 of the DSC. In the EPWM2 module, which drives the switches with 20 kHz PWM, inherent dead time of 2µsec is added between 2A and 2B to prevent the cross conduction.
Fig. 11
shows the hardware prototype used for the experiment along with the DSC.
Singlephase HBridge inverter (top) connected to 200W load along with the DSC (bottom).
Fig. 12
shows the inductor current waveforms with and without slope compensation. The slope compensation reduces the subharmonic oscillations occurring especially during the peak region of inductor current waveform. In
Fig. 13
, the hardware data of the load voltage is collected and FFT analysis is done in MATLAB. The reduction of THDs which is more than 1% with the introduction of slope compensation can be clearly seen in the FFT scope. The presence of the subharmonics in the system is prominent when slope compensation is not used. Slope compensation helps reduce these oscillations in the system and thereby making the system stable.
Fig. 14
shows the reduction of the oscillations due to the introduction of slope compensation. The hardware waveforms were redrawn by MATLAB through the data collections.
Inductor current waveforms without slope (top) and with constant slope compensation (bottom).
FFT scope for load voltage: (a) without slope compensation and (b) with slope compensation.
Inductor current and inverter voltage waveforms: (a) without slope; (b) with constant slope compensation.
The programming efficiency of this method of implementing peak current controller can be known from the execution speed of the DSC code and the remaining part of the DSCs computational part available for other tasks. Using CCS “Profiler” and checking the code in single step, the execution time for the complete ISR was found to be 1450nsec. Hence, only 22% of the high frequency EPWM1 ISR has been utilized in the code. The available computing power can used to implement the outer loop and also to control multiple power plants required especially in standalone renewable energy systems as shown in
[22]
.
Also, the circuit shown in
Fig. 6
was developed and tested for the verification of the analysis.
Fig. 15
shows the reduction in subharmonic oscillations in the inductor current when adaptive slope compensation is applied in unipolar switching scheme.
Fig. 16
is used to show the removal of subharmonic oscillations using adaptive slope compensation. The MATLAB FFT scope shows more than 2% reduction in harmonics around half the switching frequency.
Fig. 17
clearly shows the cyclebycycle variation in the amount of slope compensation in the reference signal. By the comparison of the sawtooth in C1 between the low and high region, the slope of the sawtooth seems to change continuously in every switching cycle.
Inductor current waveforms (top) without slope (bottom) with adaptive slope compensation.
MATLAB FFT scope for inductor current: (a) without slope; (b) with adaptive slope compensation.
Adaptive slope compensation implemented in the reference signal Ireference(C1), Ifeedback (C2), load voltage (C3) and inductor current (C4).
For comparison with a conventional PI controller, an inductor current waveform of a conventional PI controller is shown in
Fig. 18
. The dynamic performance of the PI controller was tested by providing a step change in the load and compared with PCC method. It can be seen that the PI controller takes more time to reach steady state compared to PCC method.
Dynamic comparison between a conventional PI controller and a peakcurrent mode controller (PCC) by a stepchange in load.
In the proposed scheme, when the reference moves from positive region to negative region, the PWM pattern and trip action is modified in the ePWM2 & ePWM3 modules. Because of the delay between the trip action input from the comparator and PWM interrupt during zero crossing region for one switching cycle missmatch occurs between trip action and PWM pattern. This can be solved by either disabling the trip action during zero crossing region using blanking method or implementing PCC in a complete digital loop with very high sampling instead of the proposed mixedsignal scheme. Even though the THDs of the proposed scheme with zero crossing distortion satisfy the desired limit, we have included the result of the elimination of this distortion using blanking method in bipolar switching in
Fig. 19
of the manuscript, as shown below.
Peakcurrent mode controller waveforms eliminating the zerocrossing distortion: (a) inductor current (top); (b) output voltage (bottom).
A rectifier load was added to the hardware prototype which shares 15% of the output power, to test the effectiveness of the proposed scheme under nonlinear load conditions.
Fig. 20
shows the load voltage and the current flowing to the rectifier load. The load voltage is able to track the reference despite the effect of the rectifier load. The MATLAB FFT scope for the obtained load voltage shows THD (4.25%) was within the permissible limits as in
Fig. 21
.
Load voltage(top) and current flowing to the rectifier load(bottom).
MATLAB FFT scope of the load voltage with additional rectifier load.
6. Conclusion
In this paper, a novel cyclebycycle current control method by peakvalley currentmode controller with digital slope compensation has been proposed for an Hbridge inverter. Different from the current control for DCDC, DCAC requires the controlmode transition from peak to valley or vice versa in every swing cycle. The extraordinary operation was efficiently implemented by a single ExclusiveOR gate. From the smallsignal models for feedforward and sampling gain terms of the peak current mode control method, the current loop gain transfer function for the Hbridge inverter has been derived. The frequency response of the derived average model for the current loop gain was found to be in correlation with the exact PWM switching model.
The inherent problem of subharmonics in peak current control has been reduced with the external slope compensation. The effectiveness of the slope compensation has been shown by the reduction in THDs of the load voltage and the stable inductor current waveform. Also, by using the mixed signal comparator and cyclebycycle trip action, the performance of this controller and effective usage of the digital controller has been ensured. The implementation of peak current controller with a unipolar switching scheme was also done with adaptive slope compensation. The digital controller contributes to the instantaneous slope compensation change, and the analysis shows that the adaptive one is more effective to the unipolar switching inverter than the constant slope compensation. Simulation and experimental verification have been done with a 200W hardware prototype of an Hbridge inverter.
Nomenclature
V_{in} Input DC voltage V_{out} Output AC voltage L Output filter inductor C Output filter capacitor R Load resistor R_{i} Current sensing gain s_{n} Inductor current slope during ON time s_{f} Inductor current slope during OFF time s_{e} External ramp slope I_{L} Inductor current I_{ref} Reference current T_{s} Switching period D Duty ratio D’ Complement of duty ratio 1D ∆I_{0,1,2} Inductor current perturbation (initial or 1st or 2nd) F_{m} Duty ratio modulator gain k_{f}’ Feedforward gain from ontime voltage to control k_{r}’ Feedforward gain from offtime voltage to control k_{r} Feedforward gain from output voltage to control H_{e} Equivalent samplinggain in current feedback TBCTR TimeBase Counter TBPRD TimeBase Period ISR Interrupt Service Routine
Acknowledgements
This work was supported by the Human Resources Development program(No. 20144030200600) of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korea government Ministry of Trade, Industry and Energy.
BIO
Mohana Sundar Manoharan received his B.S. from the Department of Electrical Engineering of Kalasalingam University, India, in 2011. He received his M.S degree in 2013 and is currently working towards his Ph.D. degree at Soongsil University, Seoul, Korea. His current research interests include the analysis and design of Power Conditioning Systems using Multilevel Inverter.
Ashraf Ahmed received his B.Sc. and M.Sc. degrees in Electrical Engineering from Assiut UniversityEgypt, Cairo UniversityEgypt in 1999 and 2005, respectively. He received his Ph.D. degree from University of DurhamUK in 2011, in the field of renewable energy control and power electronics. He is currently an Assistant Professor at Soongsil University, Seoul, Korea and a researcher in the Desert Research Center, Cairo, Egypt. His research interests include the analysis and design of switching power converters for renewable energy applications.
JoungHu Park received his B.S., M.S. and Ph.D. from the Department of Electrical Engineering and Computer Science of Seoul National University, Seoul, Korea, in 1999, 2001 and 2006, respectively. He is currently an Assistant Professor at Soongsil University, Seoul, Korea. His current research interests include the analysis of highfrequency switching converters and renewable energy applications, etc.
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