Advanced
Improved KY Converter
Improved KY Converter
Journal of Electrical Engineering and Technology. 2015. Jul, 10(4): 1578-1588
Copyright © 2015, The Korean Institute of Electrical Engineers
This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
  • Received : October 07, 2014
  • Accepted : February 16, 2015
  • Published : July 01, 2015
Download
PDF
e-PUB
PubReader
PPT
Export by style
Article
Author
Metrics
Cited by
TagCloud
About the Authors
K. I. Hwu
Corresponding Author: Dept. of Electrical Engineering, National Taipei University of Technology, Taiwan. (eaglehwu@ntut.edu.tw)
W. Z. Jiang
Dept. of Electrical Engineering, National Taipei University of Technology, Taiwan. (newjerusalem333@gmail.com,t9318083@ ntut.edu.tw)
H. M. Chen
Dept. of Electrical Engineering, National Taipei University of Technology, Taiwan. (newjerusalem333@gmail.com,t9318083@ ntut.edu.tw)

Abstract
In this paper, an improved KY converter is presented, which is constructed mainly by one charge pump capacitor and one central-tapped coupling inductor. Besides, a passive clamping snubber is added to this converter to improve the efficiency above half load. As compared to the KY converter, the voltage conversion ratio of the proposed converter is upgraded significantly. In this paper, the basic operating principles and mathematical deductions of the proposed converter are described, along with some experimental results provided to demonstrate the feasibility and effectiveness of the proposed converter.
Keywords
1. Introduction
Because of the global warming, the demand of the green power has been increasing for decades. These kinds of green power facilities include solar cells, fuel cells, etc. In many applications, high voltage conversion converters play an important role in boosting the low output voltages of green power facilities to the high voltages which the loads need. Regarding the traditional non-isolated voltage-boosting converters [1 , 2] , such as the traditional boost converter and buck-boost converter, their voltage gains are not high enough. Up to now, many kinds of voltage-boosting techniques have been presented, including several inductors which are magnetized and then pump the stored energy into the output with all inductors connected in series [3] , coupled inductors with turns ratios [4 - 8 , 10 , 11 , 15 , 19] , voltage superposition based on switching capacitors [9 , 13 - 20] , auxiliary transformers with turns ratios [12] , etc. In [8] and [10] , the output terminal is floating, thereby increasing application complexity. In [4 - 11 , 16 , 17 , 19] and [20] , these converters contain too many components, thereby making the converters relatively complicated.
Based on the mentioned above, a novel step-up converter is presented, which is based on charge pump capacitor and one central-tap coupling inductor so as to improve the voltage conversion ratio of the KY converter. In this converter, a passive clamping snubber is used to decrease the voltage spike on the switch, and hence the switch with low turn-on resistance can be used. In this paper, the basic operating principles and the mathematical deductions will be described and some experimental results are provided to verify the effectiveness of the proposed topology.
2. Overall System Configuration
Fig. 1 shows the proposed high step-up converter. This converter is constructed by three switches S 1 , S 2 and S 3 along with the corresponding body diodes D 1 , D 2 and D 3 , one output diode Do , one charge pump diode Db , one charge pump capacitor Cb , one output capacitor Co , one central-tapped coupling inductor established by one primary self-inductance Lp and one secondary self-inductance Ls , and one output load resistor Ro .
PPT Slide
Lager Image
Proposed high step-up converter.
3. Basic Operating Principles
Prior to this topic, there are some assumptions and symbols to be given:
  • (1) The voltage across the charge pump capacitorCbis equal to the input voltageVi.
  • (2) The value of the output capacitorCois larger enough to keep the output voltage constantVoat some value.
  • (3) The input current is signified byii, the current inCbis denoted byib, the current inLpis represented byiLp, the current inLsis indicated byiLs, and the current inCois described byiCo.
  • (4) The flux in the central-tapped coupling inductor is represented byφ.
  • (5) The primary-side and secondary-side turns are signified byNpandNs, respectively, andnis defined to beNsoverNp.
  • (6) The gate driving signals forS1,S2andS3arevgs1,vgs2andvgs3, respectively.
  • (7) The switching period isTs. The blanking times betweenS1andS2are negligible.
  • (8) As the converter operates in the continuous conduction mode (CCM) and the boundary conduction mode (BCM), the turn-on interval forS1andS3isDTs, whereas the turn-on interval forS2is (1 −D)Ts.
  • (9) As the converter operates in the discontinuous conduction mode (DCM), the time required byLporLsto release the stored energy to zero is denoted by Δ1Ts, and the time interval without any current inLporLsis indicated by Δ2Ts, equal to (1 −D)Ts−Δ1Ts.
  • (10) All components, including the switches, diodes, capacitors and central-tapped coupling inductor, are considered to be ideal.
Figs. 2 and 3 show the key waveforms for the converter operating in CCM and DCM, respectively.
PPT Slide
Lager Image
Illustrated waveforms for the converter operating in CCM.
PPT Slide
Lager Image
Illustrated waveforms for the converter operating in DCM.
- 3.1 Equivalent coupling inductor parameters
In the proposed converter, the currents in Lp and Ls , ip and is , are pulsating for any operating mode, due to the discontinuity in ip and is . Accordingly, for analysis convenience, some modifications to the parameters and currents of the coupling inductor are presented. First of all, let Lp be L 1 , and then during the turn-off period of S 3 , let the equivalent inductance L 2 be Lp plus Ls , as shown in Fig. 4 . Therefore,
PPT Slide
Lager Image
PPT Slide
Lager Image
Equivalent inductance L2 equal to Lp plus Ls during the turn-off period.
It is noted that how to determine which mode operates in is based on the flux in the central-tapped coupling inductor, φ , or based on Np , Ns , ip and is . Also, it is noted that the turns ratio n is equal to Ns divided by Np . Accordingly, the following equations can be obtained :
PPT Slide
Lager Image
where ℜ is the flux resistance of the core.
Based on the above mention, as shown in Fig. 5 , if the number of turns during the magnetizing and demagnetizing periods is Np , then the continuous current i L1 can be obtained. Likewise, if the number of turns during the magnetizing and demagnetizing periods is Np plus Ns , then the continuous current i L2 can be obtained. The following equations show the results:
PPT Slide
Lager Image
PPT Slide
Lager Image
Relationship between iL1, iL2 and iLp: (a) CCM; (b) DCM.
From (2) and (3), the relationship between iLp , i L1 and i L2 can be expressed to be
PPT Slide
Lager Image
In addition, in Fig. 5 , I L1 and I L2 are the average currents of i L1 and i L2 , respectively.
And, the relationship between i L1 and i L2 , and the relationship between I L1 and I L2 can be represented by
PPT Slide
Lager Image
- 3.2 Steady-state analysis
After the above modifications mentioned in Sec. 3.1, the steady-state analysis, based on the small ripple approximation, follows.
- 3.2.1 State 1 (t0
As shown in Fig. 6 , S 1 and S 3 are turned on but S 2 is turned off. During this interval, Db and Do are reverse-biased. At the same time, the voltage across Lp is the input voltage plus the voltage across Cb , namely, 2 Vi , thereby causing Lp to be magnetized. Also, the energy required by the output is provided by Co . Therefore, the corresponding equations can be obtained to be
PPT Slide
Lager Image
PPT Slide
Lager Image
Current flow for mode 1.
- 3.2.2 State 2 (t1
As shown in Fig. 7 , S 1 and S 3 are turned off but S 2 is turned on. During this interval, Db and Do are forward-biased. At the same time, the voltage across L 2 is the input voltage minus the output voltage, namely, Vi Vo . Hence, the voltage across Lp is equal to Vi minus Vo divided by ( n +1), thereby causing Lp to be demagnetized. Also, the energy required by the output is provided by the central-tapped coupling inductor which releases the stored energy. Therefore, the corresponding equations can be obtained based on the small ripple approximation to be
PPT Slide
Lager Image
PPT Slide
Lager Image
Current flow for mode 2.
By applying the voltage-second balance to Lp , one can obtain
PPT Slide
Lager Image
Rearranging (8) yields the voltage conversion ratio:
PPT Slide
Lager Image
Applying the current-second balance to Co , one can obtain
PPT Slide
Lager Image
Rearranging (10) yields the expression of I L2 :
PPT Slide
Lager Image
Via (9) under the same duty cycle, it is noted that in Fig. 8 , the proposed high step-up converter with a turns ratio set to one has a higher voltage conversion ratio than the other two, the traditional boost converter and the KY converter.
PPT Slide
Lager Image
Voltage conversion ratio comparison of three types of converters.
- 3.3 Boundary conduction mode condition
Fig. 9 shows the key waveforms for the converter operating in the boundary conduction mode (BCM). For this mode, the average current flowing through L 2 , ILB , can be expressed to be
PPT Slide
Lager Image
PPT Slide
Lager Image
Inductor current waveforms in BCM.
From state 2 mentioned in Sec. 3.2, since the current in L 2 , i L2 , corresponds to the current flowing through Lp plus Ls during the turn-off period of S 1 , the half value of i L2,peak , Δ i L2 , can be expressed to be
PPT Slide
Lager Image
where i L2, peak is the peak-to-peak value of i L2 under BCM.
Substituting (1) into (13) yields
PPT Slide
Lager Image
If ILB is equal to than Δ i L2 , then the converter operates in BCM. Accordingly, the following equation can be obtained to be
PPT Slide
Lager Image
Let
PPT Slide
Lager Image
Substituting (16) into (15), (15) can be rewritten to be
PPT Slide
Lager Image
Based on (17), if K < Kcrit ( D ) , then the converter will operate in DCM; if K > Kcrit ( D ) , then the converter will operate in CCM. Fig. 10 shows the boundary condition of the proposed converter with turns ratio n equal to one.
PPT Slide
Lager Image
Boundary condition of the proposed converter with turns ratio n equal to one.
- 3.4 Passive clamping snubber
As generally recognized, the central-tapped coupling inductor inherently has the leakage inductance LLK , since the coupling coefficient is not equal to one. Therefore, the voltage spike will be imposed on the switch. In the case, a passive clamping snubber, composed of one snubber diode Dsn and one snubber capacitor Csn , is used herein to suppress such a voltage spike. Fig. 11 shows the proposed converter with this passive clamping snubber. There are two operating states for the passive clamping snubber, to be described briefly as follows.
PPT Slide
Lager Image
Proposed converter with a passive clamping snubber.
- 3.4.1 State 1
As S 3 is turned off, the energy stored in LLK forces Dsn and Do to be turned on, as shown in Fig. 11 . At the same time, Csn is charged. As soon as the energy stored is released entirely, the operating state goes to state 2.
PPT Slide
Lager Image
Current flow of the passive clamping snubber in state 1.
- 3.4.2 State 2
As Dsn is turned off and Do is turned on, Csn is discharged as shown in Fig. 13 . As soon as the voltage across Csn , vCsn , is reduced to the minimum value, vCsn,min , which is equal to
PPT Slide
Lager Image
Dsn is turned on, and this state comes to the end.
PPT Slide
Lager Image
Current flow of the passive clamping snubber in state 2.
Fig. 14 shows the overall system configuration of the proposed converter. The feedback control loop contains one voltage divider, one analog-to-digital converter (ADC), one FPGA which is the control kernel, and three gate drivers. Besides, the gate driving signals M 1 , M 2 and M 3 are created by FPGA and used to drive the switches S 1 , S 2 and S 3 , respectively, after gate drivers.
PPT Slide
Lager Image
Overall system configuration.
Prior to designing the main power stage in Fig. 14 , there are some specifications to be given as follows: (i) the input voltage Vi is 5V; (ii) the output voltage Vo is 48V; (iii) the rated output current Io,rated is 1A; (iv) the minimum output current Io,min is 0.15A, which makes the converter operate in BCM; (v) the switching frequency fs is 50kHz; and (vi) the turns ratio is five.
- 3.5 Design of coupling inductor
According to the above specifications, the calculated duty cycle D can be obtained to be 0.417 as follows:
PPT Slide
Lager Image
From the mention at the end of Sec. 3.3, if the converter operates in CCM above the minimum output current Io,min , the primary-side inductance of the coupling inductor Lp must satisfy the following inequality:
PPT Slide
Lager Image
Substituting the given specifications into (19), the value of Lp is calculated to be larger than 27.06μH:
PPT Slide
Lager Image
Finally, the value of Lp is chosen to be about 30μH. At the same time, the value of the secondary-side inductance Ls is calculated to be 750μH, as shown in the following equation:
PPT Slide
Lager Image
Eventually, one PTS40/27/I 3C92 core, made by Ferroxcube Co., is chosen for the coupling inductor.
- 3.6 Design of charge pump capacitor
According to the basic formula for the capacitor, the relationship between voltage ripple and capacitance during the discharge interval Δ t can be expressed to be
PPT Slide
Lager Image
where Δ vCb is the voltage ripple on Cb and iCb is the current flowing through Cb .
Under the rated conditions, the average current during the turn-on period, ICb,DTs is equal to I L1,rated , namely
PPT Slide
Lager Image
where Δ v Cb,max is the maximum value of Δ vCb .
If Δ v Cb, max is smaller than 3% of Vi , then the inequality of the value of Cb can be obtained as follows:
PPT Slide
Lager Image
Eventually, one 680μF Rubycon capacitor is chosen for Cb .
- 3.7 Design of output capacitor
By the same way mentioned in Sec. 3.6, under the rated conditions, the average current during the turn-on period, I Co,DTs is equal to Io , namely
PPT Slide
Lager Image
where Δ v Co,max is the maximum value of Δ vCo .
If Δ v Co,max is smaller than 0.2% of Vi , then the inequality of the value of Co can be obtained as follows:
PPT Slide
Lager Image
Finally, one 1000μF Rubycon capacitor is chosen for Co .
- 3.8 Design of Csnin passive snubber
Prior to taking up this section, the primary-side leakage inductance LLK must be figured out first, the data shown in Table 1 is obtained based on a LCR meter, and hence the coupling coefficient of the primary side to the secondary side, kps , can be obtained to be
PPT Slide
Lager Image
Measurements of the central-tapped coupling inductor
PPT Slide
Lager Image
Measurements of the central-tapped coupling inductor
By the similar way, the coupling coefficient of the secondary side to the primary side, ksp can be obtained:
PPT Slide
Lager Image
Hence, the coupling coefficient of the central-tapped coupling inductor, k , can be calculated out to be
PPT Slide
Lager Image
Accordingly, the primary-side leakage inductance LLK can be worked out to be
PPT Slide
Lager Image
Sequentially, the value of the snubber capacitor Csn will be calculated out in the following. Under the condition that the converter operates at rated load, as soon as S 1 is turned off, the energy stored in LLK can be expressed to be
PPT Slide
Lager Image
where
PPT Slide
Lager Image
Based on the (31) and (32), the value of ELK is 8.19μJ .
Since ELK is to be released to Csn from the minimum voltage across Csn , v Csn,min , to the maximum voltage across Csn , v Csn,max , ELK also can be expressed to be
PPT Slide
Lager Image
Also,
PPT Slide
Lager Image
Assuming that v Csn,max is smaller than 20V, substituting the calculated values of ELK and v Csn,max into (33), the inequality of the value of Csn can be obtained as follows:
PPT Slide
Lager Image
Finally, one 68nF ceramic capacitor is chosen for Csn .
4. Experimental Results
At light load, Fig. 15 shows the gate driving signals v gs1 , v gs2 and v gs3 for S 1 , S 2 and S 3 , respectively, and the voltage across Cb , vCb ; Fig, 16 shows the gate driving signals v gs1 and v gs2 for S 1 and S 2 , respectively, the current through Lp , iLp , and the current through Ls , iLs ; Fig. 17 shows the gate driving signals v gs1 and v gs2 for S 1 and S 2 , respectively, the voltage across S 3 , and the voltage across Dsn . At half load, Figs. 18 to 20 show the same measured items as Figs. 15 to 17 ; at rated load, Figs. 21 to 23 show the same measured items as Figs. 15 to 17 . In addition, Fig. 24 shows the curves of efficiency versus load current, with and without a passive snubber.
PPT Slide
Lager Image
Measured waveforms at light load: (1) vgs1; (2) vgs2; (3) vgs3; (4) vCb.
PPT Slide
Lager Image
Measured waveforms at light load: (1) vgs1; (2) vgs2; (3) iLp; (4) iLs.
PPT Slide
Lager Image
Measured waveforms at light load: (1) vgs1; (2) vgs2; (3) vds3; (4) vDsn.
PPT Slide
Lager Image
Measured waveforms at half load: (1) vgs1; (2) vgs2; (3) vgs3; (4) vCb.
PPT Slide
Lager Image
Measured waveforms at half load: (1) vgs1; (2) vgs2; (3) iLp; (4) iLs.
PPT Slide
Lager Image
Measured waveforms at half load: (1) vgs1; (2) vgs2; (3) vds3; (4) vDsn.
PPT Slide
Lager Image
Measured waveforms at rated load: (1) vgs1; (2) vgs2; (3) vgs3; (4) vCb.
PPT Slide
Lager Image
Measured waveforms at rated load: (1) vgs1; (2) vgs2; (3) iLp; (4) iLs.
PPT Slide
Lager Image
Measured waveforms at rated load: (1) vgs1; (2) vgs2; (3) vds3; (4) vDsn.
PPT Slide
Lager Image
Efficiency versus load.
From Figs. 15 , 18 and 21 , it can be seen that the voltages across the energy-transferring capacitor Cb are kept near at 5V. The differences between them are due to the voltage drops of parasitic components. From Figs. 16 , 19 and 22 , it can be seen that the more the load is, the higher the currents iLp and iLs . From Figs. 17 , 20 and 23 , it can be seen that the more the load is, the higher the voltage spike, particularly at rated load, up to 20V. From Fig. 24 , it can be seen that the efficiency is above 90.38% all over the load range and can be up to 92.29%. Besides, the efficiency below the load current of 0.4A, the converter with the passive snubber has lower efficiency than the converter without the passive snubber. This is because the former has additional conduction loss due to the diode Dsn . However, as the load is from light load to rated load, the former has better performance of efficiency than the latter. This is because the voltage stress in the former is lower than that in the latter. Hence, the turn-on resistance of the switch S 3 of the former is lower than that of the latter, implying that the former has lower conduction loss than the latter.
5. Conclusion
A novel step-up converter is presented herein, which is based on coupling inductor and one central-tap coupling inductor so as to improve the voltage conversion ratio of the KY converter. In the proposed converter, a passive clamping snubber is used to decrease the voltage spike on the switch so as to increase the efficiency of this converter above half load. Besides, such a converter is simple in structure and easy to control, and hence suitable for industrial applications.
Appendix
Table 2 makes a comparison between some converters shown in the references in terms of voltage conversion ratio, component number, and switch voltage stress. From this table, it can be seen that the proposed converter a relatively good voltage conversion ratio with a reasonable component number and acceptable switch voltage stresses.
Comparison between the proposed converter and the converters shown in the References, in terms of voltage conversion ratio, component number, switch voltage stress, output inductor and floating output
PPT Slide
Lager Image
Comparison between the proposed converter and the converters shown in the References, in terms of voltage conversion ratio, component number, switch voltage stress, output inductor and floating output
Nomenclature
S1, S2, S3 Switches Db Charge pump diode D1, D2, D3 Body diodes for S1, S2, S3 Do Output diode Dsn Snubber diode Lp Primary self-inductance Ls Secondary self-inductance L1 Inductance equal to Lp L2 Inductance equal to Lp plus Ls LLK Leakage inductance Cb Charge pump capacitor Co Output capacitor Csn Snubber capacitor Ro Output load resistor Np Primary turns Ns Secondary turns n Turns ratio equal to Ns /Np Vi Input voltage Vo Output voltage vds3 Voltage across S3 vDsn Voltage across Dsn vgs1, vgs2, vgs3 Gate-source signals for S1, S2, S3 vCsn,max Maximum voltage across Csn vCsn,min Minimum voltage across Csn ΔvCb Voltage ripple on Cb ΔvCb,max Maximum value of ΔvCb ΔvCo Voltage ripple on Co ΔvCo,max Maximum value of ΔvCo iL1 Current flowing through L1 iL2 Current flowing through L2 iL2,peak Peak-to-peak value of iL2 under BCM iLK Current in LLK ΔiL2 Current ripple in L2 ILB Average current in Lp under BCM Io,rated Rated output current Io,min Minimum output current ICb,DTs Average value of iCb during the turn-on period ICo,DTs Average value of iCo during the turn-on period IL1 Average current in L1 IL2 Average current in L2 ILp,max Maximum value of iLp IL1,max Maximum value of iL1 IL2,max Maximum value of iL2 Ts Switching period D Duty cycle φ Flux in the central-tapped coupling inductor Flux resistance of the core fs Switching frequency Lp_s-short Primary inductance with secondary side shorted Ls_p-short Secondary inductance with primary side shorted Kps Coupling coefficient with primary side referred to secondary side Ksp Coupling coefficient with secondary side referred to primary side K Geometric average value of Kps and Ksp ELK Energy stored in LLK M1, M2, M3 Gate driving signals for S1, S2, S3 Ro,max Maximum value of output load resistor
BIO
K. I. Hwu He was born in Taichung, Taiwan, on August 24, 1965. He received the B.S. and Ph.D. degrees in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1995 and 2001, respectively. From 2001 to 2002, he was the Team Leader of the Voltage-Regulated Module (VRM) at AcBel Company. From 2002 to 2004, he was a Researcher at the Energy and Resources Laboratories, Industrial Technology Research Institute. He is currently a Professor at the Institute of Electrical Engineering, National Taipei University of Technology, Taipei, Taiwan, where he was the Chairman of the Center for Power Electronics Technology from 2005 to 2006. His current research interests include power electronics, converter topology, and digital control. Dr. Hwu has been a member of the Program Committee of the IEEE Applied Power Electronics Conference and Exposition since 2005. He has also been a member of the Technical Review Committee of the Bureau of Standards, Metrology, and Inspection since 2005. Since 2008, he has been a member of the IET.
W. Z. Jiang He was born in Changhua, Taiwan, on May 09, 1989. He received the B.S. and M.S. degrees in electrical engineering from National Taipei University of Technology, Taipei, Taiwan, in 2011 and 2013, respectively. Currently, he is working toward the Ph.D. degree at the same university. His fields of research interests include power electronics, converter topology, and digital control.
H. M. Chen He received the M.S degree in electrical engineering from National Taipei University of Technology, Taipei, Taiwan. His research interest is power electronics.
References
Erickson R. W. , Maksimovic D. 2001 “Fundamentals of Power Electronics,” 2nd ed. KLuwer Academic Publishers Norwell
Pressman Abrahan I. 1998 “Switching Power Supply Design,” 2nd ed. McGraw-Hill New York
Lin B. R. , Hsieh F. Y. , Chen J. J. 2008 “Analysis and implementation of a bidirectional converter with high converter ratio,” IEEE ICIT’08 1 - 6
Park K. B. , Moon G. W. , Youn M. J. 2011 “Non-isolated high step-up stacked converter based on boostintegrated isolated converter,” IEEE Transactions on Power Electronics 26 (2) 577 - 587    DOI : 10.1109/TPEL.2010.2066578
Deng Y. , Rong Q. , Zhao Y. , Shi J. , He X. 2012 “Single switch high step-up converters with built-in transformer voltage multiplier cell,” IEEE Transactions on Power Electronics 27 (8) 3557 - 3567    DOI : 10.1109/TPEL.2012.2183620
Li Wuhua , Li Weichen , He Xiangning , Xu D. , Wu Bin 2012 “General derivation law of nonisolated high-step-up interleaved converters with built-in transformer,” IEEE Transactions on Industrial Electronics 59 (3) 1650 - 1661    DOI : 10.1109/TIE.2011.2163375
Lai C. M. , Pan C. T. , Cheng M. C. 2012 “High-efficiency modular high step-up interleaved boost converter for dc-microgrid applications,” IEEE Transactions on Industrial Electronics 48 (1) 161 - 171
Wai R. J. , Duan R. Y. 2005 “High-efficiency power conversion for low power fuel cell generation system,” IEEE Transactions on Power Electronics 20 (4) 847 - 856    DOI : 10.1109/TPEL.2005.850936
Luo F. L. 2008 “Analysis of super-lift luo-converters with capacitor voltage drop,” IEEE ICIEA’ 08 417 - 422
Yang L. S. , Liang T. J. , Lee H. C. , Chen J. F. 2011 “Novel high step-up DC-DC converter with coupled-inductor and voltage-doubler circuits,” IEEE Transactions on Industrial Electronics 58 (9) 4196 - 4206
Pan C. T. , Lai C. M. 2010 “A high-efficiency high step-up converter with low switch voltage stress for fuel-cell system applications,” IEEE Transactions on Industrial Electronics 57 (6) 1998 - 2006    DOI : 10.1109/TIE.2009.2024100
Hwu K. I. , Yau Y. T. 2009 “KY converter and its derivatives,” IEEE Transactions on Power Electronics 57 (6) 128 - 137
Hwu K. I. , Yau Y. T. 2010 “A KY boost converter,” IEEE Transactions on Power Electronics 25 (11) 2699 - 2703    DOI : 10.1109/TPEL.2010.2051235
Hwu K. I. , Huang K. W. , Tu W. C. 2011 “Step-up converter combining KY and buck-boost converters,” IET Electronics Letters 47 (12) 722 - 724    DOI : 10.1049/el.2011.0392
Hwu K. I. , Yau Y. T. 2010 “Inductor-coupled KY boost converter,” IET Electronics Letters 46 (24) 1624 - 1626    DOI : 10.1049/el.2010.2400
Hwu K.I. , Tu W.C. 2012 “Voltage-boosting converters with energy pumping,” IET Power Electronics 5 (2) 185 - 195    DOI : 10.1049/iet-pel.2011.0076
Hwu K.I. , Yau Y.T. , Chen Y.H. 2008 “A novel voltageboosting converter with passive voltage clamping,” IEEE ICSET’08 351 - 354
Hwu K. I. , Yau Y. T. 2009 “Two types of KY buckboost converters,” IEEE Transactions on Industrial Electronics 56 (8) 2970 - 2980    DOI : 10.1109/TIE.2009.2023100
Hwu K. I. , Yau Y. T. 2010 “Voltage-boosting converter based on charge pump and coupling inductor with passive voltage clamping,” IEEE Transactions on Industrial Electronics 57 (7) 1719 - 1727
Hwu K.I. , Tu W.C. , Shieh J.J. 2011 “A novel voltageboosting converter based on charge pump and one inductor inserted,” IEEE PEDS’11 492 - 495