As shown in
Fig. 7
,
S
_{1}
and
S
_{3}
are turned off but
S
_{2}
is turned on. During this interval,
D_{b}
and
D_{o}
are forward-biased. At the same time, the voltage across
L
_{2}
is the input voltage minus the output voltage, namely,
V_{i}
−
V_{o}
. Hence, the voltage across
L_{p}
is equal to
V_{i}
minus
V_{o}
divided by (
n
+1), thereby causing
L_{p}
to be demagnetized. Also, the energy required by the output is provided by the central-tapped coupling inductor which releases the stored energy. Therefore, the corresponding equations can be obtained based on the small ripple approximation to be
Current flow for mode 2.
By applying the voltage-second balance to
L_{p}
, one can obtain
Rearranging (8) yields the voltage conversion ratio:
Applying the current-second balance to
C_{o}
, one can obtain
Rearranging (10) yields the expression of
I
_{L2}
:
Via (9) under the same duty cycle, it is noted that in
Fig. 8
, the proposed high step-up converter with a turns ratio set to one has a higher voltage conversion ratio than the other two, the traditional boost converter and the KY converter.
Voltage conversion ratio comparison of three types of converters.
- 3.3 Boundary conduction mode condition
Fig. 9
shows the key waveforms for the converter operating in the boundary conduction mode (BCM). For this mode, the average current flowing through
L
_{2}
,
I_{LB}
, can be expressed to be
Inductor current waveforms in BCM.
From state 2 mentioned in Sec. 3.2, since the current in
L
_{2}
,
i
_{L2}
, corresponds to the current flowing through
L_{p}
plus
L_{s}
during the turn-off period of S
_{1}
, the half value of
i
_{L2,peak}
, Δ
i
_{L2}
, can be expressed to be
where
i
_{L2, peak}
is the peak-to-peak value of
i
_{L2}
under BCM.
Substituting (1) into (13) yields
If
I_{LB}
is equal to than Δ
i
_{L2}
, then the converter operates in BCM. Accordingly, the following equation can be obtained to be
Let
Substituting (16) into (15), (15) can be rewritten to be
Based on (17), if
K
<
K_{crit}
(
D
) , then the converter will operate in DCM; if
K
>
K_{crit}
(
D
) , then the converter will operate in CCM.
Fig. 10
shows the boundary condition of the proposed converter with turns ratio
n
equal to one.
Boundary condition of the proposed converter with turns ratio n equal to one.
- 3.4 Passive clamping snubber
As generally recognized, the central-tapped coupling inductor inherently has the leakage inductance
L_{LK}
, since the coupling coefficient is not equal to one. Therefore, the voltage spike will be imposed on the switch. In the case, a passive clamping snubber, composed of one snubber diode
D_{sn}
and one snubber capacitor
C_{sn}
, is used herein to suppress such a voltage spike.
Fig. 11
shows the proposed converter with this passive clamping snubber. There are two operating states for the passive clamping snubber, to be described briefly as follows.
Proposed converter with a passive clamping snubber.
- 3.4.1 State 1
As
S
_{3}
is turned off, the energy stored in
L_{LK}
forces
D_{sn}
and
D_{o}
to be turned on, as shown in
Fig. 11
. At the same time,
C_{sn}
is charged. As soon as the energy stored is released entirely, the operating state goes to state 2.
Current flow of the passive clamping snubber in state 1.
- 3.4.2 State 2
As
D_{sn}
is turned off and
D_{o}
is turned on,
C_{sn}
is discharged as shown in
Fig. 13
. As soon as the voltage across
C_{sn}
,
v_{Csn}
, is reduced to the minimum value,
v_{Csn,min}
, which is equal to
D_{sn}
is turned on, and this state comes to the end.
Current flow of the passive clamping snubber in state 2.
Fig. 14
shows the overall system configuration of the proposed converter. The feedback control loop contains one voltage divider, one analog-to-digital converter (ADC), one FPGA which is the control kernel, and three gate drivers. Besides, the gate driving signals
M
_{1}
,
M
_{2}
and
M
_{3}
are created by FPGA and used to drive the switches
S
_{1}
,
S
_{2}
and
S
_{3}
, respectively, after gate drivers.
Overall system configuration.
Prior to designing the main power stage in
Fig. 14
, there are some specifications to be given as follows: (i) the input voltage
V_{i}
is 5V; (ii) the output voltage
V_{o}
is 48V; (iii) the rated output current
I_{o,rated}
is 1A; (iv) the minimum output current
I_{o,min}
is 0.15A, which makes the converter operate in BCM; (v) the switching frequency
f_{s}
is 50kHz; and (vi) the turns ratio is five.
- 3.5 Design of coupling inductor
According to the above specifications, the calculated duty cycle
D
can be obtained to be 0.417 as follows:
From the mention at the end of Sec. 3.3, if the converter operates in CCM above the minimum output current
I_{o,min}
, the primary-side inductance of the coupling inductor
L_{p}
must satisfy the following inequality:
Substituting the given specifications into (19), the value of
L_{p}
is calculated to be larger than 27.06μH:
Finally, the value of
L_{p}
is chosen to be about 30μH. At the same time, the value of the secondary-side inductance
L_{s}
is calculated to be 750μH, as shown in the following equation:
Eventually, one PTS40/27/I 3C92 core, made by Ferroxcube Co., is chosen for the coupling inductor.
- 3.6 Design of charge pump capacitor
According to the basic formula for the capacitor, the relationship between voltage ripple and capacitance during the discharge interval Δ
t
can be expressed to be
where Δ
v_{Cb}
is the voltage ripple on
C_{b}
and
i_{Cb}
is the current flowing through
C_{b}
.
Under the rated conditions, the average current during the turn-on period,
I_{Cb,DTs}
is equal to
I
_{L1,rated}
, namely
where Δ
v
_{Cb,max}
is the maximum value of Δ
v_{Cb}
.
If Δ
v
_{Cb, max}
is smaller than 3% of
V_{i}
, then the inequality of the value of
C_{b}
can be obtained as follows:
Eventually, one 680μF Rubycon capacitor is chosen for
C_{b}
.
- 3.7 Design of output capacitor
By the same way mentioned in Sec. 3.6, under the rated conditions, the average current during the turn-on period,
I
_{Co,DTs}
is equal to
I_{o}
, namely
where Δ
v
_{Co,max}
is the maximum value of Δ
v_{Co}
.
If Δ
v
_{Co,max}
is smaller than 0.2% of
Vi
, then the inequality of the value of
C_{o}
can be obtained as follows:
Finally, one 1000μF Rubycon capacitor is chosen for
C_{o}
.
- 3.8 Design of Csnin passive snubber
Prior to taking up this section, the primary-side leakage inductance
L_{LK}
must be figured out first, the data shown in
Table 1
is obtained based on a LCR meter, and hence the coupling coefficient of the primary side to the secondary side,
k_{ps}
, can be obtained to be
Measurements of the central-tapped coupling inductor
Measurements of the central-tapped coupling inductor
By the similar way, the coupling coefficient of the secondary side to the primary side,
k_{sp}
can be obtained:
Hence, the coupling coefficient of the central-tapped coupling inductor,
k
, can be calculated out to be
Accordingly, the primary-side leakage inductance
L_{LK}
can be worked out to be
Sequentially, the value of the snubber capacitor
C_{sn}
will be calculated out in the following. Under the condition that the converter operates at rated load, as soon as
S
_{1}
is turned off, the energy stored in
L_{LK}
can be expressed to be
where
Based on the (31) and (32), the value of
E_{LK}
is 8.19μJ .
Since
E_{LK}
is to be released to Csn from the minimum voltage across
C_{sn}
,
v
_{Csn,min}
, to the maximum voltage across
C_{sn}
,
v
_{Csn,max}
,
E_{LK}
also can be expressed to be
Also,
Assuming that
v
_{Csn,max}
is smaller than 20V, substituting the calculated values of
E_{LK}
and
v
_{Csn,max}
into (33), the inequality of the value of
C_{sn}
can be obtained as follows:
Finally, one 68nF ceramic capacitor is chosen for
C_{sn}
.
4. Experimental Results
At light load,
Fig. 15
shows the gate driving signals
v
_{gs1}
,
v
_{gs2}
and
v
_{gs3}
for
S
_{1}
,
S
_{2}
and
S
_{3}
, respectively, and the voltage across
C_{b}
,
v_{Cb}
;
Fig, 16
shows the gate driving signals
v
_{gs1}
and
v
_{gs2}
for
S
_{1}
and
S
_{2}
, respectively, the current through
L_{p}
,
i_{Lp}
, and the current through
L_{s}
,
i_{Ls}
;
Fig. 17
shows the gate driving signals
v
_{gs1}
and
v
_{gs2}
for
S
_{1}
and
S
_{2}
, respectively, the voltage across
S
_{3}
, and the voltage across
D_{sn}
. At half load,
Figs. 18
to
20
show the same measured items as
Figs. 15
to
17
; at rated load,
Figs. 21
to
23
show the same measured items as
Figs. 15
to
17
. In addition,
Fig. 24
shows the curves of efficiency versus load current, with and without a passive snubber.
Measured waveforms at light load: (1) v_{gs1}; (2) v_{gs2}; (3) v_{gs3}; (4) v_{Cb}.
Measured waveforms at light load: (1) v_{gs1}; (2) v_{gs2}; (3) i_{Lp}; (4) i_{Ls}.
Measured waveforms at light load: (1) v_{gs1}; (2) v_{gs2}; (3) v_{ds3}; (4) v_{Dsn}.
Measured waveforms at half load: (1) v_{gs1}; (2) v_{gs2}; (3) v_{gs3}; (4) v_{Cb}.
Measured waveforms at half load: (1) v_{gs1}; (2) v_{gs2}; (3) i_{Lp}; (4) i_{Ls}.
Measured waveforms at half load: (1) v_{gs1}; (2) v_{gs2}; (3) v_{ds3}; (4) v_{Dsn}.
Measured waveforms at rated load: (1) v_{gs1}; (2) v_{gs2}; (3) v_{gs3}; (4) v_{Cb}.
Measured waveforms at rated load: (1) v_{gs1}; (2) v_{gs2}; (3) i_{Lp}; (4) i_{Ls}.
Measured waveforms at rated load: (1) v_{gs1}; (2) v_{gs2}; (3) v_{ds3}; (4) v_{Dsn}.
Efficiency versus load.
From
Figs. 15
,
18
and
21
, it can be seen that the voltages across the energy-transferring capacitor
C_{b}
are kept near at 5V. The differences between them are due to the voltage drops of parasitic components. From
Figs. 16
,
19
and
22
, it can be seen that the more the load is, the higher the currents
i_{Lp}
and
i_{Ls}
. From
Figs. 17
,
20
and
23
, it can be seen that the more the load is, the higher the voltage spike, particularly at rated load, up to 20V. From
Fig. 24
, it can be seen that the efficiency is above 90.38% all over the load range and can be up to 92.29%. Besides, the efficiency below the load current of 0.4A, the converter with the passive snubber has lower efficiency than the converter without the passive snubber. This is because the former has additional conduction loss due to the diode
D_{sn}
. However, as the load is from light load to rated load, the former has better performance of efficiency than the latter. This is because the voltage stress in the former is lower than that in the latter. Hence, the turn-on resistance of the switch
S
_{3}
of the former is lower than that of the latter, implying that the former has lower conduction loss than the latter.
5. Conclusion
A novel step-up converter is presented herein, which is based on coupling inductor and one central-tap coupling inductor so as to improve the voltage conversion ratio of the KY converter. In the proposed converter, a passive clamping snubber is used to decrease the voltage spike on the switch so as to increase the efficiency of this converter above half load. Besides, such a converter is simple in structure and easy to control, and hence suitable for industrial applications.
Appendix
Table 2
makes a comparison between some converters shown in the references in terms of voltage conversion ratio, component number, and switch voltage stress. From this table, it can be seen that the proposed converter a relatively good voltage conversion ratio with a reasonable component number and acceptable switch voltage stresses.
Comparison between the proposed converter and the converters shown in the References, in terms of voltage conversion ratio, component number, switch voltage stress, output inductor and floating output
Comparison between the proposed converter and the converters shown in the References, in terms of voltage conversion ratio, component number, switch voltage stress, output inductor and floating output
Nomenclature
S_{1}, S_{2}, S_{3} Switches D_{b} Charge pump diode D_{1}, D_{2}, D_{3} Body diodes for S_{1}, S_{2}, S_{3} D_{o} Output diode D_{sn} Snubber diode L_{p} Primary self-inductance L_{s} Secondary self-inductance L_{1} Inductance equal to L_{p} L_{2} Inductance equal to L_{p} plus L_{s} L_{LK} Leakage inductance C_{b} Charge pump capacitor C_{o} Output capacitor C_{sn} Snubber capacitor R_{o} Output load resistor N_{p} Primary turns N_{s} Secondary turns n Turns ratio equal to N_{s} /N_{p} V_{i} Input voltage V_{o} Output voltage v_{ds3} Voltage across S_{3} v_{Dsn} Voltage across D_{sn} v_{gs1}, v_{gs2}, v_{gs3} Gate-source signals for S_{1}, S_{2}, S_{3} v_{Csn,max} Maximum voltage across C_{sn} v_{Csn,min} Minimum voltage across C_{sn} Δv_{Cb} Voltage ripple on C_{b} Δv_{Cb,max} Maximum value of Δv_{Cb} Δv_{Co} Voltage ripple on C_{o} Δv_{Co,max} Maximum value of Δv_{Co} i_{L1} Current flowing through L_{1} i_{L2} Current flowing through L_{2} i_{L2,peak} Peak-to-peak value of i_{L2} under BCM i_{LK} Current in L_{LK} Δi_{L2} Current ripple in L_{2} I_{LB} Average current in L_{p} under BCM I_{o,rated} Rated output current I_{o,min} Minimum output current I_{Cb,DTs} Average value of i_{Cb} during the turn-on period I_{Co,DTs} Average value of i_{Co} during the turn-on period I_{L1} Average current in L_{1} I_{L2} Average current in L_{2} I_{Lp,max} Maximum value of i_{Lp} I_{L1,max} Maximum value of i_{L1} I_{L2,max} Maximum value of i_{L2} T_{s} Switching period D Duty cycle φ Flux in the central-tapped coupling inductor ℜ Flux resistance of the core f_{s} Switching frequency L_{p_s-short} Primary inductance with secondary side shorted L_{s_p-short} Secondary inductance with primary side shorted K_{ps} Coupling coefficient with primary side referred to secondary side K_{sp} Coupling coefficient with secondary side referred to primary side K Geometric average value of K_{ps} and K_{sp} E_{LK} Energy stored in L_{LK} M_{1}, M_{2}, M_{3} Gate driving signals for S_{1}, S_{2}, S_{3} R_{o,max} Maximum value of output load resistor
BIO
K. I. Hwu He was born in Taichung, Taiwan, on August 24, 1965. He received the B.S. and Ph.D. degrees in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1995 and 2001, respectively. From 2001 to 2002, he was the Team Leader of the Voltage-Regulated Module (VRM) at AcBel Company. From 2002 to 2004, he was a Researcher at the Energy and Resources Laboratories, Industrial Technology Research Institute. He is currently a Professor at the Institute of Electrical Engineering, National Taipei University of Technology, Taipei, Taiwan, where he was the Chairman of the Center for Power Electronics Technology from 2005 to 2006. His current research interests include power electronics, converter topology, and digital control. Dr. Hwu has been a member of the Program Committee of the IEEE Applied Power Electronics Conference and Exposition since 2005. He has also been a member of the Technical Review Committee of the Bureau of Standards, Metrology, and Inspection since 2005. Since 2008, he has been a member of the IET.
W. Z. Jiang He was born in Changhua, Taiwan, on May 09, 1989. He received the B.S. and M.S. degrees in electrical engineering from National Taipei University of Technology, Taipei, Taiwan, in 2011 and 2013, respectively. Currently, he is working toward the Ph.D. degree at the same university. His fields of research interests include power electronics, converter topology, and digital control.
H. M. Chen He received the M.S degree in electrical engineering from National Taipei University of Technology, Taipei, Taiwan. His research interest is power electronics.
Erickson R. W.
,
Maksimovic D.
2001
“Fundamentals of Power Electronics,”
2nd ed.
KLuwer Academic Publishers
Norwell
Pressman Abrahan I.
1998
“Switching Power Supply Design,”
2nd ed.
McGraw-Hill
New York
Lin B. R.
,
Hsieh F. Y.
,
Chen J. J.
2008
“Analysis and implementation of a bidirectional converter with high converter ratio,”
IEEE ICIT’08
1 -
6
Park K. B.
,
Moon G. W.
,
Youn M. J.
2011
“Non-isolated high step-up stacked converter based on boostintegrated isolated converter,”
IEEE Transactions on Power Electronics
26
(2)
577 -
587
DOI : 10.1109/TPEL.2010.2066578
Deng Y.
,
Rong Q.
,
Zhao Y.
,
Shi J.
,
He X.
2012
“Single switch high step-up converters with built-in transformer voltage multiplier cell,”
IEEE Transactions on Power Electronics
27
(8)
3557 -
3567
DOI : 10.1109/TPEL.2012.2183620
Li Wuhua
,
Li Weichen
,
He Xiangning
,
Xu D.
,
Wu Bin
2012
“General derivation law of nonisolated high-step-up interleaved converters with built-in transformer,”
IEEE Transactions on Industrial Electronics
59
(3)
1650 -
1661
DOI : 10.1109/TIE.2011.2163375
Lai C. M.
,
Pan C. T.
,
Cheng M. C.
2012
“High-efficiency modular high step-up interleaved boost converter for dc-microgrid applications,”
IEEE Transactions on Industrial Electronics
48
(1)
161 -
171
Wai R. J.
,
Duan R. Y.
2005
“High-efficiency power conversion for low power fuel cell generation system,”
IEEE Transactions on Power Electronics
20
(4)
847 -
856
DOI : 10.1109/TPEL.2005.850936
Luo F. L.
2008
“Analysis of super-lift luo-converters with capacitor voltage drop,”
IEEE ICIEA’ 08
417 -
422
Yang L. S.
,
Liang T. J.
,
Lee H. C.
,
Chen J. F.
2011
“Novel high step-up DC-DC converter with coupled-inductor and voltage-doubler circuits,”
IEEE Transactions on Industrial Electronics
58
(9)
4196 -
4206
Pan C. T.
,
Lai C. M.
2010
“A high-efficiency high step-up converter with low switch voltage stress for fuel-cell system applications,”
IEEE Transactions on Industrial Electronics
57
(6)
1998 -
2006
DOI : 10.1109/TIE.2009.2024100
Hwu K. I.
,
Yau Y. T.
2009
“KY converter and its derivatives,”
IEEE Transactions on Power Electronics
57
(6)
128 -
137
Hwu K. I.
,
Huang K. W.
,
Tu W. C.
2011
“Step-up converter combining KY and buck-boost converters,”
IET Electronics Letters
47
(12)
722 -
724
DOI : 10.1049/el.2011.0392
Hwu K. I.
,
Yau Y. T.
2010
“Inductor-coupled KY boost converter,”
IET Electronics Letters
46
(24)
1624 -
1626
DOI : 10.1049/el.2010.2400
Hwu K.I.
,
Yau Y.T.
,
Chen Y.H.
2008
“A novel voltageboosting converter with passive voltage clamping,”
IEEE ICSET’08
351 -
354
Hwu K. I.
,
Yau Y. T.
2009
“Two types of KY buckboost converters,”
IEEE Transactions on Industrial Electronics
56
(8)
2970 -
2980
DOI : 10.1109/TIE.2009.2023100
Hwu K. I.
,
Yau Y. T.
2010
“Voltage-boosting converter based on charge pump and coupling inductor with passive voltage clamping,”
IEEE Transactions on Industrial Electronics
57
(7)
1719 -
1727
Hwu K.I.
,
Tu W.C.
,
Shieh J.J.
2011
“A novel voltageboosting converter based on charge pump and one inductor inserted,”
IEEE PEDS’11
492 -
495