Advanced
High Step-Up Converter with Hybrid Structure Based on One Switch
High Step-Up Converter with Hybrid Structure Based on One Switch
Journal of Electrical Engineering and Technology. 2015. Jul, 10(4): 1566-1577
Copyright © 2015, The Korean Institute of Electrical Engineers
This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
  • Received : October 07, 2014
  • Accepted : February 16, 2015
  • Published : July 01, 2015
Download
PDF
e-PUB
PubReader
PPT
Export by style
Article
Author
Metrics
Cited by
TagCloud
About the Authors
K. I. Hwu
Corresponding Author: Dept. of Electrical Engineering, National Taipei University of Technology, Taiwan. (eaglehwu@ntut.edu.tw)
T. J. Peng
Dept. of Electrical Engineering, National Taipei University of Technology, Taiwan. (Hunter_Peng@chiconypower.com.tw)

Abstract
A novel high step-up converter is presented herein, which combines the conventional buck-boost converter, the charge pump capacitor and the coupling inductor. By doing so, a quite high voltage conversion ratio due to not only the turns ratio but also the duty cycle, so as to increase design feasibility. It is noted that the denominator of the voltage conversion ratio is the square of one minus duty cycle. Above all, there is no voltage spike across the switch due to the leakage inductance and hence no passive or active snubber is needed, and furthermore, the used switch is driven without isolation and hence the gate driving circuit is relatively simple, thereby upgrading the industrial application capability of this converter. In this paper, the basic operating principles and the associated mathematical deductions are firstly described in detail, and finally some experimental results are provided to demonstrate the effectiveness of the proposed high step-up converter.
Keywords
1. Introduction
As generally recognized, the boost converter is widely used in the renewable energy system, in the standby power source, in the car power source, in the 3C (Computer, Communication, Consumer-Electronics) product, etc. The purpose of the boost converter is used to transfer the low voltage level to the stable high voltage level, so as to stabilize the overall system. Therefore, the traditional boost converter is used as a power stage, which boosts the input voltage to a 400V dc voltage to feed the standby power source, or to generate a grid-connected 220V ac voltage via the DC-AC inverter. However, the traditional boost converter has the voltage conversion ratio about four. This is because the non-ideal properties due to parasitic components make the voltage conversion ratio deteriorated [1 , 2] .
Consequently, many kinds of voltage-boosting techniques have been presented, including several inductors which are magnetized and then pump the stored energy into the output with all inductors connected in series [3] , coupled inductors with turns ratios [4 - 8 , 9 , 10 , 14 , 18 , 19] , voltage superposition based on switching capacitors [12 - 17] , auxiliary transformers with turns ratios [11] , etc. In [8] and [9] , the output terminal is floating, thereby increasing application complexity. In [6 , 7] and [10] , these converters contain too many components, thereby making the converters relatively complicated. In [3 - 10 , 14 - 16 , 18] and [19] , the output currents are pulsating, thus causing the output voltage ripples to tend to be large. In [11 - 13] and [17] , even though the output currents are non-pulsating, their voltage conversion ratios are not high enough.
Therefore, a novel high step-up converter is presented herein, which combines the traditional buck-boost converter, the charge pump and the coupling inductor. This converter possesses relatively high voltage conversion ratio, the designer can use the turns ratio to vary the voltage conversion ratio so as to make the circuit design relatively elastic. Above all, the used power switch is not floating, so as to make the gate driving circuit quite simple. Furthermore, there is no voltage spike across the switch due to the leakage inductance. In this paper, the basic operating principles and the associated mathematical deductions are firstly depicted in detail, and eventually some experimental results are provided to verify the effectiveness of the proposed high step-up converter.
2. Overall System Configuration
Fig. 1 shows the proposed high step-up converter, which is constructed by the traditional buck-boost converter, and the coupling inductor and charge pump capacitor circuit. The traditional buck-boost converter contains one switch S 1 , two diodes D 1 and D 4 , one inductor L 1 , and one energy-transferring capacitor C 1 . The coupling inductor and charge pump capacitor circuit contains one switch S 1 , three diodes D 2 , D 3 and D 4 , one charge pump capacitor C 2 , one output capacitor Co , and one coupling inductor with turns ratio of N 1 : N 2 , where N 1 and N 2 are the primary-side turns and the secondary-side turns, respectively. It is noted that the coupling inductor is built up by one magnetizing inductor Lm and one ideal transformer.
PPT Slide
Lager Image
Proposed high step-up converter with variables added.
3. Basic Operating Principles
Prior to taking up this section, there are some assumptions and symbols to be given as follows in Fig. 1 : (i) the coupling coefficient k is equal to one, that is, the primary and secondary leakage inductances are negligible; (ii) the dc input and output voltages are defined to be Vi and Vo , respectively; (iii) the dc input and output currents are signified by Ii and Io , respectively; (iv) the current in S 1 is indicated by i DS1 ; (v) the currents in D 1 , D 2 , D 3 and D 4 are denoted by i D1 , i D2 , i D3 and i D4 , respectively; (vi) the values of C 1 and C 2 are large enough to keep the voltages across themselves constant at some values, equal to V C1 and V C2 , respectively; (vii) the current flowing through L 1 is expressed by i L1 ; (viii) the currents in the N 1 and N 2 windings are signified by i 1 and i 2 , respectively; (ix) the current in Lm is indicated by iLm ; (x) i 3 is the sum of i 1 and im ; (xi) the gate driving signal for S 1 is denoted by v gs1 ; (xii) the voltages on S 1 is represented by v DS1 ; (xiii) the voltage across L 1 is expressed by v L1 ; (xiv) the voltage across Lm or the voltage across the N 1 winding is expressed by v N1 ; (xv) the voltage on the N 2 winding indicated by v N2 ; (xvi) the turns ratio of n is equal to N 2 / N 1 ; and (xvii) the duty cycle D is the quiescent dc duty cycle created from the controller.
- 3.1 CCM Operation
Since the converter operates in the continuous conduction mode (CCM), there are two operating states with the illustrated waveforms as shown in Fig. 2 .
PPT Slide
Lager Image
Illustrated waveforms related to the proposed converter.
- 3.1.1 State 1 (t0≤t≤t1)
As shown in Fig. 3(a) , S 1 is turned on. Hence, the voltage across L 1 is equal to Vi , thereby causing L 1 to be magnetized. At the same time, D 1 and D 3 are turned off, but D 2 and D 4 are turned on. Accordingly, the voltage across Lm , v N1 , is equal to the input voltage Vi plus the voltage across C 1 , V C1 , thereby causing Lm to be magnetized. In addition, C 2 is charged by Vi + V C1 + v N2 . Therefore,
PPT Slide
Lager Image
PPT Slide
Lager Image
Current flows in: (a) state 1; (b) state 2.
- 3.1.2 State 2 (t1≤t≤t0+Ts)
As shown in Fig. 3(b) , S 1 is turned off. Hence, D 2 and D 4 are turned off, but D 1 and D 3 are turned on. At the same time, the voltage across L 1 , v L1 , is equal to − V C1 , thereby causing L 1 to be demagnetized and to energize the output, whereas the voltage across Lm , v N1 , is equal to Vi + V C1 + V C2 v N2 Vo , thereby causing Lm to be demagnetized. Therefore,
PPT Slide
Lager Image
Since the turns ratio n is equal to N 2 / N 1 , (2) can be rewritten to be
PPT Slide
Lager Image
Applying the voltage-second balance to L 1 , we can obtain the following equation:
PPT Slide
Lager Image
Eq. (4) can be rewritten to be
PPT Slide
Lager Image
By applying the voltage-second balance to Lm , we can obtain the following equation:
PPT Slide
Lager Image
where
PPT Slide
Lager Image
Substituting (5) and (7) into (6) yields the voltage conversion ratio of the proposed high step-up converter:
PPT Slide
Lager Image
- 3.2 Comparison of flyback, forward and proposed converters
As generally acknowledged, the duty cycle of the flyback converter does not approach to one due to the parasitic parameters of components, whereas the duty cycle of the forward converter also does not approach to one due to a suitable time slot needed to reset the magnetizing inductance. Based on the aforementioned, the comparison in voltage conversion ratio between the flyback converter, the forward converter and the proposed converter is under the condition that each converter operates in the continuous conduction mode (CCM) with the turns ratio set to 3 and the duty cycle set at 0.75. Therefore, the voltage conversion ratios for the flyback converter, the forward converter and the proposed converter are 2.25, 9, and 68, respectively. That is, the proposed converter has a quite high voltage conversion ratio as compared with the flyback converter and forward converter.
- 3.3 CCM with leakage inductance considered
By considering the leakage inductance Llk as shown in Fig. 4 , in state 1, the corresponding equation of v N1 expressed by (1) will be modified to
PPT Slide
Lager Image
Proposed high step-up converter with leakage inductance considered.
PPT Slide
Lager Image
where k = Lm / ( Lm + Llk ).
And, in state 2, the corresponding equation of v N1 will be modified to
PPT Slide
Lager Image
By applying the voltage balance to the magnetizing inductor based on (9) and (10), the resulting voltage conversion ratio can be obtained to be
PPT Slide
Lager Image
From (11), as the value of k is close to one, the voltage conversion ratio is retrieved to (8).
- 3.3 BCM operation
Since there are two inductors L 1 and Lm in the proposed high step-up converter, the corresponding boundary conduction mode (BCM) conditions will be discussed in the following, so as to make design of L 1 and Lm relatively easy. It is assumed that there is no power loss, i.e., the input power is equal to the output power.
- 3.3.1 BCM Condition forL1
Based on (8), the dc input current Ii can be expressed as
PPT Slide
Lager Image
where
PPT Slide
Lager Image
Substituting (10) into (9) yields
PPT Slide
Lager Image
Since the dc current in L 1 , I L1 , is equal to Ii , (11) can be rewritten to be
PPT Slide
Lager Image
Also, the current ripple of i L1 , denoted by Δ i L1 , can be expressed to be
PPT Slide
Lager Image
Hence, the condition for L 1 operating in BCM is
PPT Slide
Lager Image
where
PPT Slide
Lager Image
and
PPT Slide
Lager Image
Thus, if K 1 is larger than K crit1 ( D ), then L 1 operates in CCM; if K 1 is smaller than K crit1 ( D ), then L 1 operates in DCM.
- 3.3.2 BCM Condition forLm
The dc portion of the current in the magnetizing inductor Lm , denoted by ILm , can be represented by
PPT Slide
Lager Image
Substituting (10) into (17) yields
PPT Slide
Lager Image
Also, the current ripple of iLm , denoted by Δ iLm , can be expressed to be
PPT Slide
Lager Image
Substituting (5) into (19) yields
PPT Slide
Lager Image
Hence, the condition for Lm operating in BCM is
PPT Slide
Lager Image
PPT Slide
Lager Image
PPT Slide
Lager Image
Accordingly, K 2 is larger than K crit2 ( D ), then Lm operates in CCM; if K 2 is smaller than K crit1 ( D ), then Lm operates in DCM.
3. Design Considerations
Prior to taking up this section, there are some system specifications and key components to be given as follows: (i) the range of the dc input voltage Vi is from 20V to 28V with 24V rated; (ii) the rated dc output voltage Vo is 400V; (iii) the rated dc output power Po,rated is 200W, i.e., the rated dc output current Io,rated is 0.5A; (iv) the minimum dc output power Po,min is 40W, i.e., the minimum dc output current Io,min is 0.1A; (v) the switching frequency fs is 50kHz, i.e., the switching period Ts is 20μs; and (vi) the product name of the control IC is MC34060A. It is noted that the proposed converter operates in CCM above the minimum dc output current. In addition, Tables 1 and 2 show the voltage and current stresses of the switch and diodes, and the specifications for the components used in the main power stage of the proposed converter.
Voltage and current stresses of the switch and diodes
PPT Slide
Lager Image
Voltage and current stresses of the switch and diodes
Components used in the main power stage of the proposed converter
PPT Slide
Lager Image
Components used in the main power stage of the proposed converter
Sequentially, the energy-storing components, such as L 1 , Lm , C 1 , C 2 and Co , are taken into account, under the condition that the converter operates in CCM and the turns ratio of the coupling inductor, n , is set to one.
- 4.1 Design ofL1
Fig. 5(a) shows the waveforms related to L 1 .In addition, (8) can be rewritten to be
PPT Slide
Lager Image
PPT Slide
Lager Image
Waveforms related to: (a) L1; (b) Lm.
From (24), the duty cycle D can be obtained as
PPT Slide
Lager Image
Therefore, according to (25), the minimum duty cycle Dmin occurs at the maximum dc input voltage Vi,max , and the maximum duty cycle Dmax occurs at the minimum dc input voltage Vi,min .
Sequentially, based on Fig. 5(a) , Δ i L1 can be expressed to be
PPT Slide
Lager Image
Therefore, the maximum value of Δ i L1 , signified by Δ i L1, max , can be expressed to be
PPT Slide
Lager Image
In order to make sure that L 1 operates in CCM, the following inequality must be obeyed:
PPT Slide
Lager Image
where I L1,min is the minimum dc current in L 1 .
Also, if the efficiency of the overall system is assumed to be equal to 100%, then the following equation can be obtained to be
PPT Slide
Lager Image
Based on (27) to (29), the inequality for L 1 can be obtained to be
PPT Slide
Lager Image
Therefore, the value of L 1 is larger than 115.4μH so as to make sure that L 1 operates in CCM. Furthermore, considering the efficiency performance, the higher the value of L 1 is, the smaller the peak current in L 1 and hence the lower the conduction loss and core loss. Eventually, the value of L 1 is chosen to be 225μH, which is about double the calculated value. Also, the core, named CC4220/JPP44A, is selected to construct L 1 along with the corresponding turns of 38 and the required air-gap of 1.622mm.
- 4.2 Design ofLm
Fig. 5(b) shows the waveforms related to Lm . In addition, Δ iLm can be expressed as
PPT Slide
Lager Image
According to (5) and (31) can be rewritten as
PPT Slide
Lager Image
Therefore, it can be seen that the maximum value of Δ iLm , signified by Δ iLm,max , can be expressed to be
PPT Slide
Lager Image
In order to make sure that Lm operates in CCM, the following equation must be obeyed:
PPT Slide
Lager Image
where ILm,min is the minimum dc current in Lm and can be expressed to be
PPT Slide
Lager Image
Based on (33) to (35), the inequality for Lm can be obtained as
PPT Slide
Lager Image
Hence, the value of Lm is larger than 824.6μH, so as to make sure that Lm operates in CCM. Furthermore, considering the limitation of winding area, the value of Lm is chosen to be 900μH, which is about 1.1 times of the calculated value. Also, the core, named CC4220/JPP44A, is selected to construct Lm along with the corresponding N 1 turns of 48 and the required air-gap of 0.628mm. In addition, since n is set at one, the corresponding N 2 turns are also 48.
- 4.3 Design ofC1
From Fig. 6(a) , the voltage ripple on C 1 , called Δ v C1 , is composed of the voltage ripple Δ v C1_ESR created from the current flowing through the equivalent series resistor ESR C1 , and the voltage ripple Δ v C1_cap created from the charging and discharging of C 1 Therefore, Δ v C1 can be expressed to be
PPT Slide
Lager Image
Also, Δ v C1_ESR can be represented by
PPT Slide
Lager Image
where
PPT Slide
Lager Image
where tan δ C1 is the dissipation factor of C 1 .
In addition, Δ v C1_cap can be signified by
PPT Slide
Lager Image
where i C1_(1−D) is the current flowing through C 1 during the turn-off period.
By assuming the value of Δ v C1 is set at 1% of the rated dc output voltage Vo , substituting (8), (38), (39) and (40) into (37) yields the following rearranged equation:
PPT Slide
Lager Image
Based on (25) and (41), the minimum value of C 1 occurs under the conditions of the rated dc output power and the minimum dc input voltage. In addition, under the given switching period Ts , the value of 1 tan δ C1 is about 13.13 based on the datasheet of Rubycon ZLH series capacitors. Hence, the minimum value of C 1 can be calculated to be 1563μF as follows:
PPT Slide
Lager Image
Finally, one 2200μF Rubycon capacitor is chosen for C 1 .
- 4.4 Design of C2
From Fig. 6(b) , the voltage ripple on C 2 , called Δ v C2 , is composed of the voltage ripple Δ v C2_ESR created from the current flowing through the equivalent series resistor ESR C2 , and the voltage ripple Δ v C2_cap created from the charging and discharging of C 2 . Therefore, Δ v C2 can be expressed to be
PPT Slide
Lager Image
PPT Slide
Lager Image
Waveforms pertaining to: (a) C1; (b) C2; (c) Co.
Also, Δ v C2_ESR can be represented by
PPT Slide
Lager Image
where
PPT Slide
Lager Image
where tan δ C2 is the dissipation factor of C 2 .
Moreover, Δ v C2_cap can be signified by
PPT Slide
Lager Image
where i C2 _(1−D) is the current flowing through C 2 during the turn-off period.
By assuming that the value of Δ v C2 is set at 0.5% of the rated dc output voltage Vo , substituting (8), (44), (45) and (46) into (43) yields the following rearranged equation:
PPT Slide
Lager Image
Based on (25) and (47), the minimum value of C 2 occurs under the conditions of the rated dc output power and the minimum dc input voltage. In addition, under the given switching period Ts , the value of tan δ C2 is about 6.22 based on the datasheet of Nichicon CS series capacitors. Hence, the minimum value of C 2 can be worked out to be 92.3μF as follows:
PPT Slide
Lager Image
Eventually, one 220μF Nichicon capacitor is selected for C 2 .
- 4.5 Design of Co
From Fig. 6(c) , the voltage ripple on Co , called Δ vo , is composed of the voltage ripple Δ vCo_ESR created from the current flowing through the equivalent series resistor ESRCo , and the voltage ripple Δ vCo_cap created from the charging and discharging of Co . Therefore, Δ vo can be expressed to be
PPT Slide
Lager Image
Also, Δ v C2_ESR can be represented by
PPT Slide
Lager Image
where
PPT Slide
Lager Image
where tan δCo is the dissipation factor of Co .
Besides, Δ v Co_cap can be signified by
PPT Slide
Lager Image
where i Co_(D) is the current flowing through Co during the turn-on period.
By assuming that the value of Δ vo is set at 0.1% of the rated output voltage Vo , substituting (8), (50), (51) and (52) into (49) yields the following rearranged equation:
PPT Slide
Lager Image
Based on (25) and (53), the minimum value of Co occurs under the conditions of the rated dc power and the minimum dc input voltage. In addition, under the given switching period Ts , the value of tan δCo is about 14.14 based on the datasheet of Rubycon CXW series capacitors. Hence, the minimum value of Co can be figured out to be 180.9μF as follows:
PPT Slide
Lager Image
At last, two 150μF Rubycon capacitors, one 0.33μF plastic capacitor and one 22nF plastic capacitor are chosen for Co and paralleled together.
- 4.6 Switch utilization
Like the traditional boost converter, the higher the voltage conversion ratio is, the lower the switch utilization SU [2] , which is defined to be
PPT Slide
Lager Image
where
PPT Slide
Lager Image
PPT Slide
Lager Image
PPT Slide
Lager Image
Therefore, based on (55), the switch utilization of the proposed converter is about 0.032. This value is quite low due to the corresponding voltage conversion ratio is ultra high, about 20.
5. Experimental Results
On the one hand, Fig. 7 shows the waveforms relevant to the input voltage of 24V at rated load. Fig. 7 depicts the gate driving signal for S 1 , v gs1 , and the current in L 1 , i L1 ; Fig. 8 shows the gate driving signal for S 1 , v gs1 , the current i 3 with the sum of the current in N 1 , i 1 , and the current in Lm , iLm , and the current in N 2 , i 2 ; Fig. 9 depicts the gate driving signal for S 1 , v gs1 , the current in D 4 , i D4 , and the current in S 1 , i DS1 ; Fig. 10 shows the gate driving signal for S 1 , v gs1 , and the voltages on C 1 and C 2 , v C1 and v C2 ; Fig. 11 depicts the gate driving signal for S 1 , v gs1 , and the output voltage ripple Δ vo ; Fig. 12 shows the gate driving signal for S 1 , v gs1 , and the voltage on S 1 , v DS1 . From these figures, it can be seen that the proposed converter can operate well to some extent and the output voltage ripple is about 360mV, i.e., 0.09% of Vo , smaller than 0.1% of Vo . Furthermore, it can be seen that from Fig. 12 , the voltage across S 1 has no voltage spike.
PPT Slide
Lager Image
Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) iL1.
PPT Slide
Lager Image
Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) i3; (3) i2.
PPT Slide
Lager Image
Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) iD4; (3) iDS1.
PPT Slide
Lager Image
Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) vC1; (3) vC2.
PPT Slide
Lager Image
Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) Δvo .
PPT Slide
Lager Image
Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) vDS1.
The following is used to further explain the current spikes on i 2 and i 3 shown in Fig. 8 . Since the proposed converter operates in CCM, the reverse recovery currents created from the diodes are indispensible. Aside from this, in order to reduce the primary and secondary leakage inductances, the bifilar winding technique is adopted, thereby causing the equivalent parasitic capacitance in the transformer to be increased. Furthermore, since the proposed converter is an ultra high step-up converter, the voltage across the transformer is relatively large during the turn-off period, implying that the energy stored in the equivalent parasitic capacitance in the transformer is relatively large. Therefore, based on the mentioned above, high current spikes occur as soon as the switch is turned on. This phenomenon can be seen in the traditional boost converter operating in CCM with a high output voltage. As generally acknowledged, these current spikes will create EMI noises. However, the EMI problem should be taken into account from many aspects, such as EMI choke design, shielding design, layout, etc. Consequently, in this paper, it is very hard to discuss the effects of these current spikes on the EMI problem.
Besides, Figs. 13 and 14 are used to show load transient responses due to step load change from 50% to 100% load and 100% and 50%, respectively. From these figures, it can be seen that the values of two recovery times are both about 1.2V, and the values of the undershoot and overshoot are both within 16ms. And, Fig. 15 shows a photo of the experimental setup.
PPT Slide
Lager Image
Load transient response due to step load change from 50% to 100% load under the rated input voltage.
PPT Slide
Lager Image
Load transient response due to step load change from 100% to 50% load under the rated input voltage.
PPT Slide
Lager Image
Photo of the experimental setup.
Finally, Table 3 makes a comparison between the proposed converter and the converters shown in the References, in terms of voltage conversion ratio, component number, switch voltage stress, output inductor and floating output. From Table 3 , it can be seen that the denominator of the voltage conversion ratio of the proposed converter is the square of one minus duty cycle, and hence, under a given duty cycle and turns ratio, the proposed converter has a higher voltage conversion ratio than all the other references do, but the corresponding voltage stress is higher than all the other voltage stresses. Also, the number of the components is 10, which is acceptable as compared to those used in the References.
Comparison between the proposed converter and the converters shown in the References, in terms of voltage conversion ratio, component number, switch voltage stress, output inductor and floating output
PPT Slide
Lager Image
Comparison between the proposed converter and the converters shown in the References, in terms of voltage conversion ratio, component number, switch voltage stress, output inductor and floating output
6. Conclusion
A high step-up converter is presented herein, which combines the traditional buck-boost converter, the charge pump capacitor and the coupling inductor, so as to make the circuit design relatively elastic. Above all, the leakage inductance energy can be recycled to the output, and hence no voltage spike on the switch occurs. In addition, the used power switch is not floating, so as to make the gate driving circuit quite simple. Based on the mentioned above, this converter is very suitable for the green energy applications.
BIO
K. I. Hwu He was born in Taichung, Taiwan, on August 24, 1965. He received the B.S. and Ph.D. degrees in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1995 and 2001, respectively. From 2001 to 2002, he was the Team Leader of the Voltage-Regulated Module (VRM) at AcBel Company. From 2002 to 2004, he was a Researcher at the Energy and Resources Laboratories, Industrial Technology Research Institute. He is currently a Professor at the Institute of Electrical Engineering, National Taipei University of Technology, Taipei, Taiwan, where he was the Chairman of the Center for Power Electronics Technology from 2005 to 2006. His current research interests include power electronics, converter topology, and digital control.
T. J. Peng He received the M.S degree in electrical engineering from National Taipei University of Technology, Taipei, Taiwan. His research interest is power electronics.
References
Erickson R. W. , Maksimovic D. 2001 Fundamentals of Power Electronics 2nd ed. KLuwer Academic Publishers Norwell
Mohan N. , Undeland T. M. , Robbins W. P. 2003 Power Electronics 2nd ed. Wiley New York
Lin B. R. , Hsieh F. Y. , Chen J. J. 2008 “Analysis and implementation of a bidirectional converter with high converter ratio,” IEEE ICIT’08 1 - 6
Park K.B. , Moon G.W. , Youn M.J. 2011 “Nonisolated high step-up stacked converter based on boost-integrated isolated converter,” IEEE Transactions on Power Electronics 26 (2) 577 - 587    DOI : 10.1109/TPEL.2010.2066578
Deng Y. , Rong Q. , Zhao Y. , Shi J. , He X. 2012 “Single switch high step-up converters with built-in transformer voltage multiplier cell,” IEEE Transactions on Power Electronics 27 (8) 3557 - 3567    DOI : 10.1109/TPEL.2012.2183620
Li Wuhua , Li Weichen , He Xiangning , Xu D. , Wu Bin 2012 “General derivation law of nonisolated high-step-up interleaved converters with built-in transformer,” IEEE Transactions on Industrial Electronics 59 (3) 1650 - 1661    DOI : 10.1109/TIE.2011.2163375
Lai C. M. , Pan C. T. , Cheng M. C. 2012 “High-efficiency modular high step-up interleaved boost converter for dc-microgrid applications,” IEEE Transactions on Industrial Electronics 48 (1) 161 - 171
Wai R. J. , Duan R. Y. 2005 “High-efficiency power conversion for low power fuel cell generation system,” IEEE Transactions on Power Electronics 20 (4) 847 - 856    DOI : 10.1109/TPEL.2005.850936
Yang L. S. , Liang T. J. , Lee H. C. , Chen J. F. 2011 “Novel high step-up DC-DC converter with coupled-inductor and voltage-doubler circuits,” IEEE Transactions on Industrial Electronics 58 (9) 4196 - 4206
Pan C. T. , Lai C. M. 2010 “A high-efficiency high step-up converter with low switch voltage stress for fuel-cell system applications,” IEEE Transactions on Industrial Electronics 57 (6) 1998 - 2006    DOI : 10.1109/TIE.2009.2024100
Hwu K. I. , Yau Y. T. 2009 “KY converter and its derivatives,” IEEE Transactions on Power Electronics 57 (6) 128 - 137
Hwu K. I. , Yau Y. T. 2010 “A KY boost converter,” IEEE Transactions on Power Electronics 25 (11) 2699 - 2703    DOI : 10.1109/TPEL.2010.2051235
Hwu K. I. , Huang K. W. , Tu W. C. 2011 “Step-up converter combining KY and buck-boost converters,” IET Electronics Letters 47 (12) 722 - 724    DOI : 10.1049/el.2011.0392
Hwu K. I. , Yau Y. T. 2010 “Inductor-coupled KY boost converter,” IET Electronics Letters 46 (24) 1624 - 1626    DOI : 10.1049/el.2010.2400
Hwu K. I. , Tu W. C. 2012 “Voltage-boosting converters with energy pumping,” IET Power Electronics 5 (2) 185 - 195    DOI : 10.1049/iet-pel.2011.0076
Hwu K. I. , Yau Y. T. , Chen Y. H. 2008 “A novel voltage-boosting converter with passive voltage clamping,” IEEE ICSET’08 351 - 354
Hwu K. I. , Yau Y. T. 2009 “Two types of KY buckboost converters,” IEEE Transactions on Industrial Electronics 56 (8) 2970 - 2980    DOI : 10.1109/TIE.2009.2023100
Li Wuhua , Li Weichen , Deng Yan , He Xiangning 2010 “Single-stage single-phase high-step-up ZVT boost converter for fuel-cell microgrid system,” IEEE Transactions on Power Electronics 25 (12) 3057 - 3065    DOI : 10.1109/TPEL.2010.2079955
Li Wuhua , Zhao Yi , Deng Yan , He Xiangning 2010 “Interleaved converter with voltage multiplier cell for high step-up and high efficiency conversion,” IEEE Transactions on Power Electronics 25 (9) 2397 - 2408    DOI : 10.1109/TPEL.2010.2048340