This paper introduces a low cost, high efficiency, high performance threephase unified power quality conditioner (UPQC) by using fourswitch threephase inverters (FSTPIs) and an extra capacitor in the shunt active power filter (APF) side of the UPQC. In the proposed UPQC, both shunt and series APFs are developed by using FSTPIs so that the number of switching devices is reduced from twelve to eight devices. In addition, by inserting an additional capacitor in series with the shunt APF, the DClink voltage in the proposed UPQC can also be greatly reduced. As a result, the system cost and power loss of the proposed UPQC is significantly minimized thanks to the use of a smaller number of power switches with a lower rating voltage without degrading the compensation performance of the UPQC. Design of passive components for the proposed UPQC to achieve a good performance is presented in detail. In addition, comparisons on power loss, overall system efficiency, compensation performance between the proposed UPQC and the traditional one are also determined in this paper. Simulation and experimental studies are performed to verify the validity of the proposed topology.
1. Introduction
The intensive use of power electronics devices and nonlinear loads such as diode rectifiers, adjustable speed motor drives, and switching power supplies leads to the injection of a large amount of harmonic currents into the power distribution systems. Harmonic currents cause various severe impacts on power systems such as voltage distortions, increasing losses and heat on networks, malfunction of electronic equipment, and degrading the power quality of networks. Due to these issues, various international standards such as IEEE 5191992
[1]
or IEC 6100032
[2]
have been published to restrict the amount of harmonic currents injected into distribution networks by nonlinear loads, where the total harmonic distortion (THD) of load current is regularly limited within 5% at the rated power condition. Meanwhile, the THD of the voltage harmonics in the low voltage distribution system (<1kV) is also restricted within 5% according to IEEE 5191992 or EN 50160 standards
[3]
. As a consequence, to comply with those harmonic standards, installing power filters and custom devices to compensate current harmonics and improve the power quality becomes a feasible solution and mandatory requirement for both network operators and end users.
Various kinds of custom power devices have been proposed and developed in the literature: Passive filters
[4]
, shunt active power filters (APFs)
[5
,
6]
, and hybrid APFs
[7]
are used to mitigate current harmonics. Meanwhile, series APFs
[8]
and dynamic voltage restorers
[9]
are used for voltage distortion and voltage sag compensation. These compensating devices are effective solutions, but most of them can only deal with one or two power quality issues. Recently, unified power quality conditioners (UPQCs) have been introduced as a powerful and advanced custom power device to simultaneously deal with various current and voltage related problems. An UPQC, composed of shunt and series APFs, is capable of compensating voltage distortions at the supply side as well as current harmonics at the load side to make the load voltage and the supply current become pure sinusoidal. Control of UPQC for harmonic compensation have been widely investigated and various kind of control techniques have been introduced such as hysteresis control
[10

15]
, fuzzy logic control
[16]
, artificial neural network
[17
,
18]
, particle swarm optimizationbased control
[19]
, resonant control
[20]
, etc.
In spite of exhaust researches on UPQC control system, high cost and complexity of control system still restrict the wide application of UPQC in practice, especially in medium and high voltage systems because of some reasons: 1) A typical UPQC topology for threephase system is composed of twelve power switches, which lead to a high cost of an UPQC system. 2) The high DClink voltage, regularly larger than the peaktopeak value of the supply voltage, not only causes higher power losses on the UPQC system but also requires high voltage switching devices. 3) Complex control systems with multistage control and a large number of sensors are regularly required for the conventional UPQC control system
[11]
,
[12]
. In order to reduce the complexity of the UPQC control system, several novel control approaches have been developed by omitting the harmonic detectors and reducing the number of sensors in system
[13

15
,
20]
. Even though the suggested control approaches can improve the control performance of UPQC with a simpler hardware and control system, a high DClink voltage is still required and the high cost problem of the UPQC system cannot be solved in those methods. In
[21]
, a modified threephase UPQC with reduced DClink voltage is introduced. The suggested topology has a low operating DClink voltage, but it has several limitations: 1) Due to the use of hysteresis controllers, the control performance is not effectively improved. 2) Comparisons on power loss and system efficiency of the proposed topology with those of the conventional UPQC are not clearly investigated. 3) The number of switching devices is not reduced compared to the conventional UPQC. In order to reduce the number of switching devices in the UPQC, the fourswitch threephase inverters (FSTPIs) can be considered to replace the traditional threephase inverters. However, in case that the FSTPI instead of the traditional threephase inverters is applied to the UPQC system without any modification, the DClink voltage of the UPQC will increase twice
[22]
. In addition, because one phase leg of FSTPI is the midpoint of two capacitors, the inherent variation of these two capacitor voltage badly affects the performance of the UPQC.
To overcome those issues, this paper introduces a new topology to apply the FSTPI to the UPQC without degrading control performance. A new topology for threephase UPQC includes two FSTPIs and an extra capacitor in series with the shunt APF of the UPQC. The proposed topology shows remarkable advantages compared to the traditional UPQC: 1) By employing two FSTPIs for both shunt and series APFs in the UPQC, the number of switching devices is reduced from twelve to eight, which results in the cost reduction of the UPQC system. 2) By adding an extra capacitor in series with the shunt APF, the DClink voltage using in the proposed UPQC is significantly decreased compared to that of the traditional one, which leads to the reduction of both the power losses and the voltage ratings for the power switches on UPQC. 3) A simple system with a minimum number of sensors is proposed to improve control performance of the UPQC. Design of passive components for the proposed UPQC to achieve a good performance is presented in detail. Simulation and experimental studies are performed to verify the validity of the proposed topology.
This paper is organized as follows. Section 2 depicts the hardware configuration of the conventional and proposed UPQC topologies. Section 3 describes the design of passive components for the proposed UPQC system. In Section 4, the control strategy for proposed UPQC topology is presented. Section 5 shows simulation results of both the traditional and proposed UPQCs. Section 6 corroborates the expected features of the proposed UPQC topology through experimental results. Section 7 presents the conclusions of this study.
2. Proposed UPQC Topology
 2.1 Configuration of conventional threephase UPQC
Fig. 1
shows the configuration of the traditional threephase UPQC, which consists of two voltage source inverters connected backtoback through a common DClink capacitor, where one inverter is the shunt APF and another inverter is the series APF. The series APF is connected in series between the supply and the load through a series transformer. Meanwhile, the shunt APF is connected in parallel with the loads through an inductor
L_{pf}
. A
LC
(
L_{f}
,
C_{f}
) filter is connected at the ac output voltage of the series APF to eliminate high frequency switching ripples. In
Fig. 1
, the traditional UPQC has a large number of power switching devices, i.e., twelve devices. In addition, to ensure a proper operation of the UPQC, the voltage across the common DClink capacitor must be higher than peaktopeak value of supply voltage. Besides, in order to achieve the harmonic voltage and current compensation, a complex control system and a large number of sensors at
v_{S}
,
i_{L}
,
v_{Sr}
,
i_{F}
, and
V_{dc}
are generally required
[8

11]
. These problems result in a high system cost of UPQC and limit the application of UPQC in practice.
Configuration of the typical threephase UPQC.
 2.2 Proposed threephase UPQC
In order to overcome the high cost issue of the traditional threephase UPQC, we propose threephase UPQC by using FSTPI as shown in
Fig. 2
. Because the proposed UPQC is composed of two FSTPIs, the total number of switching devices is reduced from twelve in traditional topology to eight switches in the proposed system. In addition, the traditional UPQC topology is modified by adding the extra capacitor (
C_{pf}
) in series with the filter inductor (
L_{pf}
) of the shunt APF. This extra capacitor takes three major roles: 1)
C_{pf}
absorbs the fundamental component of the supply voltage, so that no fundamental voltage is imposed on shunt APF and the required DClink voltage is greatly reduced. 2)
C_{pf}
and
L_{pf}
combine and operate as a passive filter to sink a specific (regularly the fifth or seventh) harmonic current. 3)
C_{pf}
can also supply a part of reactive power required by loads. As a consequence, the use of
C_{pf}
allows reducing the DClink voltage as well as supporting the shunt APF to compensate both harmonic current and reactive power. Design of passive components in the proposed UPQC plays a vital role to achieve a good performance of the UPQC. This content will be discussed in detail in section 3. In addition, to further enhance the compensation performance of the proposed UPQC, an advanced control strategy is developed as shown in
Fig. 2
: The repetitive controller is employed in the voltage control scheme for the series APF and a proportional controller is adopted in the current control loop of the shunt APF. Analysis and design of the voltage and current controllers are described in detail in section 4.
Configuration of the proposed threephase UPQC and its control strategy.
3. Design of Passive Components for Proposed UPQC Topology
The passive components for UPQC include the inductor
L_{pf}
, the capacitor
C_{pf}
, the
LC
filter of the series APF, and the DClink capacitor
C_{dc}
. They are designed as following:
 3.1 Design ofLpfandCpf
In
Fig. 2
, a passive filter, made of
C_{pf}
and
L_{pf}
, can eliminate the specific harmonic current generated by nonlinear loads. In this paper,
C_{pf}
and
L_{pf}
are tuned to absorb the seventh order harmonic current (n
_{1}
=7) instead of the fifth harmonic to reduce the volume and cost of
C_{pf}
and
L_{pf}
[23]
. The resonant frequency of the passive filter
ω
_{res1}
is defined as following:
where
f_{s}
= 50
Hz
denotes the fundamental frequency of system.
In addition,
C_{pf}
also supplies a part of reactive power required by the loads, which is calculated as
where
V_{ll}
=190V is the RMS value of the linetoline voltage in this paper.
From (2), we can see that a higher value of
C_{pf}
provides a larger amount of
Q_{c}
. However, if
Q_{c}
is larger than the consumed reactive load power, overcompensation happens. In that case, the current flow into the shunt APF (
i_{F,abc}
) is significantly increased, which causes shunt APF oversized. Furthermore, a large
C_{pf}
makes the UPQC controller expensive and bulky. Therefore, it is important to determine the suitable value of
C_{pf}
. Fortunately, authors in
[23]
introduce the optimal
C_{pf}
to be 25% of the base capacitance of the system capacitance
C_{b}
which supplies the rated load power.
C_{b}
is defined as following:
where
P_{L}
= 5 kW is the rated load power.
A closest commercial capacitance is chosen, i.e.,
C_{pf}
= 75
μF
.
From (1), we can obtain
L_{pf}
as
Then, a commercial inductor with the inductance value of
L_{pf}
= 2.8 mH is selected.
 3.2 Design ofLCfilter (LfandCf)
The
LC
filter is used to suppress the switching noise of series APF. Since the series APF is used to compensate higher harmonic voltages than the typical inverter output frequency, the resonant frequency of the
LC
filter should be sufficiently high not to degrade the performance of the UPQC. In this study, we assume that the highest harmonic voltage order contained in the source voltage is 13
^{th}
(n
_{2}
=13), which corresponds to 650 Hz in 50 Hz system. In this case, the resonant frequency of the
LC
filter can be selected to be four times larger than the highest considering harmonic frequency
[5]
.
As shown in (6), there are countless options to select
C_{f}
and
L_{f}
. When the volume and cost of the filter are considered as dominant factors in design,
C_{f}
is generally selected to be less than 5% of the base value
C_{b}
for volume and cost optimization
[5]
. In this paper,
C_{f}
is selected as 4% of
C_{b}
:
A closest commercial capacitance available on the market is selected, i.e.,
C_{f}
= 12
μF
.
From (6),
L_{f}
is determined as
So, we choose
L_{f}
=0.5 mH.
 3.3 Selection of the DClink voltage level and DClink capacitor
It is necessary to determine the DClink voltage (
V_{dc}
) before selecting the value of DClink capacitor
C_{dc}
. In order to choose
V_{dc}
properly, we need to know the supply voltage level. In this paper, threephase phase voltage is selected as 110V RMS. Then, the peaktopeak value of phase voltage becomes 311V. In case of the traditional UPQC, the DClink voltage is higher than the peaktopeak value of the phase voltage to ensure a proper operation of the shunt APF
[24]
. Hence, the reference DClink voltage is properly selected as 350 V in the traditional UPQC.
In contrast, the DClink voltage of the proposed UPQC becomes much lower than that of traditional topology thanks to the use of capacitor
C_{pf}
. In fact, the selection of DClink voltage for the proposed UPQC is not a straightforward task because there is no lower restriction for this value. However, we have a constraint to select this value: If the DClink voltage is low, the power losses and switching noises can be reduced, but the harmonic compensation performance is degraded at the meantime. On the other hand, if the DClink voltage is high, the control performance is improved, but the power losses and switching noises are increased. In addition, an appropriate DClink voltage also depends on the harmonic currents in the load current and the values of
L_{pf}
and
C_{pf}
[7]
. By using the method in
[7]
, we select the DClink voltage to be 100V for the proposed UPQC.
Capacitance of the DClink capacitor should be large enough to suppress the voltage fluctuation on the DClink under the load variation. In this paper, the maximum allowable voltage variation is selected as 3% of the DClink voltage, i.e., Δ
V_{dc}
= 0.03
V_{dc}
according to the selection guideline in
[25]
. If the DClink voltage is varied with the value of
ΔV_{dc}
when the load is changed from 50% to full load,
C_{dc}
is calculated as following:
where
I_{rated}
=16.7A is the current rating of load.
In the proposed UPQC, two capacitors are connected in series, so the capacitance of each capacitor is twice of the determined value in (9). From (9), the closest commercial capacitance available on the market is selected, i.e.,
C
_{1}
=
C
_{2}
= 2
C_{dc}
= 2200
μF
.
We summarize all system parameters in
Table 1
including the designed parameters.
System parameters
4. Control Strategy for proposed UPQC
 4.1 Control of the shunt APF
The passive filter has been designed to mitigate seventh harmonic current, and the remaining harmonic currents can be sufficiently filtered by an appropriate control strategy in the shunt APF. In addition, the shunt APF also has a responsibility to maintain the common DClink voltage in a stable condition. As a result, the control strategy includes two parts: The harmonic current compensation and the DClink voltage regulation as shown in
Fig. 3
. Unlike the complex control scheme in the shunt APF of the traditional UPQC, which requires information of load current, shunt APF current, and DClink voltage
[8]
, the control strategy in
Fig. 3
is simpler, which demands the information of the supply current and the DClink voltage. Therefore, only one voltage sensor and two current sensors are needed.
Control scheme for the shunt APF.
In
Fig. 3
, the DClink voltage is regulated by using a proportionalintegral (PI) controller and its output, i.e., the reference current in
q
axis
Meanwhile, in the harmonic compensation block, the threephase supply current is measured and transformed into synchronous (
dq
) reference frame using
abc

dq
transformation in (10).
Then, a highpass filter (HPF) given in (11) is applied to extract harmonic components in the supply current, which becomes the reference current
and
.
where
ω_{p}
= 2
π
.20 (rad/s) is the passing frequency of the HPF.
Afterward, a simple proportional controller
K_{p}
is utilized to mitigate the harmonic components in the supply current. Finally, the output control signals for the threephase fourswitch shunt APF are calculated as
where
In addition, since the middle point of two split capacitors is used for common phase leg of both shunt and series APFs, the instantaneous voltage on these two capacitors varies according to the filter currents, mainly the shunt APF current (
i_{Fc}
). In fourswitch threephase inverters, the fluctuation of capacitor voltage is unavoidable and it may badly affect the performance of both shunt and series APFs. However, it is not necessary to insert the additional controller to balance the capacitor voltage because the performance of the series and shunt APFs is not degraded if a proper voltage variation compensation scheme is employed. According to
[22]
, if the modulation signals for two phase legs (
Sh_{a}
and
Sh_{b}
) of the shunt APF are adjusted as (13), the voltage variation on
V
_{C1}
and
V
_{C2}
becomes negligible, and the compensation performance of the shunt APF is not degraded.
where
d
_{1}
and
d
_{2}
are modulation signals for phase leg
Sh_{a}
and
Sh_{b}
of shunt APF, respectively, and
V
_{C1}
and
V
_{C2}
are the capacitor voltages.
 4.2 Control of the series APF
The purpose of the series APF is to compensate harmonic components in the distorted supply voltage to maintain the load voltage sinusoidal. The supply voltage (
v_{S}
) is assumed to be distorted, which includes the fundamental (
v
_{S1}
) and harmonic components (
v_{Sn}
) as follows
where n is the nth harmonic order.
To make load voltage sinusoidal, the harmonic components presented in (14) must be completely compensated. Some previous studies adopted hysteresis control for harmonic voltage compensation
[12

15]
. But the hysteresis control cannot assure a good performance of the load voltage due to the variation of the switching frequency. To overcome this drawback and to effectively compensate a large number of harmonic components, this paper adopts the repetitive control technique to regulate the voltage harmonics
[26]
.
The voltage controller for the series APF is illustrated in
Fig. 4
. The control strategy only needs the information of the load voltage. Thus, only two voltage sensors are required for the control scheme. In
Fig. 4
, the threephase load voltage is measured and transformed into the
d

q
reference frame (
v_{L,dq}
).Then, the load voltage is compared with its reference value
and the error is input to the repetitive controller (RC) to generate the control signal for the series APF. The transfer function of the RC is given as
where
T_{d}
is the time delay of the RC,
Q(s)
is a filter transfer function, and
K_{r}
is the RC gain.
Voltage controller for the series APF.
In
Fig. 4
, after executing the voltage controller to compensate voltage harmonics, the output control signals for the series APF (
and
) is calculated as
where
Similar to the shunt APF control, the modulation signals for two phase legs
Sr_{a}
and
Sr_{b}
of the series APF are also adjusted as
where
d
_{3}
and
d
_{4}
are modulation signals for phase leg
Sr_{a}
and
Sr_{b}
, respectively.
Detail on design procedure of the RC for harmonic compensator is described clearly in
[26]
.
5. Simulation results
To verify the validity of the proposed UPQC topology, digital simulation is carried out with the aid of the PSIM using the system parameters in
Table 1
. The distorted supply voltage is programed by injecting fifth and seventh order harmonic voltages. In addition, the load current is also highly distorted due to the use of threephase diode rectifier at the load side. The total harmonic distortion (THD) values of the supply current and the load voltage are about 27.5% and 8.06%, respectively.
Fig. 5
shows the simulation results of the traditional UPQC by using the resonant control method introduced in
[17]
. In
Fig. 5
, the load voltage and the supply current are compensated to be sinusoidal despite of the severe condition of the supply voltage and the load current. The THD of the load voltage and the supply current after compensation are reduced to about 1.97% and 3.24%, respectively. In
Fig. 5
, the DClink voltage is 350V in order to guarantee a proper operation in the conventional UPQC. This high voltage causes high cost, higher switching noises and power losses in the UPQC.
Simulation results of the traditional UPQC, from top to bottom: supply voltage, load voltage, load current, supply current, filter current, and DClink voltage.
To verify the superiority of the proposed topology compared to the traditional one, the proposed UPQC is investigated under the same condition with
Fig. 5
and the results are illustrated in
Fig. 6
. From
Fig. 6
, the load voltage and the supply current are effectively compensated to be sinusoidal with extremely low THD values of 1.22% and 1.35%, respectively. These values totally comply with the IEEE 5191992 and IEC 6100032 standards. Therefore, we can say that the performance of the proposed UPQC is not degraded compared to that of the conventional one despite of the reduced number of switching devices.
Simulation results of the proposed UPQC, from top to bottom: supply voltage, load voltage, load current, supply current, filter current, and DClink and capacitor voltages.
Furthermore, a vital improvement of the proposed topology is that the required DClink voltage for the UPQC is very low, i.e., 100V, which is less than onethird of that in the traditional UPQC. This low DClink voltage leads to the decrement of the switching noises on the load voltage and the supply current waveforms, so that the THD values of the load voltage and the supply current have been slightly reduced compared to those in
Fig. 5
. In addition, the low DClink voltage results in the reduction of power losses, which has the overall efficiency of the UPQC system improved. In fact, because we use the midpoint of two capacitors as a common phase leg of both shunt and series APFs, the voltages on two capacitors
C_{1}
and
C_{2}
are fluctuated in a small range as shown in
Fig. 6
. But, this voltage variation has no effects on the performance of the load voltage and the supply current. A summary on THD values of the load voltage and the supply current for the conventional and the proposed UPQC is given in
Table 2
. From
Table 2
, the proposed UPQC offers a slightly better THD performance thanks to the reduced DClink voltage, which results in a smaller amount of switching noises.
Comparison on THD of the load voltage and the supply current by using the conventional and the proposed UPQC
Comparison on THD of the load voltage and the supply current by using the conventional and the proposed UPQC
To verify the robust operation of the proposed UPQC with load change, dynamic performance of the proposed UPQC is plotted in
Fig. 7
with the increasing the load power from 50% to full load condition. In
Fig. 7
, the load voltage is maintained sinusoidal during the transition, and the UPQC takes only about three fundamental cycles to compensate the supply current to be sinusoidal. And also, there are no overcurrent or resonance phenomena at the supply current in spite of the load variation. These results verify the fast dynamic response and the robust operation of the proposed UPQC topology under load variation. As a result, the proposed UPQC shows a good steadystate performance as well as a fast and robust response under the load change.
Dynamic responses of the proposed UPQC with load change, from top to bottom: supply voltage, load voltage, load current, supply current, filter current, and DClink and capacitor voltages.
6. Experimetal Results
An experimental system is built as shown in
Fig. 8
to show the possibility of the practical application. All system parameters in experimental system are the same as those used in simulation given in
Table 1
. The proposed UPQC is implemented by using four IGBT modules (FMG2G50 US60 from Fairchild). The control strategy is realized by a 32bit floatingpoint DSP (TMS320F28335 of Texas Instruments). The supply voltage is generated by a Programmable AC Power Source (Chroma 61704) and a threephase diode rectifier is used as the nonlinear load. The THD values of the load voltage and the supply current, and overall system efficiency are measured by a power analyzer (HIOKI 3193).
Experimental platform for the proposed UPQC.
Experimental results of the proposed UPQC are shown in
Fig. 9
. As shown in
Fig. 9
, even though the supply voltage and the load current are highly distorted, the load voltage and the supply current are effectively compensated to be almost pure sinusoidal with very low THD values of 1.58% and 2.06%, respectively. These results are a little higher than those in simulation results due to the switching noises on experimental system. However, these values are still very low and completely comply with the IEEE 5191992 and IEC 6100032 standards. In
Fig. 9
, the injected current (
i_{Fa}
) of the shunt APF is lower than 30% of load current. Therefore, the use of additional capacitor
C_{pf}
in the proposed UPQC topology does not cause the whole system bulky and oversize. In addition, the DClink voltage of the proposed UPQC is about 100V, which is much lower compared with that of the traditional UPQC, 350V, under the same supply voltage condition
[20]
. Therefore, the UPQC performance is not degraded even though the proposed UPQC uses FSTPI with a reduced number of switching devices and lower DClink voltage.
Steadystate performance of the proposed UPQC, from top to bottom: supply voltage, load voltage, supply current, load current, DClink voltage, and filter current.
Besides a good steadystate performance, a robust operation under the load variation is also a vital assessment. The dynamic performance of the proposed UPQC is plotted in Fig. 10 by changing the load, which increases from 50% to full load condition. The experimental results in
Fig. 10
are similar to the simulation results in
Fig. 7
, which shows that the proposed UPQC provides a robust response under the load change.
Dynamic responses of the proposed UPQC under load change, from top to bottom: supply voltage, load voltage, supply current, load current, DClink voltage, and filter current.
Power loss and the overall system efficiency are experimentally obtained by using power analyzer, and the results are summarized in
Table 3
. From
Table 3
, the proposed UPQC has lower power losses thanks to the reduced DClink voltage (100V) compared to 350V for the traditional UPQC. As a consequence, the overall system efficiency of the proposed UPQC is higher than that of the traditional one in spite of a reduced number of switching devices and sensors as well as a decreased DClink voltage. Therefore, we can say that the proposed UPQC achieves low cost, high efficiency, and high performance for the UPQC.
Comparison on characteristics of conventional and proposed UPQC
Comparison on characteristics of conventional and proposed UPQC
7. Conclusions
This paper proposed a low cost, high efficiency and high performance threephase UPQC by using FSTPIs and an extra capacitor in the shunt APF side of the UPQC. The proposed UPQC accomplishes a lower cost as well as a lower power loss thanks to a reduced number of power switches and a low DClink voltage. Even though the proposed topology requires extra capacitors, it is economically feasible in the system cost and efficiency because the current rating of additional capacitors is lower than onethird of the rated load current.
The validity of the proposed topology is verified through simulation and experiment. Simulation and experimental results show that the THD values of the supply current and the load voltage are kept very low and sufficiently comply with IEEE 5191192 and IEC 6100032 standards. The proposed topology is suitable to apply for the harmonic compensation in medium and high voltage distribution systems.
Acknowledgements
This work was supported by 2014 Research Funds of Hyundai Heavy Industries for University of Ulsan.
BIO
QuocNam Trinh was born in Vietnam, in 1985. He received the B.S. degree in Power Engineering from Ho Chi Minh City University of Technology, Vietnam, in 2008 and the Ph.D degree in Electrical Engineering from University of Ulsan, Korea in 2014. Since August 2014, he has joined Energy Research Institute @ NTU, Nanyang Technological University, Singapore as a postdoctoral research fellow. His research interests are active power filters, harmonic compensation, distributed generation, and gridconnected inverters.
HongHee Lee received his B.S., M.S., and Ph.D. in Electrical Engineering from Seoul National University, Seoul, Korea, in 1980, 1982, and 1990, respectively. From 1994 to 1995, he was a Visiting Professor at the Texas A&M University. He has been a Professor in the School of Electrical Engineering in the Department of Electrical Engineering, University of Ulsan, Ulsan, Korea since 1985. He is also the Director of the Networkbased Automation Research Center (NARC), which is sponsored by the Ministry of Trade, Industry and Energy. His research interests include power electronics, networkbased motor control, and renewable energy. Dr. Lee is a member of the Institute of Electrical and Electronics Engineers (IEEE), the Korean Institute of Power Electronics (KIPE), the Korean Institute of Electrical Engineers (KIEE), and the Institute of Control, Robotics and Systems (ICROS).
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