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Maximum Efficiency Operation of Three-Level T-type Inverter for Low-Voltage and Low-Power Home Appliances
Maximum Efficiency Operation of Three-Level T-type Inverter for Low-Voltage and Low-Power Home Appliances
Journal of Electrical Engineering and Technology. 2015. Mar, 10(2): 586-594
Copyright © 2015, The Korean Institute of Electrical Engineers
This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0/)which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
  • Received : September 23, 2014
  • Accepted : October 03, 2014
  • Published : March 01, 2015
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About the Authors
Seung-Min Shin
School of Information and Communication Engineering, Sungkyunkwan University, Korea. (shinmin000@skku.edu)
Jung-Hoon Ahn
School of Information and Communication Engineering, Sungkyunkwan University, Korea. (shinmin000@skku.edu)
Byoung-Kuk Lee
Corresponding Author: School of Information and Communication Engineering, Sungkyunkwan University, Korea. (bkleeskku@skku.edu)

Abstract
This paper proposes a maximum efficiency operation strategy for three-level T-type inverter in entire operation areas. The three-level T-type inverter has higher and lower efficiency areas compared with two-level inverter. The proposed strategy aims to operate in the maximum efficiency point for the low-voltage and low-power home appliances. The three-level T-type inverter is analyzed in detail, and the two operation mode selection strategy is developed. The proposed algorithm is verified by theoretical analysis and experimental results.
Keywords
1. Introduction
Voltage source inverters are widely used in many applications, such as industrial systems and home appliances, to achieve energy conservation and to improve high motion control quality. Especially, the two-level inverter to drive a multi-pole permanent magnet synchronous motor is a general choice for modern home appliances and industrial systems [1 , 2] . In recent years, the low-voltage applications with 270V~600V DC link voltage for home appliances is continually increased and for higher efficient energy conversion and low cost, the micro-control unit and the power electronics technology are advanced [3] .
A two-level voltage source inverter is commonly used for home appliances and industrial systems since its configuration is simple and the reliability is sufficiently ensured. However, there is a limit to improve the two-level inverter efficiency and performance because two-level inverter output voltage is decided by ±V DC /2. Furthermore, the inverter efficiency and performance are varied according to the switching method. In the case of the six-step modulation, the switching loss can be reduced, but the copper loss and torque ripple are increased because of the low frequency harmonics. The pulse width modulation method (PWM) is commonly used to solve the harmonic problem of this six-step method in many applications. PWM methods can be reduced the copper loss and the torque ripple compared with six-step method since PWM method switching frequency is higher than six-step method, but the switching loss becomes increased. The switching loss is more prominent when the switching frequency is increased and the DC link voltage becomes higher [4] . Therefore, in order to overcome these limitations of the two-level inverter efficiency and performance, a three-level inverter is being researched in various applications for further improvement of energy efficiency, reliability, power and density [5] .
The multi-level topology such as the three-level inverter has been developed to drive medium-voltage level (DC link voltage: 600V~2500V) and high-voltage level (DC link voltage: 2500V~) since a semiconductor voltage blocking capability in conjunction is limited. Furthermore, it is verified that the multi-level topology offered a superior harmonic spectrum, lower overvoltage stress at cable and end windings of motors, lower common-mode voltage and lower switching loss [6] . Among various well-established multi-level topologies, the neutral-point clamped inverter (NPCI), flying capacitor inverter (FCI), and cascaded H-bridge inverter (CHBI) have been widely used and investigated as shown in Fig. 1 [7 - 14] . For these topologies, the switching loss in each switch is half and the conduction losses become double of the counterpart of the two-level inverter due to the two switch series connection. Therefore, these three-level inverter topologies are not suitable for low-voltage and low-power applications. To overcome these characteristics in the multi-level topology, the three-level T-type inverter (3LTI) has been proposed for the high efficiency and performance in low-voltage applications [15] .
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Conventional multi-level inverter topologies
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Circuit configuration of three-level T-type inverter
Even though the 3LTI is generally evaluated and investigated to apply in low-voltage industrial systems [16 , 17] , it has difficulties to apply in low-voltage and low-power home appliances such as refrigerators and air conditioners because the increased efficiency is not sufficient due to its complexity and cost problem. More accurately, since the utilization rate of switches is varied according to the modulation index (MI), the 3LTI has together higher and lower efficiency points. Therefore, in this paper, the maximum efficiency operation strategy for the 3LTI in entire operation areas is proposed. With the proposed strategy, the 3LTI is always operated in the maximum efficiency point in low-voltage and low-power applications. The proposed strategy is theoretically explained in detail and its validity is verified by experiment results.
2. General Characteristics of Three-Level T-type Inverters
- 2.1 Operational principle
Basically, the output bridge can be connected one of three states:
  • 1) SX, Highis turn-on- It is connected to positive DC link voltage level- The output voltage is VDC/2
  • 2) SX, N1or SX, N2is turn-on- It is connected to neutral voltage level- The output voltage is 0
  • 3) SX, Lowis turn-on- It is connected to negative DC link voltage level- The output voltage is -VDC/2
The 3LTI is implemented by comparing the reference voltage with two triangular waves which are corresponding to the high-side capacitor voltage (V DC1 ) and low-side capacitor voltage (V DC2 ). During the period of the positive reference, S X, High and S X, N1 are operated complementary through the relationship between the reference voltage and the triangular wave corresponding to V DC1 , and S X, N2 is kept on-state in order to guarantee the current path through the anti-parallel diode of S X, N1 . Therefore, it is possible to control the phase voltage in the period of the positive reference. On the contrary, during the period of the negative reference, S X, Low and S X, N2 are operated complementary through the relationship between the reference voltage and the triangular wave corresponding to V DC2 , and S X, N1 is kept on-state. Then, since improper voltage sharing on DC link capacitors leads to an overvoltage on switches and, a failure of the 3LTI, the capacitor voltage change should be reflected in the triangular wave to maintain the DC link voltage balancing.
- 2.2 Analysis of operating modes
One phase of the T-type inverter has six operating modes according to the direction of the output current (i X ) and reference voltage (V X, RER ) as shown in Fig. 3 . Modes 1, 3, 4, and 6 are same as two-level inverter operation modes. Mode 2 and 5 construct bidirectional current path between the neutral point and the output bridge. Therefore, the operating mode is selected one of two-level inverter operation modes (Mode 1, Mode 3, Mode 4, Mode 6) and one of bidirectional current path modes (Mode 2, Mode 5) as shown in Fig. 4 . For instance, in period 1, since the output bridge is connected to the positive voltage level for the negative output current, mode 1 and mode 2 are selected. Therefore, mode 4 and mode 5 are selected in period 2, mode 5 and mode 6 are selected in period 3, and mode 2 and mode 3 are selected in period 4.
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Operation mode for one phase of T-type inverter
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Operating mode classification according to the relationship between the reference voltage and the load current
The proportion of each period is changed according to the phase delay. If the phase delay is increased, the proportion of period 1 and period 3 is increased, but the proportion of period 2 and period 4 is decreased. Furthermore, the utilization rate of S X, High and S X, Low is changed according to the magnitude of V X, REF . If the size of V X, REF is bigger than the present value, S X, High and S X, Low are more frequently used. As a result, in the high MI areas, the 3LFI and the two-level inverter are similar in the utilization rate of switches. Therefore, the 3LFI efficiency is influenced by the phase delay and the MI.
3. Proposed Maximum Efficiency Operation Algorithm
- 3.1 Utilization rate of switch for 3LTI
The utilization rate of switches for the 3LTI is influenced by the MI, switching method and reference voltage angle. Especially, the utilization rate of switches is instantaneously varied according to the angle of the reference voltage in each cycle. For example, when the angle of the reference voltage is 30°, the utilization rate of the V-phase switch is always two regardless of the MI and switching method since the V-phase reference voltage is zero voltage. However, in this case, the utilization rate of the U-phase switch and W-phase switch is varied according to the MI and switching method. Fig. 5 shows the variation of the reference voltage in space vector pulse width modulation (SVPWM) and classification of areas according to the reference voltage. As a result, controllable switches are changed according to the reference voltage. In case 1, case 2 and case 6, V U, Ref is the positive value. Therefore, in these cases, V U, Ref determines S U, High and S U, N1 switching patterns and the utilization rate of S U, High and S U, N1 . However, in case 3, case 4 and case 5, V U, Ref is the negative value. Therefore, in contrast with case 1, case 2 and case 6, V U, Ref determines S U, Low and S U, N2 switching patterns and the utilization rate of S U, Low and S U, N2 . Therefore, the instantaneous utilization rate of the switch (S θ ) for the SVPWM 3LTI can be calculated as
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where V SN is the offset voltage according to the switching method and θ is the angle of the reference voltage.
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Classification of areas according to reference voltage
Basically, regardless of the MI and switching method, the average utilization rate of switches for the two-level inverter is always three. The average utilization rate of switches for the three-level NPCI and FCI is always six. However, the average utilization rate of switches for the 3LTI is changed based on the MI and switching method as shown in Table 1 . Neutral point switches are more used compared with high-side and low-side switches in the low MI. Since if the MI is increased, the utilization rate of high-side and low-side switches is also increased, the average utilization rate of switches is decreased. Therefore, if the MI is low, conduction losses of the 3LTI are similar to the three-level NPCI and FCI. However, if the MI is sufficiently high, conduction losses of the 3LTI are similar to the two-level inverter. Furthermore, in the case of using a discrete pulse width modulation, the average utilization rate of switches is much more decreased.
Average utilization rate of switches according to the MI and the inverter topology
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Average utilization rate of switches according to the MI and the inverter topology
- 3.2 Efficiency calculation method and proposed maximum efficiency operation algorithm
Commonly, switching losses can be calculated by using the switching energy and switching frequency. However, since all switching actions during a fundamental period have to be considered, two assumptions are required. First, the switching frequency (f SW ) is higher than the fundamental frequency. Second, the switching actions evenly distributed over the fundamental period. Therefore, the average switching energy losses (E SWITCH ) and the switching losses (P SWITCH ) can be expressed as
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where V SWITCH is the switching voltage, and V BASE is the reference switching voltage, used in the datasheet. Using these two value, the switching energy is linearly scaled. θ represents the current angle, I PEAK is the maximum current value, and α 1 and α 2 represent the switching intervals within one fundamental period. A and B are the curvefitting constants for IGBTs (A S , B S ) and diodes (A D , B D ) switching energy.
In order to calculate the 3LTI switching losses, operation switches are classified depending on the switching intervals as shown in Table 2 . V SWITCH is determined according to the connection position of the operation switch. The high-side and low-side switches (S X, High , S X, Low ) have to block the full DC link voltage. However, since the full DC link voltage is blocked by using two IGBTs in the neutral point switches (S X, N1 , S X, N2 ), V SWITCH of the neutral point switches is half of the full DC link voltage. Therefore, based on Table 2 , the average switching losses for each switch can be calculated as
Operation switches and operation modes according to the switching intervals for the 3LTI
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Operation switches and operation modes according to the switching intervals for the 3LTI
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where ø represents the phase delay angle.
Conduction losses can be calculated using the conduction I-V characteristics of the IGBT and anti-parallel diode. These characteristics can be approximated by using two curve-fitting constants with instantaneous current (i), on-state zero-current saturation voltage (V 0 ) and on-state resistance (R)
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Then, the average conduction losses (P CON ) can be expressed as
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where D is a duty cycle, and β 1 and β 2 represent conduction angle intervals within one fundamental period.
The conduction interval and conduction switch can be classified as shown in Table 3 . For example, in period 2, mode 4 and mode 5 are operated complementary by using S X, High , D X, N1 and S X, N2 . Therefore, the conduction interval can be determined as 0~(π – ø). The duty cycle is assumed according to the output bridge state change. Based on Table 3 , average conduction losses for each switch can be calculated as
Conduction switches and duty cycle according to the conduction intervals for the 3LTI
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Conduction switches and duty cycle according to the conduction intervals for the 3LTI
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where V 0,S and R S is the IGBT on-state zero-current saturation voltage and on-state resistance, V 0,D and R D is the diode on-state zero-current saturation voltage and on-state resistance, respectively. Therefore, total conduction losses for the 3LTI can be calculated as
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Table 4 shows calculation results of switching and conduction losses according to the MI in the half and full load condition. Conduction and switching losses are calculated based on the IKP10B60T (600V, 10A, Infineon), which was selected to implement the low-voltage and low-power 3LTI prototype. The percent value represents the ratio of the 3LTI calculation result according to the MI compared with the two-level inverter. 3LTI switching losses are smaller than two-level inverter, and conduction losses are varied from 193% to 133% according to the MI. Consequentially, the 3LTI has together higher and lower efficiency areas compared with the two-level inverter. Especially, in the high MI, the 3LTI efficiency is higher than the two-level inverter. The magnitude and ratio of the calculated loss might be changed according to the electrical characteristics of the switching device, the overall trend of loss analysis could be similar to the evaluated results in Table 4 .
Calculation results of switching and conduction losses according to the MI
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Calculation results of switching and conduction losses according to the MI
If the 3LTI is applied in the low-voltage and low-power home appliance such as refrigerators and air conditioners, compared with the two-level inverter, it has low efficiency in the low speed region, but it has high efficiency in the high speed region. Especially, due to the low power factor, the efficiency is much lower in the low-load and low-speed region since the proportion of conduction losses is further increased.
The 3LTI consists of the general two-level inverter and six IGBTs. Six IGBTs are connected between the DC link midpoint and each output bridge in order to generate the zero voltage in the two-level inverter. Therefore, unlike the other well-known three-level inverter such as NPCI, FCI and CHBI, the 3LTI is possible the selective operation as shown in Fig. 6 , such as the two-level operation mode and the three-level operation mode. If the operation mode is selected to drive maximum efficiency according to the load current, MI and power factor as shown in Fig. 7 , the 3LTI is possible to always obtain the maximum efficiency. Based on each mode efficiency, the 3LTI is operated two-level operation mode in low-speed region, and it is operated three-level operation mode in high-speed region.
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Three-level and two-level operation mode
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Operation mode selection according to each mode efficiency
4. Experimental Results
A prototype of the 3LTI system was built to verify the validity of the proposed maximum efficiency operation strategy. Fig. 8 shows the entire block diagram of the 3LTI test-bed, along with the prototype. The strategy was implemented base on a digital signal process 28335, and 600-V 10-A Infineon IKP10B60T single IGBT is used for the 3LTI. Also, an interior permanent magnet synchronous motor (IPMSM) for a refrigerator driver system is applied to the experiment test-bed and the proposed strategy is verified under the operation condition of refrigerator. The conditions and parameters of the experiments are shown in Table 5 . The output waveform of the three-level operation mode and two-level operation mode are shown in Fig. 9 .
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Experimental test-bed
Experimental conditions and motor parameter
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Experimental conditions and motor parameter
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Output voltage and current waveforms according to operation modes (VUV: 50V/div., IU: 1A/div., IV: 1A/div., VU*: 1V/div.)
Fig. 10 shows the 3LTI efficiency without and with the proposed strategy under half and full loads. In the low MI region such as 1000RPM and 1800RPM, the 3LTI efficiency is improved about 2% compared with the two-level mode by using the proposed strategy. Similarly, in the half load condition, the 3LTI efficiency with the proposed strategy is improved about 2%. In the motor speed higher than 2000RPM, since the efficiency of the three-level operation mode is higher than the efficiency of the two-level operation mode, the 3LTI with the proposed strategy is operated as the three-level operation mode.
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3LTI efficiency comparison between the three-level mode operation and the proposed strategy operation
Fig. 11 shows 3LTI efficiency with the proposed strategy and the two-level inverter efficiency. In the low MI region, since the 3LTI is operated the two-level operation mode, the two-level inverter and the 3LTI efficiency are similar. However, in the middle and high MI region, the 3LTI efficiency is higher than the two-level inverter since the 3LTI is operated as the three-level operation mode. As a result, the 3LTI with the proposed strategy can be always obtained the maximum efficiency in all operation areas.
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Efficiency comparison between the two-level inverter and the proposed strategy operation
5. Conclusion
This paper has analyzed the maximum efficiency operation strategy for the 3LTI in low-voltage and low-power home appliance. Unlike the other well-known three-level inverter such as the three-level NPCI and FCI, the efficiency of the 3LTI is effected by the utilization rate of switches. In the low MI region, the efficiency of the 3LTI is similar to the general three-level inverters since the utilization rate of switches is increased. However, in the high MI region, the efficiency of the 3LTI is similar to the two-level inverter since the utilization rate of switches is decreased. Therefore, compared with the two-level inverter, the 3LTI has together higher and lower efficiency areas according to the MI. To overcome this characteristic, two operation mode selection strategy is proposed for maximum efficiency operation. Based on each mode efficiency, the 3LTI is operated two-level operation mode in low MI, and it is operated three-level operation mode in high MI. As a result, the 3LTI can always obtain the maximum efficiency in all operation areas. The validity of the proposed strategy has been verified by experimental results.
BIO
Seung-Min Shin He received his B.S. and M.S. degrees in Electrical Engineering from Sungkyunkwan University, Suwon, Korea, in 2009 and 2011, respectively. Since 2009, he has studied for Ph.D. degree in electrical Engineering at Sungkyunkwan University. His research interests are electric vehicle drives, power electronics and advanced motor drive systems.
Jung-Hoon Ahn He received the B.S. and the M.S. degrees from Sungkyunkwan University, Suwon, Korea, in 2011 and 2013, respectively. Since 2013, he has worked for his Ph.D in Electrical Engineering at Sungkyunkwan University. His research interests include DC home appliance like future home system, battery management system (BMS), high / low power DC-DC converter for PHEV/EV and advanced motor drive systems.
Byoung-Kuk Lee He received the B.S. and the M.S. degrees from Hanyang University, Seoul, Korea, in 1994 and 1996, respectively and the Ph.D. degree from Texas A&M University, College Station, TX, in 2001, all in electrical engineering. From 2003 to 2005, he has been a Senior Researcher at Power Electronics Group, Korea Electrotechnology Research Institute (KERI), Changwon, Korea. From 2006 Dr. Lee joins at School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea. His research interests include charger for electric vehicles, hybrid renewable energy systems, dc distribution systems for home appliances, power conditioning systems for fuel cells and photovoltaic, modeling and simulation, and power electronics. Prof. Lee is a recipient of Outstanding Scientists of the 21st Century from IBC and listed on 2008 Ed. of Who’s Who in America. Prof. Lee is an Associate Editor in the IEEE Transactions on Industrial Electronics and Power Electronics. He was the General Chair for IEEE Vehicular Power and Propulsion Conference (VPPC) in 2012.
References
ün Emre , Hava Ahmet M. 2009 “A Near-State PWM Method with Reduced Switching Losses and Reduced Common-Mode Voltage for Three-Phase Voltage Source Inverters,” IEEE Trans. Industry Applications 45 (2) 782 - 793    DOI : 10.1109/TIA.2009.2013580
Choudhury Abhijit , Pillay Pragasen , Amar M , Williamson Sheldon S 2014 “Performance Comparison study of Two and Three-Level Inverter for Electric Vehicle Application,” Transportation Electrification Conference and Expo (ITEC), 2014 IEEE Dearborn, USA
Shin Hojoon , Ha Jung-Ik 2014 “Phase Current Reconstructions from DC-Link Currents in Three-Phase Three-Level PWM Inverters,” IEEE Trans. Power Electronics 29 (2) 582 - 593    DOI : 10.1109/TPEL.2013.2257866
Itoh Jun-ichi , Ogura Takumi 2010 “Evaluation of Total Loss for An Inverter and Motor by Applying Modulation Strategies,” Proceedings of IEEE EPE, 2010 Ohrid, Macedonia S12-21 - S12-28
Schweizer M. , Lizama I. , Friedli T. , Kolar J. W. 2012 “Comparison of the chip area usage of 2-level and 3-level voltage source converter Topologies,” Proc. 36th Annu. Conf. IEEE Ind. Electron. 391 - 396
Teichmann R. , Bernet S. 2005 “A comparison of threelevel converters versus two-level converters for lowvoltage drives, tractions, and utility applications,” IEEE Trans. Ind. Appl. 391-396, Nov. 2012 41 (3) 391 - 396
Dordevic O , Jones M , Levi E 2009 “A Comparison of Carrier-Based and Space Vector PWM Technique for the Three-Level Five-Phase Voltage Source Inverter,” IEEE Trans. Industrial Informatics 9 (2) 609 - 619
Schweiser M , Kolar W 2013 “Comparative Evaluation of Advanced Three-Level Inverter / Converter Topologies against Two-Level Systems,” IEEE Trans. Industrial Electronics 60 (12) 5515 - 5527    DOI : 10.1109/TIE.2012.2233698
Padilha Felipe J. C. , Suemitsu Walter Issamu , Bellar Maria Dias , Lourenco Plutarcho Maravilha 2009 “Low-Cost Gate Drive Circuit for Three-level Neutral-Point-Clamped Voltage-Source Inverter,” IEEE Trans. Ind. Electron 56 (4) 1196 - 1204    DOI : 10.1109/TIE.2008.2007554
Felipe J. , Padilha C. 2011 “A Hybrid Cascade Converter Topology with Series-Connected Symmetrical and Asymmetrical Diode-Clamped H-Bridge Cells,” IEEE Trans. Power Electron. 26 (1) 51 - 65    DOI : 10.1109/TPEL.2009.2031115
Padilha Felipe J. C. , Suemitsu Walter Issamu , Bellar Maria Dias , Lourenco Plutarcho Maravilha 2013 “Modified DC-Link Voltage Balancing Algorithm for a 3-Level Neutral Point Clamped (NPC) Traction Inverter Based Electric Vehicle PMSM Drive,” Proc. Annual Conf. of the IEEE Industrial Electronics Society Vienna, Austria 4660 - 4665
Abu-Rub H. , Holtz J. , Rodriguez J. , Baoming G. 2010 “Medium Voltage Multilevel Converters: State of the art, Challenges and Requirements in Industrial Applications,” IEEE Trans. Ind. Electron. 57 (8) 2581 - 2596    DOI : 10.1109/TIE.2010.2043039
Rodriguez J. , Bernet S. , Steimer P. K. , Lizama I. E. 2009 “A Survey on Neutral-Point-Clamped Inverters,” IEEE Trans. Ind. Electron. 57 (7) 2219 - 2230
Sharkh Suleiman M. , Abusara Mohammad A. , Orfanoudakis Georgios I. , Hussain Babar 2014 `Loss Comparison of Two- and Three-Level Inverter Topologies: Power Electronic Converter for Microgrids John Wiley & Sons
Schweizer Mario , Kolar Johann W. 2013 “Design and Implementation of a Highly Efficiency Three-Level T-Type Converter for Low-Voltage Applications,” IEEE Trans. Ind. Electron. 28 (2) 889 - 907
Choi Ui-Min , Lee Kyo-Beum , Blaabjerg Frede 2014 “Diagnosis and Tolerant Strategy of an Open-Switch Fault for T-Type Three-Level Inverter Systems,” IEEE Trans. Ind. Appl. 50 (1) 495 - 508    DOI : 10.1109/TIA.2013.2269531
Komatsu K. , Yatsu M. , Miyashita S. , Okita S. , Nakazawa H. , Igarashi S. , Takahashi Y. , Okuma Y. , Seki Y. , Fujihira T. 2010 “New IGBT Modules for Advanced Neutral-Point-Clamped 3-Level Power Converters,” Conf. Rec. IPEC 523 - 527