A novel parallel threelevel zero voltage switching (ZVS) DC converter is presented for medium voltage applications. The proposed converter includes three subcircuits connected in parallel with the same power switches to share load current and reduce the current stress of passive components at the output side. Thus, the size of the output chokes is reduced and the switch counts in the proposed converter are less that in the conventional parallel threelevel DC/DC converter. Each subcircuit combines one halfbridge converter and one threelevel converter. The transformer secondary windings of these two converters are connected in series in order to reduce the size of output inductor. Due to the threelevel circuit topology, the voltage stress of power switches is equal to
V_{in}
/2. Based on the resonant behavior by the output capacitance of power switches and the leakage inductance (or external inductance) at the transition interval, each switch can be turned on under ZVS. Finally, experiments based on a 2 kW prototype are provided to verify the performance of the proposed converter.
1. Introduction
Threelevel PWM converters/inverters
[1

3]
have been presented for medium voltage applications by using low voltage stress devices such as reactive power compensator, active power filters, AC motor drives and renewable energy conversion systems. Threephase SMPS systems are normally used for medium power applications such as modern cloud power units. In order to meet the power quality demand, threephase power factor correctors with one, four or six power switches have been proposed for past twenty years. Basically power factor correctors are based on boost type voltage conversion. The DC bus voltage after threephase power factor corrector is higher than 750V for threephase 380/480V voltage. In order to realize the low size, light weight and high circuit efficiency SMPS, threelevel converters with zero voltage switching (ZVS) or zero current switching (ZCS) at the desired load range have been proposed in
[4

10]
. Threelevel converters with auxiliary circuits
[11

12]
have been proposed to extend ZVS operation range. However, the design procedure of the auxiliary circuit is very complicated to derive the component parameters of auxiliary circuit. Series resonant converters
[13

16]
with variable switching frequency have been presented to control output voltage with high circuit efficiency. However, the resonant converters have a wider range of switching frequency from light load to full load. Thus, the magnetic components are very difficult to be designed at the optimal condition.
A new parallel ZVS converter is proposed to reduce the switch counts and decrease the output ripple current. In the proposed converter, three DC subcircuits with the same MOSFETs are connected in parallel to reduce the switch counts and decrease the current stress of the transformer windings, rectifier diodes and output inductors. In each subcircuit, one halfbridge converter and one threelevel converter are adopted at high voltage side to limit the voltage stress of power switches at
V_{in}
/2. The transformer secondary windings of two converters are connected in series at low voltage side so that the voltage across the output inductors is reduced and the output inductor ripple current is decreased compared with that in conventional threelevel converter. The output capacitor of active switches and resonant inductor are resonant at the transition interval and MOSFETs can be turned on under ZVS. Finally, experiments with a laboratory prototype are provided to demonstrate the circuit performance.
2. Circuit Configuration
The circuit configurations of conventional halfbridge and fullbridge converters with 400V input voltage are shown in
Figs. 1(a)
and
Fig. 1(b)
respectively for singlephase switching mode power supplies. The phaseshift PWM scheme is normally used in fullbridge DC/DC converter to regulate output voltage and realize ZVS turnon for all power switches. For threephase industry power converters, the DC bus after the threephase power factor corrector is normally equal to between 750 V and 800 V. Thus, threelevel DC/DC converter with ZVS turnon is proposed in
Fig. 1(c)
to reduce the voltage stress of switches at
V_{in}
/2. It is clear that two voltage levels, namely,
V_{in}
/(2
n
) and 0, are observed at the rectified voltage
v_{rect}
. If the voltage variation across the output inductor is decreased, then the current ripple on the output inductor is reduced. Therefore, one more halfbridge converter is added to the conventional threelevel DC converter as shown in
Fig. 1(c)
to reduce the current ripple and voltage variation on the output inductor. The voltage stress of
S_{1}
−
S_{4}
equals
V_{in}
/2.
C_{f1}
,
C_{f2}
,
S_{2}
,
S_{3}
,
T_{2}
and
L_{r2}
operate as an uncontrolled halfbridge converter. The secondary windings of
T_{1}
and
T_{2}
are connected in series so that two voltage levels,
V_{in}
/(2
n_{1}
)+
V_{in}
/(4
n_{2}
) and
V_{in}
/(4
n_{2}
), are generated on the rectified voltage
v_{rect}
. Therefore, the lower ripple current of output inductor is obtained due to lower voltage across the output inductor compared with the conventional threelevel DC converter as shown in
Fig. 1(c)
. For high current applications, the parallel DC converters were normally adopted in industry power converters. These solutions increase the circuit components and will reduce the circuit reliability.
Circuit configurations: (a) conventional PWM halfbridge converter, (b) conventional phaseshift fullbridge converter, and (c) conventional threelevel converter (d) one halfbridge and one threelevel converter.
Fig. 2
gives the circuit configuration of the proposed ZVS converter. The voltage stress of all switches is equal to
V_{in}
/2. The input DC bus voltage
V_{in}
is obtained from a threephase AC/DC converter with power factor correction (PFC). The high DC bus voltage
V_{in}
is normally equal to 750V or 800V for a threephase 380V
_{rms}
/480V
_{rms}
AC/DC converter.
C_{in1}
and
C_{in2}
are input split capacitances to obtain the equal voltages
V_{C1}
=
V_{C2}
=
V_{in}
/2.
S_{1}
−
S_{4}
are power MOSFETs with
V_{in}
/2 voltage stress.
C_{r1}
−
C_{r4}
are output capacitors of
S_{1}
−
S_{4}
, respectively. The average flying capacitor voltages are
V_{Cf1}
=
V_{Cf2}
=
V_{in}
/4.
C_{1a}
−
C_{2b}
are DC blocking capacitors. The average capacitor voltages
V_{C1a}
=
V_{C2a}
=
V_{in}
/2 and
V_{C1b}
=
V_{C2b}
=
V_{in}
/4.
L_{r1a}
−
L_{r3b}
are the resonant inductors.
L_{o1}
−
L_{o3}
are output inductors.
D_{1}
−
D_{6}
are rectifier diodes.
T_{1a}
−
T_{3b}
are isolated transformers.
C_{o}
and
R_{o}
are output capacitor and load resistor, respectively. The proposed converter includes three subcircuits sharing the same power switches
S_{1}
−
S_{4}
, flying capacitors
C_{f1}
and
C_{f2}
, and freewheeling diodes
D_{a}
and
D_{b}
. Each subcircuit includes a threelevel ZVS converter and a halfbridge converter. The secondary windings of two transformers are connected in series. Two voltage levels,
V_{in}
/(2
n_{1}
)+
V_{in}
/(4
n_{2}
) and
V_{in}
/(4
n_{2}
), can be observed on the rectified voltage
v_{rect}
. Thus, low ripple current or switching current on the output inductors
L_{o1}
−
L_{o3}
can be achieved because of the low voltage across the output inductor. The PWM signals of
S_{1}
and
S_{4}
are complementary each other and PWM signals of
S_{2}
and
S_{3}
are also complementary. For subcircuit 1, the components
C_{in1}
,
C_{in2}
,
D_{a}
,
D_{b}
,
C_{f1}
,
C_{f2}
,
S_{1}
−
S_{4}
,
C_{r1}
−
C_{r4}
,
C_{1a}
,
L_{r1a}
and
T_{1a}
are the basic threelevel PWM converter. Three voltage levels
V_{in}
,
V_{in}
/2 and 0 are generated on the AC terminal voltage
v_{ab}
. The average voltage of
C_{1a}
equals
V_{in}
/2 so that three voltage levels
V_{in}
/2, 0 and −
V_{in}
/2 are generated on the primary side of
T_{1a}
and inductor
L_{r1a}
. The components
C_{f1}
,
C_{f2}
,
S_{2}
,
S_{3}
,
C_{r2}
,
C_{r3}
,
C_{1b}
,
L_{r1b}
and
T_{1b}
are an uncontrolled halfbridge converter with 50% duty cycle. Two voltage levels
V_{in}
/4 and −
V_{in}
/4 are generated on the primary side of
T_{1b}
and inductor
L_{r1b}
. In the same manner,
V_{in}
/2, 0 and −
V_{in}
/2 are generated on
T_{2a}
and
L_{r2a}
in subcircuit 2 and on
T_{3a}
and
L_{r3a}
in subcircuit 3.
V_{in}
/4 and −
V_{in}
/4 are generated on
T_{2b}
and
L_{r2b}
in subcircuit 2 and on
T_{2b}
and
L_{r3b}
in subcircuit 3. The current rating of output inductors
L_{o1}
−
L_{o2}
equals
I_{o}
/3. The centertapped rectifiers are employed at the secondary side to have one diode conduction loss. The output capacitances of
S_{1}
–
S_{4}
and the resonant inductance are resonant at the transition interval. Therefore,
S_{1}
–
S_{4}
can be turned on under ZVS.
Circuit configuration of the proposed ZVS converter.
3. Operation Principle
The operation principle and circuit analysis are discussed in this section. In order to simplify the system analysis, the following are assumptions in the proposed converter.

(1) DiodesD1−D6and clamped diodesDaDbare ideal,

(2) MOSFETsS1−S4are ideal except for the internal antiparallel diode of it and the output capacitorsCr1−Cr4,

(3)Lo1=Lo2=Lo3=Lo,Lr1a=Lr2a=Lr3a=Lra,Lr1b=Lr2b=Lr3b=Lrb,

(4) Turns ratio ofT1a−T3aisnand turns ratio ofT1b−T3bisn/2,

(5)Cr1=Cr2=Cr3=Cr4=Cr,C1a=C2a=Ca,C1b=C2b=CbandCa,Cb>>Cr,

(6) The average capacitor voltagesVC1a=VC2a=Vin/2,VCin1=VCin2=Vin/2 andVC1b=VC2b=VCf1=VCf2=Vin/4,

(7)Cois large enough to be considered as a constant output voltage,

(8) The energy stored in the resonant inductances is greater than the energy stored in the resonant capacitances so that the ZVS turnon of all switches can be achieved.
Based on the on/off states of
S_{1}
−
S_{4}
,
D_{a}
−
D_{b}
and
D_{1}
−
D_{6}
, there are ten operation modes in each switching period.
Fig. 3
shows the main key waveforms in the proposed converter in every switching cycle. However, the operation modes in the second half cycle are symmetry with respectively to the operation modes in the first half cycle. Thus, only first five modes are discussed and their topological states are given in
Fig. 4
. Prior to
t_{0}
,
S_{1}
and
S_{2}
and diodes
D_{1}
−
D_{6}
are conducting. Inductor currents
i_{Lr1a}
and
i_{Lr1b}
are negative, and
i_{Lr2a}
,
i_{Lr2b}
,
i_{Lr3a}
and
i_{Lr3b}
are positive.
Key waveforms of the proposed converter.
Operation modes of the proposed converter during the first half cycle (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5.
Mode 1 [t_{0}≤t<t_{1}]:
Mode 1 begins at
t_{0}
when the commutation of
D_{1}

D_{6}
is finished and
i_{D1}
=
i_{D4}
=
i_{D6}
=
0
.
S_{1}
and
S_{2}
are conducting. Input power is transferred to the output load through diodes
D_{2}
,
D_{3}
and
D_{5}
. The AC terminal voltages
v_{ab}
=
v_{ac}
=0,
v_{cd}
=
V_{in}
/2,
v_{ce}
=
V_{in}
,
v_{cf}
=
v_{Cf1}
=
V_{in}
/4 and
v_{cg}
=
V_{in}
/2. The voltages across (
T_{1a}
and
L_{r1a}
) and (
T_{1b}
and
L_{r1b}
) are negative, and the voltages across (
T_{2a}
and
L_{r2a}
), (
T_{2b}
and
L_{r2b}
), (
T_{3a}
and
L_{r3a}
) and (
T_{3b}
and
L_{r3b}
) are positive. The output inductor voltages
v_{Lo1}
=
v_{Lo3}
=
v_{Lo5}
=
V_{in}/n
−
V_{o}
>0. In this mode,
i_{Lo1}
−
i_{Lo3}
increase,
i_{Lr1a}
and
i_{Lr1b}
decrease, and
i_{Lr2a}
,
i_{Lr2b}
,
i_{Lr3a}
and
i_{Lr3b}
increase. Power is delivered from
V_{in}
to
R_{o}
during this mode.
Mode 2 [t_{1}≤t<t_{2}]:
Mode 2 begins at
t_{1}
when
S_{1}
is turned off. Since
i_{Lr1a}
<0,
i_{Lr1b}
<0 and
i_{Lr2a}
−
i_{Lr3b}
are positive,
C_{r1}
and
C_{r4}
are charged and discharged via capacitors
C_{f1}
and
C_{f2}
. Since the charged time of
C_{r1}
is very soon and
i_{Lr1a}
−
i_{Lr3b}
are almost constant during this mode. The ZVS turnon condition of
S_{4}
can be approximately expressed as:
At
t_{2}
,
C_{r1}
is charged to
V_{in}
/2 and
C_{r4}
is discharged to zero voltage. Since
i_{S4}
(
t_{2}
) is negative, the antiparallel diode of
S_{4}
is conducting. The time interval Δ
t_{12}
in this mode can be expressed as:
where
i_{Lo1,max}
−
i_{Lo3,max}
are the maximum value of inductor currents
i_{Lo1}
−
i_{Lo3}
, respectively.
Mode 3 [t_{2}≤t<t_{3}]:
Mode 3 begins at time
t_{1}
when
v_{Cr1}
=
V_{in}
/2 and
v_{Cr4}
=0. Therefore,
D_{a}
is conducting. The AC terminal voltages
v_{ab}
=
v_{ac}
=
V_{in}
/2,
v_{cd}
=
v_{ce}
=
V_{in}
/2,
v_{cg}
=0 and
v_{cf}
=
v_{Cf1}
=
V_{in}
/4. Since the average capacitor voltages
V_{C1a}
=
V_{C2a}
=
V_{in}
/2 and
V_{C1b}
=
V_{C2b}
=
V_{Cf1}
=
V_{Cf2}
=
V_{in}
/4, the voltages across (
T_{1a}
and
L_{r1a}
), (
T_{2a}
and
L_{r2a}
) and (
T_{3a}
and
L_{r3a}
) are equal to zero and the voltages across (
T_{1b}
and
L_{r1b}
), (
T_{2b}
and
L_{r2b}
) and (
T_{3b}
and
L_{r3b}
) are equal to −
V_{in}
/4,
V_{in}
/4 and
V_{in}
/4, respectively. The secondary rectified voltages
v_{rect1}
=
v_{rect2}
=v
v_{rect3}
=
V_{in}
/(2
n
). The output inductor voltages
v_{Lo1}
=
v_{Lo2}
=
v_{Lo3}
=
V_{in}
/(2
n
)
V_{o}
<0. Inductor currents
i_{Lo1}
−
i_{Lo3}
are decreased during this mode.
Mode 4 [t_{3}≤t<t_{4}]:
Mode 4 begins at
t_{3}
when
S_{2}
is turned off. Since
i_{Lr1a}
<0,
i_{Lr1b}
<0,
i_{Lr2a}
>0,
i_{Lr2b}
>0,
i_{Lr3a}
>0 and
i_{Lr3b}
>0,
C_{r2}
and
C_{r3}
are charged and discharged, respectively. The ZVS turnon condition of
S_{3}
is given as:
At time
t_{4}
,
C_{r3}
is discharged to zero voltage. The time interval in mode 4 is given as:
Mode 5 [t_{4}≤t<t_{5}]:
Mode 5 begins at
t_{4}
when
C_{r3}
is discharged to zero voltage. Since
i_{Lr1a}
(
t_{4}
)+
i_{Lr1b}
(
t_{4}
) −
i_{Lr2a}
(
t_{4}
) −
i_{Lr2b}
(
t_{4}
) −
i_{Lr3a}
(
t_{4}
) −
i_{Lr3b}
(
t_{4}
)<0, the antiparallel diode of
S_{3}
is conducting. Therefore,
S_{3}
can be turned on at this moment under ZVS. During this mode,
D_{1}
−
D_{6}
are in the commutation state and
i_{Lo1}
−
i_{Lo3}
are decreasing with the slope of −
V_{o}
/
L_{o}
. The primary inductor voltages
v_{Lr1a}
=
V_{in}
−
v_{C1a}
≈
V_{in}
/2,
v_{Lr1b}
=
v_{Cf}
−
v_{C1b}
≈
V_{in}
/4,
v_{Lr2a}
=
v_{Lr3a}
≈ −
V_{in}
/2 and
v_{Lr2b}
=
v_{Lr3b}
≈ −
V_{in}
/4. Thus, the current slopes of
L_{r1a}
−
L_{r3b}
are expressed as:
The current slopes of
D_{1}
,
D_{4}
and
D_{6}
are expressed as:
In the same manner, the current slope of
D_{2}
,
D_{3}
and
D_{5}
are given as:
From (7) and (8), the relationship of
L_{ra}
and
L_{rb}
can be derived as
L_{ra}
=4
L_{rb}
. At time
t_{5}
,
i_{D2}
,
i_{D3}
and
i_{D5}
are decreased to zero. In this mode, the current variations on
L_{r1a}
,
L_{r2a}
and
L_{r3a}
are Δ
i
_{Lr1a}
= Δ
i
_{Lr2a}
= Δ
i
_{Lr3a}
≈
I_{o}
/(3
n
) . However, the current variations on
L_{r1b}
,
L_{r2b}
and
L_{r2b}
are Δ
i
_{Lr1b}
= Δ
i
_{Lr2b}
= Δ
i
_{Lr3b}
≈ 2
I_{o}
/(3
n
) . Thus, the time interval during this mode is expressed as Δ
t
_{45}
=
t
_{5}
−
t
_{4}
≈ 2
L_{ra} I_{o}
/ (3
nV_{in}
) . Although
S_{3}
and
S_{4}
are conducting, diodes
D_{1}
−
D_{6}
are in the commutation state. Thus,
v_{rect1}
−
v_{rect3}
are all equal to zero voltage. No power is transferred from
V_{in}
to
R_{o}
during this mode. The duty loss in mode 5 is expressed as:
where
T_{s}
and
f_{s}
are the switching period and switching frequency, respectively.
4. Circuit Characteristics
To simplify the discussions of the circuit characteristics, the charge and discharge time of
S_{1}

S_{4}
are neglected. Thus, only modes 1, 3, 5, 6, 8 and 10 are considered in the following discussions. In mode 3,
v_{Cin1}
+
v_{Cin2}
=
V_{in}
and
v_{Cf1}
+
v_{Cf2}
=
v_{Cin2}
. Similarly,
v_{Cf1}
+
v_{Cf2}
=
v_{Cin1}
in mode 8. Thus, the input capacitor voltages are obtained as
v_{Cin1}
=
v_{Cin2}
=
v_{Cf1}
+
v_{Cf2}
=
V_{in}
/2 and
C_{in1}
and
C_{in2}
are automatically balanced in a switching cycle. Due to the voltsecond balance across (
L_{r1a}
and
T_{1a}
), (
L_{r1b}
and
T_{1b}
), (
L_{r2a}
and
T_{2a}
), (
L_{r2b}
and
T_{2b}
) and (
L_{r3b}
and
T_{3b}
) in steady state, the average capacitor voltages
V_{C1a}

V_{Cf2}
are derived in (10).
Similarly, the output voltage
V_{o}
can be obtained in (11) based on the voltsecond balance on
L_{o1}
−
L_{o3}
.
where
V_{f}
is the voltage drop on diode
D_{1}
−
D_{6}
, and
d
is the duty ratio of the AC side voltages
v_{ac}
and
v_{ce}
when
S_{1}
and
S_{2}
are conducting. In steady state, the average inductor currents are balanced
I_{Lo1}
=
I_{Lo2}
=
I_{Lo3}
=
I_{o}
/3. The ripple current on
L_{o1}
−
L_{o3}
is expressed as Δ
i_{Lo}
.
The maximum and minimum inductor currents
i_{Lo,max}
and
i_{Lo,min}
of
L_{o1}
−
L_{o3}
can be given as:
Since the average currents of
C_{r1a}
−
C_{r2b}
are zero and the average magnetizing currents of
T_{1a}
−
T_{3b}
are zero, the magnetizing ripple currents can be obtained in mode 1.
where
L_{ma}
and
L_{mb}
are the magnetizing inductances of
T_{1a}
−
T_{3a}
and
T_{1b}
−
T_{3b}
, respectively. The average currents of
D_{1}
−
D_{6}
are equal to
I_{o}
/6. The voltage stresses of
D_{1}
−
D_{6}
are equal to 2
V_{in}
/
n
. If the ripple currents of
S_{1}
−
S_{4}
can be neglected, the
rms
currents of
S_{1}
−
S_{4}
are expressed in (17).
The voltage stress of
S_{1}
−
S_{4}
equals
V_{in}
/2. In mode 2, the inductor currents
i_{Lr1a}
(
t_{1}
),
i_{Lr2a}
(
t_{1}
) and
i_{Lr3a}
(
t_{1}
) are expressed as:
Based on (1), (18) and (19), the necessary resonant inductance
L_{ra}
is given in (20) to achieve ZVS turnon for
S_{1}
and
S_{4}
.
In mode 4, the inductor currents
i_{Lr1a}
(
t_{3}
) −
i_{Lr3b}
(
t_{3}
) are approximately expressed as:
Based on (3) and (21)(24), the necessary resonant inductance
L_{rb}
is given in (25) to achieve ZVS turnon for
S_{2}
and
S_{3}
.
5. Experimental Results
In this section, experiments are presented to verify the effectiveness of the proposed converter. The specifications of the proposed converter are
V_{in}
: 750V800V,
V_{o}
=48V,
I_{o}
=40A,
f_{s}
=100kHz. The component parameters of the prototype circuit are
S_{1}
−
S_{4}
: IRFP460, turns ratio of
T_{1a}
,
T_{2a}
,
T_{3a}
: 48 turns/4 turns, turns ratio of
T_{1b}
,
T_{2b}
,
T_{3b}
: 24 turns/4 turns,
L_{ma}
=4.8mH,
L_{mb}
=1.2mH,
L_{ra}
=40μH,
L_{rb}
=10μH,
L_{o}
=30μH,
C_{a}
=
C_{b}
=0.4μF,
C_{in1}
=
C_{in2}
=
C_{f1}
=
C_{f2}
= 0.47μF,
D_{a}
−
D_{b}
: 30ETH06,
D_{1}
−
D_{6}
: KCU30A30 and
C_{o}
=4000μF. The measured results of the gate waveforms of
S_{1}
−
S_{4}
at 30% and 100% loads under
V_{in}
=750V are shown in
Fig. 5
. Similarly, the measured gate voltages of
S_{1}
−
S_{4}
at 30% and 100% loads under
V_{in}
=800V are illustrated in
Fig. 6
. The measured gate voltage, drain voltage and switch current of
S_{1}
−
S_{4}
at 30% and 100% loads under
V_{in}
=800V are shown in
Fig. 7
. From the measured results shown in
Fig. 7
,
S_{1}
−
S_{4}
are all turned on under ZVS from 30% load to full load. The measured waveforms of AC side voltages
v_{ac}
,
v_{ce}
and
v_{cg}
and inductor currents
i_{Lr1a}
−
i_{Lr3b}
at full load are given in
Fig. 8
. There are three voltage levels,
V_{in}
,
V_{in}
/2 and 0, on AC side voltages
v_{ac}
and
v_{ce}
. When
v_{ac}
=0 and
v_{ce}
=
V_{in}
,
i_{Lr1a}
and
i_{Lr1b}
decrease and
i_{Lr2a}
−
i_{Lr3b}
increase. In the same manner,
i_{Lr1a}
and
i_{Lr1b}
increase and
i_{Lr2a}
−
i_{Lr3b}
decrease if
v_{ac}
=
V_{in}
and
v_{ce}
=0. The measured waveforms of the capacitor voltages
v_{C1a}
−
v_{C2b}
and two flying capacitor voltages
v_{Cf1}
and
v_{Cf2}
at full load are shown in
Fig. 9
. The average capacitor voltages
v_{C1a}
and
v_{C2a}
equal
V_{in}
/2 and
v_{C1b}
,
v_{C2b}
,
v_{Cf1}
and
v_{Cf2}
equal
V_{in}
/4. The measured results of diode currents and output inductor currents at full load are given in
Fig. 10
. The output currents
i_{Lo1}
−
i_{Lo3}
are balanced.
Fig. 11
gives the measured circuit efficiencies of the proposed converter at different load conditions.
Measured gate voltage waveforms of S_{1}  S_{4} at V_{in}= 750V and (a) 30% load (b) full load.
Measured gate voltage waveforms of S_{1}  S_{4} at V_{in}= 800V and (a) 30% load (b) full load.
Measured waveforms of gate voltage, drain voltage and switch current (a) S_{1} at 30% load (b) S_{1} at 100% load (c) S_{2} at 30% load (d) S_{2} at 100% load (e) S_{3} at 30% load (f) S_{3} at 100% load (g) S_{4} at 30% load (h) S_{4} at 100% load.
Measured results of the AC side voltages and primary side inductor currents at full load and (a) V_{in}=750V (b) V_{in}=800V.
Measured capacitor voltages v_{C1a}  v_{C2b}, v_{Cf1} and v_{Cf2} at full load and (a) V_{in}=750V (b) V_{in}=800V.
Measured waveforms of diode currents and output inductor currents at full load and (a) V_{in}=750V (b) V_{in}=800V.
Measured circuit efficiencies at different load conditions.
6. Conclusion
This paper presents a new ZVS DC/DC converter with three subcircuits for high input voltage and high load current applications. The proposed converter has the features of ZVS turnon of power switches from 30% load to full load, low current stress of rectifier diodes and magnetic components and low voltage stress of MOSFETs. Threelevel diode clamped circuit is adopted to limit the voltage stress of power MOSFETs at onehalf of input voltage and two flying capacitors are used to balance input split capacitor voltages. For high load current applications, three circuit cells with the same power switches are used and connected in parallel at low voltage side to reduce current stress of transformer windings, rectifier diodes and output inductors. Each circuit cell has one halfbridge converter and one threelevel converter. The transformer secondary windings of two converters are connected in series to reduce output inductor voltage so that output inductor current ripple is reduced compared with that in the conventional threelevel PWM converter. Based on the resonant behavior at the transition interval, all MOSFETs can be turned on under ZVS at the designed load ranges. Thus, the conduction losses on MOSFETs can be reduced. Two centertapped rectifiers are used at the secondary side to have only one diode conduction loss. The main contributions of the proposed converter are low output inductor current ripple, less switch counts and low switching losses compared with the conventional parallel threelevel DC/DC converter. Finally, experiments are provided to demonstrate the circuit performance.
Acknowledgements
This research is supported by the National Science Council of Taiwan under Grant NSC1022221E224022 MY3
BIO
BorRen Lin received the B.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and the M.S. and Ph.D. degrees in electrical engineering from the University of MissouriColumbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings — Power Electronics and the Journal of Power Electronics. His main research interests include powerfactor correction, multilevel converters, active power filters, and softswitching converters. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of the Research Excellence Awards in 2004, 2005, 2007 and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, the IEEE  Power Electronics and Drive Systems 2009 Conference, and the 2014 IEEEInternational Conference Industrial Technology.
JengYu Chen is currently working toward his M.S. in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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