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Analysis of a New Parallel Three-Level Zero-Voltage Switching DC Converter
Analysis of a New Parallel Three-Level Zero-Voltage Switching DC Converter
Journal of Electrical Engineering and Technology. 2015. Jan, 10(1): 128-137
Copyright © 2015, The Korean Institute of Electrical Engineers
This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0/)which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
  • Received : April 24, 2014
  • Accepted : July 21, 2014
  • Published : January 01, 2015
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About the Authors
Bor-Ren Lin
Corresponding Author: Department of Electrical Engineering, National Yunlin University of Science and Technology, Taiwan. (linbr@yuntech.edu.tw)
Jeng-Yu Chen
Department of Electrical Engineering, National Yunlin University of Science and Technology, Taiwan.

Abstract
A novel parallel three-level zero voltage switching (ZVS) DC converter is presented for medium voltage applications. The proposed converter includes three sub-circuits connected in parallel with the same power switches to share load current and reduce the current stress of passive components at the output side. Thus, the size of the output chokes is reduced and the switch counts in the proposed converter are less that in the conventional parallel three-level DC/DC converter. Each sub-circuit combines one half-bridge converter and one three-level converter. The transformer secondary windings of these two converters are connected in series in order to reduce the size of output inductor. Due to the three-level circuit topology, the voltage stress of power switches is equal to Vin /2. Based on the resonant behavior by the output capacitance of power switches and the leakage inductance (or external inductance) at the transition interval, each switch can be turned on under ZVS. Finally, experiments based on a 2 kW prototype are provided to verify the performance of the proposed converter.
Keywords
1. Introduction
Three-level PWM converters/inverters [1 - 3] have been presented for medium voltage applications by using low voltage stress devices such as reactive power compensator, active power filters, AC motor drives and renewable energy conversion systems. Three-phase SMPS systems are normally used for medium power applications such as modern cloud power units. In order to meet the power quality demand, three-phase power factor correctors with one, four or six power switches have been proposed for past twenty years. Basically power factor correctors are based on boost type voltage conversion. The DC bus voltage after three-phase power factor corrector is higher than 750V for three-phase 380/480V voltage. In order to realize the low size, light weight and high circuit efficiency SMPS, three-level converters with zero voltage switching (ZVS) or zero current switching (ZCS) at the desired load range have been proposed in [4 - 10] . Three-level converters with auxiliary circuits [11 - 12] have been proposed to extend ZVS operation range. However, the design procedure of the auxiliary circuit is very complicated to derive the component parameters of auxiliary circuit. Series resonant converters [13 - 16] with variable switching frequency have been presented to control output voltage with high circuit efficiency. However, the resonant converters have a wider range of switching frequency from light load to full load. Thus, the magnetic components are very difficult to be designed at the optimal condition.
A new parallel ZVS converter is proposed to reduce the switch counts and decrease the output ripple current. In the proposed converter, three DC sub-circuits with the same MOSFETs are connected in parallel to reduce the switch counts and decrease the current stress of the transformer windings, rectifier diodes and output inductors. In each sub-circuit, one half-bridge converter and one three-level converter are adopted at high voltage side to limit the voltage stress of power switches at Vin /2. The transformer secondary windings of two converters are connected in series at low voltage side so that the voltage across the output inductors is reduced and the output inductor ripple current is decreased compared with that in conventional three-level converter. The output capacitor of active switches and resonant inductor are resonant at the transition interval and MOSFETs can be turned on under ZVS. Finally, experiments with a laboratory prototype are provided to demonstrate the circuit performance.
2. Circuit Configuration
The circuit configurations of conventional half-bridge and full-bridge converters with 400V input voltage are shown in Figs. 1(a) and Fig. 1(b) respectively for single-phase switching mode power supplies. The phase-shift PWM scheme is normally used in full-bridge DC/DC converter to regulate output voltage and realize ZVS turn-on for all power switches. For three-phase industry power converters, the DC bus after the three-phase power factor corrector is normally equal to between 750 V and 800 V. Thus, three-level DC/DC converter with ZVS turn-on is proposed in Fig. 1(c) to reduce the voltage stress of switches at Vin /2. It is clear that two voltage levels, namely, Vin /(2 n ) and 0, are observed at the rectified voltage vrect . If the voltage variation across the output inductor is decreased, then the current ripple on the output inductor is reduced. Therefore, one more half-bridge converter is added to the conventional three-level DC converter as shown in Fig. 1(c) to reduce the current ripple and voltage variation on the output inductor. The voltage stress of S1 S4 equals Vin /2. Cf1 , Cf2 , S2 , S3 , T2 and Lr2 operate as an uncontrolled half-bridge converter. The secondary windings of T1 and T2 are connected in series so that two voltage levels, Vin /(2 n1 )+ Vin /(4 n2 ) and Vin /(4 n2 ), are generated on the rectified voltage vrect . Therefore, the lower ripple current of output inductor is obtained due to lower voltage across the output inductor compared with the conventional three-level DC converter as shown in Fig. 1(c) . For high current applications, the parallel DC converters were normally adopted in industry power converters. These solutions increase the circuit components and will reduce the circuit reliability.
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Circuit configurations: (a) conventional PWM halfbridge converter, (b) conventional phase-shift fullbridge converter, and (c) conventional three-level converter (d) one half-bridge and one three-level converter.
Fig. 2 gives the circuit configuration of the proposed ZVS converter. The voltage stress of all switches is equal to Vin /2. The input DC bus voltage Vin is obtained from a three-phase AC/DC converter with power factor correction (PFC). The high DC bus voltage Vin is normally equal to 750V or 800V for a three-phase 380V rms /480V rms AC/DC converter. Cin1 and Cin2 are input split capacitances to obtain the equal voltages VC1 = VC2 = Vin /2. S1 S4 are power MOSFETs with Vin /2 voltage stress. Cr1 Cr4 are output capacitors of S1 S4 , respectively. The average flying capacitor voltages are VCf1 = VCf2 = Vin /4. C1a C2b are DC blocking capacitors. The average capacitor voltages VC1a = VC2a = Vin /2 and VC1b = VC2b = Vin /4. Lr1a Lr3b are the resonant inductors. Lo1 Lo3 are output inductors. D1 D6 are rectifier diodes. T1a T3b are isolated transformers. Co and Ro are output capacitor and load resistor, respectively. The proposed converter includes three sub-circuits sharing the same power switches S1 S4 , flying capacitors Cf1 and Cf2 , and freewheeling diodes Da and Db . Each sub-circuit includes a three-level ZVS converter and a half-bridge converter. The secondary windings of two transformers are connected in series. Two voltage levels, Vin /(2 n1 )+ Vin /(4 n2 ) and Vin /(4 n2 ), can be observed on the rectified voltage vrect . Thus, low ripple current or switching current on the output inductors Lo1 Lo3 can be achieved because of the low voltage across the output inductor. The PWM signals of S1 and S4 are complementary each other and PWM signals of S2 and S3 are also complementary. For sub-circuit 1, the components Cin1 , Cin2 , Da , Db , Cf1 , Cf2 , S1 S4 , Cr1 Cr4 , C1a , Lr1a and T1a are the basic three-level PWM converter. Three voltage levels Vin , Vin /2 and 0 are generated on the AC terminal voltage vab . The average voltage of C1a equals Vin /2 so that three voltage levels Vin /2, 0 and − Vin /2 are generated on the primary side of T1a and inductor Lr1a . The components Cf1 , Cf2 , S2 , S3 , Cr2 , Cr3 , C1b , Lr1b and T1b are an uncontrolled half-bridge converter with 50% duty cycle. Two voltage levels Vin /4 and − Vin /4 are generated on the primary side of T1b and inductor Lr1b . In the same manner, Vin /2, 0 and − Vin /2 are generated on T2a and Lr2a in sub-circuit 2 and on T3a and Lr3a in sub-circuit 3. Vin /4 and − Vin /4 are generated on T2b and Lr2b in sub-circuit 2 and on T2b and Lr3b in sub-circuit 3. The current rating of output inductors Lo1 Lo2 equals Io /3. The center-tapped rectifiers are employed at the secondary side to have one diode conduction loss. The output capacitances of S1 S4 and the resonant inductance are resonant at the transition interval. Therefore, S1 S4 can be turned on under ZVS.
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Circuit configuration of the proposed ZVS converter.
3. Operation Principle
The operation principle and circuit analysis are discussed in this section. In order to simplify the system analysis, the following are assumptions in the proposed converter.
  • (1) DiodesD1−D6and clamped diodesDa-Dbare ideal,
  • (2) MOSFETsS1−S4are ideal except for the internal anti-parallel diode of it and the output capacitorsCr1−Cr4,
  • (3)Lo1=Lo2=Lo3=Lo,Lr1a=Lr2a=Lr3a=Lra,Lr1b=Lr2b=Lr3b=Lrb,
  • (4) Turns ratio ofT1a−T3aisnand turns ratio ofT1b−T3bisn/2,
  • (5)Cr1=Cr2=Cr3=Cr4=Cr,C1a=C2a=Ca,C1b=C2b=CbandCa,Cb>>Cr,
  • (6) The average capacitor voltagesVC1a=VC2a=Vin/2,VCin1=VCin2=Vin/2 andVC1b=VC2b=VCf1=VCf2=Vin/4,
  • (7)Cois large enough to be considered as a constant output voltage,
  • (8) The energy stored in the resonant inductances is greater than the energy stored in the resonant capacitances so that the ZVS turn-on of all switches can be achieved.
Based on the on/off states of S1 S4 , Da Db and D1 D6 , there are ten operation modes in each switching period. Fig. 3 shows the main key waveforms in the proposed converter in every switching cycle. However, the operation modes in the second half cycle are symmetry with respectively to the operation modes in the first half cycle. Thus, only first five modes are discussed and their topological states are given in Fig. 4 . Prior to t0 , S1 and S2 and diodes D1 D6 are conducting. Inductor currents iLr1a and iLr1b are negative, and iLr2a , iLr2b , iLr3a and iLr3b are positive.
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Key waveforms of the proposed converter.
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Operation modes of the proposed converter during the first half cycle (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5.
Mode 1 [t0t<t1]: Mode 1 begins at t0 when the commutation of D1 - D6 is finished and iD1 = iD4 = iD6 = 0 . S1 and S2 are conducting. Input power is transferred to the output load through diodes D2 , D3 and D5 . The AC terminal voltages vab = vac =0, vcd = Vin /2, vce = Vin , vcf = vCf1 = Vin /4 and vcg = Vin /2. The voltages across ( T1a and Lr1a ) and ( T1b and Lr1b ) are negative, and the voltages across ( T2a and Lr2a ), ( T2b and Lr2b ), ( T3a and Lr3a ) and ( T3b and Lr3b ) are positive. The output inductor voltages vLo1 = vLo3 = vLo5 = Vin/n Vo >0. In this mode, iLo1 iLo3 increase, iLr1a and iLr1b decrease, and iLr2a , iLr2b , iLr3a and iLr3b increase. Power is delivered from Vin to Ro during this mode.
Mode 2 [t1t<t2]: Mode 2 begins at t1 when S1 is turned off. Since iLr1a <0, iLr1b <0 and iLr2a iLr3b are positive, Cr1 and Cr4 are charged and discharged via capacitors Cf1 and Cf2 . Since the charged time of Cr1 is very soon and iLr1a iLr3b are almost constant during this mode. The ZVS turn-on condition of S4 can be approximately expressed as:
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At t2 , Cr1 is charged to Vin /2 and Cr4 is discharged to zero voltage. Since iS4 ( t2 ) is negative, the anti-parallel diode of S4 is conducting. The time interval Δ t12 in this mode can be expressed as:
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where iLo1,max iLo3,max are the maximum value of inductor currents iLo1 iLo3 , respectively.
Mode 3 [t2t<t3]: Mode 3 begins at time t1 when vCr1 = Vin /2 and vCr4 =0. Therefore, Da is conducting. The AC terminal voltages vab = vac = Vin /2, vcd = vce = Vin /2, vcg =0 and vcf = vCf1 = Vin /4. Since the average capacitor voltages VC1a = VC2a = Vin /2 and VC1b = VC2b = VCf1 = VCf2 = Vin /4, the voltages across ( T1a and Lr1a ), ( T2a and Lr2a ) and ( T3a and Lr3a ) are equal to zero and the voltages across ( T1b and Lr1b ), ( T2b and Lr2b ) and ( T3b and Lr3b ) are equal to − Vin /4, Vin /4 and Vin /4, respectively. The secondary rectified voltages vrect1 = vrect2 =v vrect3 = Vin /(2 n ). The output inductor voltages vLo1 = vLo2 = vLo3 = Vin /(2 n )- Vo <0. Inductor currents iLo1 iLo3 are decreased during this mode.
Mode 4 [t3t<t4]: Mode 4 begins at t3 when S2 is turned off. Since iLr1a <0, iLr1b <0, iLr2a >0, iLr2b >0, iLr3a >0 and iLr3b >0, Cr2 and Cr3 are charged and discharged, respectively. The ZVS turn-on condition of S3 is given as:
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At time t4 , Cr3 is discharged to zero voltage. The time interval in mode 4 is given as:
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Mode 5 [t4t<t5]: Mode 5 begins at t4 when Cr3 is discharged to zero voltage. Since iLr1a ( t4 )+ iLr1b ( t4 ) − iLr2a ( t4 ) − iLr2b ( t4 ) − iLr3a ( t4 ) − iLr3b ( t4 )<0, the anti-parallel diode of S3 is conducting. Therefore, S3 can be turned on at this moment under ZVS. During this mode, D1 D6 are in the commutation state and iLo1 iLo3 are decreasing with the slope of − Vo / Lo . The primary inductor voltages vLr1a = Vin vC1a Vin /2, vLr1b = vCf vC1b Vin /4, vLr2a = vLr3a ≈ − Vin /2 and vLr2b = vLr3b ≈ − Vin /4. Thus, the current slopes of Lr1a Lr3b are expressed as:
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The current slopes of D1 , D4 and D6 are expressed as:
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In the same manner, the current slope of D2 , D3 and D5 are given as:
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From (7) and (8), the relationship of Lra and Lrb can be derived as Lra =4 Lrb . At time t5 , iD2 , iD3 and iD5 are decreased to zero. In this mode, the current variations on Lr1a , Lr2a and Lr3a are Δ i Lr1a = Δ i Lr2a = Δ i Lr3a Io /(3 n ) . However, the current variations on Lr1b , Lr2b and Lr2b are Δ i Lr1b = Δ i Lr2b = Δ i Lr3b ≈ 2 Io /(3 n ) . Thus, the time interval during this mode is expressed as Δ t 45 = t 5 t 4 ≈ 2 Lra Io / (3 nVin ) . Although S3 and S4 are conducting, diodes D1 D6 are in the commutation state. Thus, vrect1 vrect3 are all equal to zero voltage. No power is transferred from Vin to Ro during this mode. The duty loss in mode 5 is expressed as:
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where Ts and fs are the switching period and switching frequency, respectively.
4. Circuit Characteristics
To simplify the discussions of the circuit characteristics, the charge and discharge time of S1 - S4 are neglected. Thus, only modes 1, 3, 5, 6, 8 and 10 are considered in the following discussions. In mode 3, vCin1 + vCin2 = Vin and vCf1 + vCf2 = vCin2 . Similarly, vCf1 + vCf2 = vCin1 in mode 8. Thus, the input capacitor voltages are obtained as vCin1 = vCin2 = vCf1 + vCf2 = Vin /2 and Cin1 and Cin2 are automatically balanced in a switching cycle. Due to the volt-second balance across ( Lr1a and T1a ), ( Lr1b and T1b ), ( Lr2a and T2a ), ( Lr2b and T2b ) and ( Lr3b and T3b ) in steady state, the average capacitor voltages VC1a - VCf2 are derived in (10).
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Similarly, the output voltage Vo can be obtained in (11) based on the volt-second balance on Lo1 Lo3 .
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where Vf is the voltage drop on diode D1 D6 , and d is the duty ratio of the AC side voltages vac and vce when S1 and S2 are conducting. In steady state, the average inductor currents are balanced ILo1 = ILo2 = ILo3 = Io /3. The ripple current on Lo1 Lo3 is expressed as Δ iLo .
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The maximum and minimum inductor currents iLo,max and iLo,min of Lo1 Lo3 can be given as:
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Since the average currents of Cr1a Cr2b are zero and the average magnetizing currents of T1a T3b are zero, the magnetizing ripple currents can be obtained in mode 1.
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where Lma and Lmb are the magnetizing inductances of T1a T3a and T1b T3b , respectively. The average currents of D1 D6 are equal to Io /6. The voltage stresses of D1 D6 are equal to 2 Vin / n . If the ripple currents of S1 S4 can be neglected, the rms currents of S1 S4 are expressed in (17).
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The voltage stress of S1 S4 equals Vin /2. In mode 2, the inductor currents iLr1a ( t1 ), iLr2a ( t1 ) and iLr3a ( t1 ) are expressed as:
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Based on (1), (18) and (19), the necessary resonant inductance Lra is given in (20) to achieve ZVS turn-on for S1 and S4 .
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In mode 4, the inductor currents iLr1a ( t3 ) − iLr3b ( t3 ) are approximately expressed as:
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Based on (3) and (21)-(24), the necessary resonant inductance Lrb is given in (25) to achieve ZVS turn-on for S2 and S3 .
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5. Experimental Results
In this section, experiments are presented to verify the effectiveness of the proposed converter. The specifications of the proposed converter are Vin : 750V-800V, Vo =48V, Io =40A, fs =100kHz. The component parameters of the prototype circuit are S1 S4 : IRFP460, turns ratio of T1a , T2a , T3a : 48 turns/4 turns, turns ratio of T1b , T2b , T3b : 24 turns/4 turns, Lma =4.8mH, Lmb =1.2mH, Lra =40μH, Lrb =10μH, Lo =30μH, Ca = Cb =0.4μF, Cin1 = Cin2 = Cf1 = Cf2 = 0.47μF, Da Db : 30ETH06, D1 D6 : KCU30A30 and Co =4000μF. The measured results of the gate waveforms of S1 S4 at 30% and 100% loads under Vin =750V are shown in Fig. 5 . Similarly, the measured gate voltages of S1 S4 at 30% and 100% loads under Vin =800V are illustrated in Fig. 6 . The measured gate voltage, drain voltage and switch current of S1 S4 at 30% and 100% loads under Vin =800V are shown in Fig. 7 . From the measured results shown in Fig. 7 , S1 S4 are all turned on under ZVS from 30% load to full load. The measured waveforms of AC side voltages vac , vce and vcg and inductor currents iLr1a iLr3b at full load are given in Fig. 8 . There are three voltage levels, Vin , Vin /2 and 0, on AC side voltages vac and vce . When vac =0 and vce = Vin , iLr1a and iLr1b decrease and iLr2a iLr3b increase. In the same manner, iLr1a and iLr1b increase and iLr2a iLr3b decrease if vac = Vin and vce =0. The measured waveforms of the capacitor voltages vC1a vC2b and two flying capacitor voltages vCf1 and vCf2 at full load are shown in Fig. 9 . The average capacitor voltages vC1a and vC2a equal Vin /2 and vC1b , vC2b , vCf1 and vCf2 equal Vin /4. The measured results of diode currents and output inductor currents at full load are given in Fig. 10 . The output currents iLo1 iLo3 are balanced. Fig. 11 gives the measured circuit efficiencies of the proposed converter at different load conditions.
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Measured gate voltage waveforms of S1 - S4 at Vin= 750V and (a) 30% load (b) full load.
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Measured gate voltage waveforms of S1 - S4 at Vin= 800V and (a) 30% load (b) full load.
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Measured waveforms of gate voltage, drain voltage and switch current (a) S1 at 30% load (b) S1 at 100% load (c) S2 at 30% load (d) S2 at 100% load (e) S3 at 30% load (f) S3 at 100% load (g) S4 at 30% load (h) S4 at 100% load.
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Measured results of the AC side voltages and primary side inductor currents at full load and (a) Vin=750V (b) Vin=800V.
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Measured capacitor voltages vC1a - vC2b, vCf1 and vCf2 at full load and (a) Vin=750V (b) Vin=800V.
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Measured waveforms of diode currents and output inductor currents at full load and (a) Vin=750V (b) Vin=800V.
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Measured circuit efficiencies at different load conditions.
6. Conclusion
This paper presents a new ZVS DC/DC converter with three sub-circuits for high input voltage and high load current applications. The proposed converter has the features of ZVS turn-on of power switches from 30% load to full load, low current stress of rectifier diodes and magnetic components and low voltage stress of MOSFETs. Three-level diode clamped circuit is adopted to limit the voltage stress of power MOSFETs at one-half of input voltage and two flying capacitors are used to balance input split capacitor voltages. For high load current applications, three circuit cells with the same power switches are used and connected in parallel at low voltage side to reduce current stress of transformer windings, rectifier diodes and output inductors. Each circuit cell has one half-bridge converter and one three-level converter. The transformer secondary windings of two converters are connected in series to reduce output inductor voltage so that output inductor current ripple is reduced compared with that in the conventional three-level PWM converter. Based on the resonant behavior at the transition interval, all MOSFETs can be turned on under ZVS at the designed load ranges. Thus, the conduction losses on MOSFETs can be reduced. Two center-tapped rectifiers are used at the secondary side to have only one diode conduction loss. The main contributions of the proposed converter are low output inductor current ripple, less switch counts and low switching losses compared with the conventional parallel three-level DC/DC converter. Finally, experiments are provided to demonstrate the circuit performance.
Acknowledgements
This research is supported by the National Science Council of Taiwan under Grant NSC102-2221-E-224-022- MY3
BIO
Bor-Ren Lin received the B.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and the M.S. and Ph.D. degrees in electrical engineering from the University of Missouri-Columbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings — Power Electronics and the Journal of Power Electronics. His main research interests include power-factor correction, multilevel converters, active power filters, and softs-witching converters. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of the Research Excellence Awards in 2004, 2005, 2007 and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, the IEEE - Power Electronics and Drive Systems 2009 Conference, and the 2014 IEEE-International Conference Industrial Technology.
Jeng-Yu Chen is currently working toward his M.S. in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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