A Generalized Loss Analysis Algorithm of Power Semiconductor Devices in Multilevel NPC Inverters
A Generalized Loss Analysis Algorithm of Power Semiconductor Devices in Multilevel NPC Inverters
Journal of Electrical Engineering and Technology. 2014. Nov, 9(6): 2168-2180
• Received : April 16, 2014
• Accepted : July 04, 2014
• Published : November 01, 2014 PDF e-PUB PubReader PPT Export by style
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Payam, Alemi
Dept. of Electrical Eng., Yeungnam University, Korea. (payamalemi @ynu.ac.kr)
Dong-Choon, Lee
Corresponding Author: Dept. of Electrical Eng., Yeungnam University, Korea. (dclee@yu.ac.kr)

Abstract
In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.
Keywords
1. Introduction
Multilevel inverters are being used popularly in the area of high power applications since they have the lower voltage stress on switching devices and lower total harmonic distortion (THD) in the output voltage compared with the two-level inverters [1 - 4] . The typical topologies of multilevel inverters are the neutral-point clamped (NPC), the flying capacitor (FC) and the cascaded H-bridge (CHB) types  .
The power losses in a semiconductor device can be classified as conduction loss, switching loss, and leakage loss. The leakage loss of devices can be neglected since they are insignificant compared with the conduction and switching losses. The power loss analysis in two- and three-level converters has been presented in the literatures extensively. The conduction loss of inverters can be found in [5 - 10] and the switching loss has been analyzed using the approximations of IGBT and diode I-V switching characteristics [11 - 14] . However, these methods cannot be applied to the higher level inverters than the three-level, since calculating the conduction loss requires more factors such as the modulation depth, the on-time duration of switches and the PF. The switching loss is also affected by the MI in the M-level inverters.
This paper is an extended version of the work  , where an algorithm for calculating the power losses in the M-level NPC inverter has been proposed. The conduction loss is analyzed by considering the on-time duration of switches at various MIs and the PF. The switching loss is calculated from the turn-on and turn-off times of the devices during which the switching state changes. The results of power loss analysis are provided for the threeand five-level NPC inverters. The conduction loss versus the MI is analyzed and then the total conduction loss is plotted, on which the effect of the MI at the different PF angles is shown.
The total power loss as a function of switching frequency is plotted for three- and five-level NPC inverters, which show the dependency of the inverter loss on the switching frequency. The total switching loss versus the MI and switching frequency are presented, respectively. Finally, the 3-D plot of the switching losses as a function of MI and switching frequency is presented. In the five-level inverter, the switching loss is affected by the MI and the PF. The 3-D plot of total power loss for the three-and five-level NPC inverters versus MI and PF are presented. In order to verify the theoretical derivation of algorithm for three- and five-level NPC inverters, the simulation and experiment have been carried out. The results from the analysis are nearly close to simulation and experimental results.
2. Evaluation Algorithm of Power Losses for M-level NPC Inverters
The power losses of semiconductor devices in the inverters mainly comprise two parts: (i) conduction loss, (ii) switching loss. The device leakage loss is not considered since the leakage current during the off-state of the device is negligible.
- 2.1 Conduction losses
The conduction losses are produced while the power device is conducting the current. Several factors should be considered for the conduction loss evaluation of multilevel inverters, which are the current paths, conducting devices at various time divisions (which are made in relation of the fundamental output phase voltage and load current) and the on-time duration. The procedure calculating the total conduction losses is described as follows:
2.1.1 Finding the current paths and the conducting devices in various time divisions
The circuit of the three-phase M-level NPC voltage-source inverter is shown in Fig. 1 . The conducting devices according to the switching state in the M-level inverter are listed in Table 1 , in which SaK , DaK and Dc represent the IGBT switches, anti-parallel diodes and clamping diodes in M-level NPC inverters, respectively, where the subscript ‘ K ’ means the conducting switch number. In Table 1 , there are the different switching states of ' P ',⋯,' Pj ',⋯,' O ',⋯,' Nj ',⋯,' N ', in which the corresponding conducting devices are listed. PPT Slide
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Three-phase M-level NPC inverter.
Conducting switches in M-level NPC inverters. PPT Slide
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Conducting switches in M-level NPC inverters.
From Fig. 2 , the time duration for power loss analysis is known, which is decided by the voltage and current waveforms. In the case of voltage, the conduction devices are changed depending on what carrier waveform the reference voltage is compared with. Since the level-shifted PWM is used in this analysis, the angles where the carriers are changed should be known. At the angles of ± φMI j and π ± φMI j , the switching states are changed. For the even-level number in the M-level inverters, PPT Slide
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Time duration in relation to Vref and i in a leg-A of M-level NPC inverters. PPT Slide
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and for the odd-level number, PPT Slide
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In addition, the current polarity should be considered which is changed at PPT Slide
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and PPT Slide
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.
2.1.2 Finding the on-time duration
The on-time duration of each device for one PWM period is needed to calculate the average conduction loss. It is assumed that the reference voltage is constant in one PWM period as shown in Fig. 3 . In this analysis, the SPWM method is used. The carrier modulation schemes for multilevel inverters can be generally classified into two categories which are PSPWM (phase shift pulse width modulation) and LSPWM (level shift pulse width modulation) algorithms. Since both of the modulation methods can be applied to the multilevel inverters, in this analysis the LSPWM is used to find the power loss in the inverters. The on-time duration can be found by comparing the reference voltage with the carrier waveform. Since (M-1) carriers are used in the M-level inverters, the (M-1) equations are investigated to find the on-time of switches, which is expressed as PPT Slide
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The on-time duration according to the position of reference voltage in M-level inverters with (a) Even number of levels. (b) Odd number of levels. PPT Slide
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where i=1 corresponds to the P state, 1
where,
• Vref: reference voltage.
2.1.3 Computing total conduction losses
The conduction loss of devices, pon , is computed from the saturation voltage and the conducting current during the on-time duration, which is expressed as PPT Slide
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where,
• von: saturation voltage,
• Vo: threshold voltage,
• Ron: on resistance of device,
• φ: PF angle,
• Ic: peak value of conducting current.
The average conduction loss of each device in the M-level inverter is calculated as PPT Slide
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where ‘ D ’ means the duty ratio of conducting devices, and ‘ a ’ and ‘ b ’ denote the beginning and ending points of each conduction interval, respectively.
- 2.2 Switching losses
In the multilevel inverter, the switching loss varies since the device for switching is changed according to the modulation depth. In addition, it is proportional to the switching frequency. For example, in the case of level-shifted PWM, the switching frequency of the device is not the same as the carrier frequency, which is calculated by PPT Slide
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The switching loss in a leg of the M-level inverter for the positive and negative current directions is calculated as (7) and (8) respectively: PPT Slide
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where, PPT Slide
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• ET: IGBT turn-on and-off energy,
• ED: diode turn-off energy,
• fsw: device switching frequency,
• Psw1: switching loss for the positive current direction,
• Psw2: switching loss for the negative current direction,
• Van(i): reference voltage.
In a leg of the inverter, the switching loss is given by PPT Slide
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and for the three legs of the inverter, PPT Slide
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The IGBTs and diodes which change the operating conditions in the M-level NPC inverters are listed in Table 2 .
Switching state of M-level inverter according to current direction. PPT Slide
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Switching state of M-level inverter according to current direction.
3. Power loss of Three- and Five-level NPC Inverters
- 3.1 Three-level NPC inverters
3.1.1 Conduction losses
Finding the current paths and the conducting devices
Figs. 4(a) and (b) show the current paths in the three-level NPC inverter for positive and negative current directions, respectively. The conducting devices for each switching state are listed in Table 3 . Also, the conducting devices in a leg-A of the three-level NPC inverter depending on the current and voltage polarities is shown in Fig. 5 . PPT Slide
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Current paths of three-level NPC inverters according to switching states: (a) Positive current; (b) Negative current.
Conducting switches in three- and five-level NPC inverters. PPT Slide
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Conducting switches in three- and five-level NPC inverters. PPT Slide
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Conducting devices in a leg-A of three-level NPC inverters.
Finding the on-time duration
The on-time duration can be determined by setting M=3 in (3), in which the reference voltage is compared with two carrier waveforms (shown in Fig. 6 ). The on-state duration of the conducting devices in the three-level inverter is calculated as PPT Slide
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PWM in the three-level inverter.
The on-time duration are calculated, which are listed in Table 4 .
On-time duration of conducting devices in three-level NPC inverters. PPT Slide
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On-time duration of conducting devices in three-level NPC inverters.
Computing the total conduction loss
The average conduction loss is calculated by integrating the power loss of each device in every time duration illustrated in Fig. 5 . It is calculated by (13) to (16) for the three-level inverters: PPT Slide
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3.1.2 Switching losses
The switching loss can be calculated by setting N=3 in (7)-(9) for the positive current direction in the three-level NPC inverter as follows: PPT Slide
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and for negative current direction PPT Slide
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the total power loss in one leg of the three-level NPC inverter is calculated as PPT Slide
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The IGBTs and diodes which change the operating conditions are listed in Table 5 .
Switching states of three-level inverter according to current direction. PPT Slide
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Switching states of three-level inverter according to current direction.
- 3.2 Five-level NPC inverter
3.2.1 Conduction losses
Finding the current paths and the conducting devices
Figs. 7 (a) and (b) show the current paths in the five-level NPC inverters in positive and negative current directions. The conducting devices for each switching state are listed in Table 3 . For 0.5 < MI ≤ 1 , there are two cases in which the change between carrier waveforms occurs for the level-shifted PWM before the change of current polarity as shown in Fig. 8(a) or the current polarity is changed before the change of the carrier waveforms as shown in Fig. 8(b) . For 0 ≤ MI ≤ 0.5, there is no change of the MI as shown in Fig. 8(c) . PPT Slide
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Current paths of five-level NPC inverter according to switching states: (a) Positive current; (b) Negative current. PPT Slide
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Conducting devices in a leg-A of five-level NPC inverters.
Finding the on-time duration
In the case of five-level inverters, the reference voltage is compared with the four carrier waveforms. On-time duration of each switch in the five-level NPC inverters is listed in Table 6 in different regions of operation.
On-time duration of conducting devices in five-level NPC inverters. PPT Slide
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On-time duration of conducting devices in five-level NPC inverters.
Computing the total conduction loss
The average conduction loss of each device in the five-level inverter is calculated in the same way as the three-level one.
3.2.2 Switching Losses
The devices which change the operating condition in the five-level inverter are listed in Table 7 . The total switching l loss can be calculated in the same way for the three-level inverters.
Switching states of five-level inverter according to current direction. PPT Slide
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Switching states of five-level inverter according to current direction.
4. Results of Power Loss Evaluation
For a power loss analysis, a 33-kW system for the three- and five-level NPC inverters is adopted. The DC-link voltage is 600 V. An RL load is connected to the inverter. The semiconductor device used is SKM 75GAL063D (Semikron product), of which rated current is 100 A. Conduction and switching losses are calculated from the parameters in Table 8  . Figs. 9 and 10 show the conduction loss of each device in the three-and five level NPC inverters, respectively. In Fig. 9 , it is obvious that the conduction loss for anti-parallel diode is very low compared with IGBT switches whereas the clamping diodes have slightly higher conduction loss than anti-parallel diodes. The conduction losses of IGBTs and diodes in the five-level NPC inverter are illustrated in Figs. 10(a) and (b) , respectively.
Parameters of SKM 100GB063D module. (VCES= 600[V], T = 25° ) PPT Slide
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Parameters of SKM 100GB063D module . (VCES = 600[V], T = 25° ) PPT Slide
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Conduction loss of each device in three-level NPC inverters versus MI. PPT Slide
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Conduction loss of upper devices in one-leg of five-level NPC inverters versus MI: (a) IGBT switches; (b) Clamping and anti-parallel diodes.
In Fig. 11 the conduction power loss of inverters are investigated as a function of MI and φ respectively. The conduction loss of the three-level inverter at MI=1 and MI=0.5 are 237-W and 85-W, respectively, which are 495-W and 218-W, respectively in the five-level inverter ( Fig. 11(a) ). The conduction loss as a function of angle φ is illustrated in Fig. 11(b) , where the conduction loss of three- and five level inverters in the case of φ = π /2 are 210-W and 450-W, respectively at which condition the MI=1. PPT Slide
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Conduction loss of three-phase NPC inverters versus MI in. (a) φ = 0°. (b) MI=1.
In Fig. 12 the total power loss of inverters are investigated as a function of MI and fsw respectively. In Fig. 12(a) , the power losses of inverters are investigated in different MI in which the switching frequency is fsw = 5[kHz] . The loss of the three-and five-level inverters at MI=1 are 295-W and 619-W, respectively, which are 151-W and 305-W in the case of MI=0.5. The power loss of three-and five-level inverters as a function of switching frequency are illustrated in Fig. 12(b) , where the MI=1 and φ = 0°. PPT Slide
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Total power loss of three-phase NPC inverters versus (a) MI at φ = 0°, fsw = 5[kHz]. (b) Switching frequency at ϕ = 0°, MI = 1 .
The switching loss as a function of the switching frequency is illustrated in Fig. 13(a) . In the three-level inverter, the switching loss is 58-W at 5-kHz switching frequency, which is 87-W in the five-level inverter. The switching loss as a function of switching frequency is shown in Fig. 13(b) . PPT Slide
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Switching loss of three-phase NPC inverters versus (a) MI at φ = 0°, fsw = 5[kHz]. (b) Switching frequency at φ = 0°, MI = 1 .
Fig. 14 illustrates the 3-D plots of power loss in three-phase inverters. The total power loss as a function of MI and PF angle is illustrated in Fig. 14(a) , in which the power loss varies abruptly at MI=0.5 in the five-level NPC inverter. The 3-D plots of switching versus MI and φ are shown in Fig. 14(b) , where the switching frequency is fsw = 5[kHz] . It is shown that, in the case of five-level inverter, the switching loss is affected by MI and power factor angle, however the switching loss of three-level inverter is not changed in different MI and have a slight changes in various power factor angles which is not distinguishable in the figure. The 3-D plot for the conduction losses of inverters are presented in Fig. 14(c) . PPT Slide
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The 3-D plot of the power losses in NPC inverters in 5[kHz] switching frequency: (a) Total power losses; (b) Switching losses; (c) Conduction losses.
5. Verification through Simulation
The power loss analysis is verified by simulation. The inverter operates at the same conditions as analysis aforementioned. The DC-link voltage is 600 V and the load current is 50 A. For simulation, the forward voltage, on-resistance and the turn-on and -off times of IGBT and diodes are required, which are set from the datasheet parameters. The simulation is carried out for the three-and five-level NPC inverters. The total power loss of the inverter is obtained from the difference between the measured input and output powers.
Figs. 15 and Fig. 16 show the total power loss in the three- and five-level NPC inverters, where the operating condition is changed three times during running simulation In the zone (a), the MI=0.55 and PF=1, in the zone (b) the MI=1 and the PF=1, and in the zone (c) the MI=0.4 and PF=0.86. After a transient period due to the changing of simulation conditions, the average power loss of the inverter conditions, the average power loss of the inverter is obtained. For a comparison between the simulation and analysis results, the total power losses are listed in Table 9 . The simulation and analysis results are very close each other, so the loss analysis developed can be validated. PPT Slide
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Measured power loss of three-level NPC inverters. PPT Slide
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Measured power loss of five-level NPC inverters.
Simulation and analysis results of power loss in three-and five-level NPC inverters. PPT Slide
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Simulation and analysis results of power loss in three-and five-level NPC inverters.
6. Verification through Experiment
The power loss analysis of three-level NPC inverter is verified by experiment. The inverter is implemented by using the Semikron IGBT module SKM 75GB128D. The parameters of selected IGBT module are listed in Table. 10 .
Parameters of SKM 75GB128D module. (VCES= 1200[V], T = 25° ) PPT Slide
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Parameters of SKM 75GB128D module . (VCES = 1200[V], T = 25° )
Analysis results:
The power loss is analyzed by using the selected module (SKM 75GB128D). The DC-link voltage is 310 V and the load current is 14 A. The results of analysis are illustrated in Fig. 17 .
In Fig. 17(a) the total power loss, conduction and switching loss of inverter versus MI is shown, where the switching loss is constant in different MI, which is changed as a function of switching frequency in Fig. 17(b) . The conduction power loss and total power loss of inverter are shown in Figs. 17(a) , (b) as a function of MI and switching frequency respectively. PPT Slide
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Power loss analysis results for three-level inverter using SKM 75GB128D module versus: (a) MI; (b). fsw
Experimental results:
The experiment is performed in the same condition as analysis. The total power loss of the inverter is obtained from the difference between the measured input and output powers. The output power is measured by two FLUKE 39 watt meters, which used the line voltage and phase current to measure the power. The three-phase power is calculated as a sum of two watt meters. The inverter input power is obtained by sensing the DC-link capacitor current and voltage. Since the DC-link current is the pulse type, the low pass filter is included to find the capacitor current. The results of loss measurement according to various phase difference, MI and switching frequencies are listed in Tables 11 - 13 . The total power losses of inverter have a slight difference with analysis results in various PF ( Fig. 18 ).
The loss measurement according to different phase difference. PPT Slide
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The loss measurement according to different phase difference.
The loss measurement according to various switching frequency. PPT Slide
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The loss measurement according to various switching frequency.
The loss measurement according to various MI. PPT Slide
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The loss measurement according to various MI. PPT Slide
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Fig. 18. Measured loss of three-level inverter versus PF (MI = 1, fsw = 5[kHz] ).
In Figs. 19 , 20 the measured power loss is compared with analysis results as a function of MI and switching frequency. The differences are very small, which are mainly due to the measurement device accuracy and the performed experiment condition. PPT Slide
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Measured loss of three-level inverter versus MI ( φ = 0° , fsw = 5[kHz] ). PPT Slide
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Measured loss of three-level inverter versus switching frequency (ϕ = 0°, MI = 1).
7. Conclusion
In this paper, a generalized evaluation algorithm for the semiconductor losses in the multilevel NPC inverter has been proposed. From the loss analysis results, several conclusions can be made as follows:
• The conduction and switching losses of the higher-level inverter than the three-level depend on the MI, whereas the switching loss is constant in different MI in the three-level inverter.
• In the five-level inverter, the jumps of the conduction and switching power losses occur at MI=0.5 where the modulation depth changes.
• The proposed algorithm can be applied to the power loss evaluation for any higher level of inverters.
• The validity of the power loss analysis has been verified by simulation results and experimental results.
Acknowledgements
This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2012R1A1A4A01015362).
BIO Payam Alemi was born in Tabriz, Iran in 1982. He received the B.Sc. degree from the University of Tabriz, Tabriz, Iran in 2005 and the M.S. degree from the science and research branch, Tehran Azad University in 2008. He is currently working toward his Ph.D. degree. His research interests include the control of multilevel power converters, power loss analysis for converters, LCL filter and machine drives. Dong-Choon Lee received his B.S., M.S., and Ph.D. in Electrical Engineering from Seoul National University, Seoul, Korea, in 1985, 1987, and 1993, respectively. He was a Research Engineer with Daewoo Heavy Industry, Korea, from 1987 to 1988. Since 1994, he has been a faculty member in the Department of Electrical Engineering, Yeungnam University, Gyeongbuk, Korea. As a Visiting Scholar, he joined the Power Quality Laboratory, Texas A&M University, College Station, TX, USA, in 1998, the Electrical Drive Center, University of Nottingham, Nottingham, U.K., in 2001, the Wisconsin Electric Machines & Power Electronic Consortium, University of Wisconsin, Madison, Wisconsin, USA, in 2004, and the FREEDM Systems Center, North Carolina State University, Raleigh, North Carolina, USA, from September 2011 to August 2012. His current research interests include ac machine drives, control of power converters, wind power generation, and power quality. Prof. Lee is currently a Publication Editor of the Journal of Power Electronics of the Korean Institute of Power Electronics.
References