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Evaluation of Radio-Frequency Performance of Gate-All-Around Ge/GaAs Heterojunction Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric by Mixed-Mode Simulation
Evaluation of Radio-Frequency Performance of Gate-All-Around Ge/GaAs Heterojunction Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric by Mixed-Mode Simulation
Journal of Electrical Engineering and Technology. 2014. Nov, 9(6): 2070-2078
Copyright © 2014, The Korean Institute of Electrical Engineers
  • Received : October 31, 2014
  • Accepted : July 08, 2014
  • Published : November 01, 2014
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About the Authors
Hee Bum Roh
School of Electronics Engineering, Kyungpook National University, Korea. (jhseo@ee.knu.ac.kr)
Jae Hwa Seo
School of Electronics Engineering, Kyungpook National University, Korea. (jhseo@ee.knu.ac.kr)
Young Jun Yoon
School of Electronics Engineering, Kyungpook National University, Korea. (jhseo@ee.knu.ac.kr)
Jin-Hyuk Bae
School of Electronics Engineering, Kyungpook National University, Korea. (jhseo@ee.knu.ac.kr)
Eou-Sik Cho
Department of Electronics Engineering, Gachon University, Korea (felixcho@gachon.ac.kr)
Jung-Hee Lee
Department of Electronics Engineering, Gachon University, Korea (felixcho@gachon.ac.kr)
Seongjae Cho
Department of Electronics Engineering, Gachon University, Korea (felixcho@gachon.ac.kr)
In Man Kang
Corresponding Author: School of Electronics Engineering, Kyungpook National University, Korea. (imkang@ee.knu.ac.kr)

Abstract
In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point ( Q -point) was obtained at V DS = 1 V, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ( A v ), unit-gain frequency ( f unity ), and cut-off frequency ( f T ). The Ge/GaAs HGD pnpn TFET demonstrated A v = 19.4 dB, f unity = 10 THz, f T = 0.487 THz and f max = 18THz.
Keywords
1. Introduction
Conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) driven by drift and diffusion have a lower limit in subthreshold swing ( S ) (~60 mV/dec) at room temperature due to thermionic emission. The irreducible S is a hindrance in enhancing the on-state current ( I on ) while maintaining a sufficiently low off-state current ( I off ), which is also closely related with operation voltage scaling. For this reason, there have been efforts to reduce S below 60 mV/dec for improved switching characteristics [1 - 4] . Tunneling field-effect transistors (TFETs) operated by band-to-band (BTB) tunneling have been widely researched for its plausible feature of small S dropping below the theoretical limit of MOSFETs [5 - 10] . Also, TFETs have stronger immunity against shortchannel effects (SCEs) owing to its tunneling-based operating principle and channel doping profile different from those of conventional MOSFETs [11] . Low on-state current ( I on ) has been pointed out as a drawback of silicon (Si) TFET and efforts have been made to enhance the current drivability of many aspects which include trials of applying particular structures [12 - 14] and low bandgap materials [15] . Besides, it can be achieved by using compound materials to obtain low effective mass and small bandgap [16 , 17] . Several device geometry have been researched in order to diminish ambipolar current and an encumbering effect of gate electric field [18 - 21] . In this work, a TFET device operating by approaches to achieve higher I on of which validation have been confirmed in terms of high-frequency characteristics, especially frequency response. The device is equipped with both hetero-gate-dielectric (HGD) materials and n-type insertion layer boosting the BTB tunneling [12 , 13] . Furthermore, the device channel consists of Ge (source) and III-V compound semiconductor (channel and drain) for enhancing the tunneling efficiency (higher I on ) at the source side and suppressing I off at the drain side. Besides the betterments in current characteristics, Ge/(Al)GaAs heterojunction has a good interface owing to its little lattice mismatch [16 , 17] . Considering approaching more practical and accurate situation, we are focused on tunneling current via nonlocal trap in the relatively wide tunneling width region of the previous researches [22] . In terms of circuit operation, it is expected that the device with HGD and with n-type insertion layer has the immunity to trap-assisted tunneling (TAT) mechanism and decent high-frequency characteristics even if it is set to lower input Q bias. The channel had a gate-all-around (GAA) structure for enhancing the gate controllability in mainly focused and its characteristics are compared with those of devices with ppn and pnpn channels. The frequency responses are investigated from common-source (CS) amplifier embedding the Ge/GaAs HGD pnpn TFET, one of the most fundamental functional block in the analog circuit, by mixed-mode simulation to obtain more accurate solutions through monitoring the real-time interactions between the device and circumference circuit components [23] .
2. Device Schemes and Direct-Current (DC) Performances
Fig. 1 shows the cross-sectional view of nanowire Ge/ GaAs heterojunction TFET with (a) ppn channel, (b) pnpn channel, and (c) hetero-gate-dielectric (HGD) and n-insertion layer (pnpn channel).
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Schematics of simulated devices and circuit. Crosssectional view of (a) ppn, (b) pnpn, and (c) HGD pnpn TFETs. (d) Configuration of CS amplifier with the TFETs.
These devices will be shortly called ppn, pnpn, and HGD pnpn TFETs, respectively. In device simulation, the doping concentrations were p + Ge source of 10 20 cm -3 , p GaAs channel of 10 16 cm -3 , and n + GaAs drain of 10 18 cm -3 , and GaAs n-type insertion layer of 10 18 cm -3 . For comparison with HGD pnpn device regarding circuit level performance, ppn and pnpn device are made like reference device [13 , 22] . Multiple models were employed for higher accuracy in simulation results, including concentration-dependent mobility model, Shockley-Read- Hall recombination model, bandgap narrowing model, and BTB model by Hurkx assisted by non-local BTB tunneling calculation, quantum model, and trap-assisted tunnel (TAT) model. The device is designed to have channel length ( L ch ) of 30 nm, channel radius ( r ch ) of 10 nm, and gate dielectric thickness ( T ox ) of 2 nm. The lengths of n-insertion layer ( L ch-n-GaAs ) and HGD ( L HG ) were adjusted for obtaining fully depleted tunneling junction and both of them were 8 nm. HGD consisted of hafnium oxide (HfO 2 ) (source side) with a relativity permittivity ( εr ) of 25 and aluminum oxide (Al 2 O 3 ) (drain side) with εr =9.3. Copper (workfunction ( φ m ) = 4.4 eV) was used for the gate metal. From a fabrication point of view, Ge and GaAs can be epitaxially grown by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) forming good interfacial status owing to genuinely little lattice mismatch [24] . Combinational uses of plasma laser annealing doping (PLAD), excimer laser annealing (ELA), and dopant profile-steepening implantation (DPSI) can be considered as the most recent possible techniques to obtain high doping concentration with nearly abrupt junctions [25 - 27] . Fig. 1(d) shows schematic of CS amplifier embedding a TFET. Signal resistance ( R sig ) and drain resistance ( R D ) were selected to be 50 Ω and 4 kΩ, respectively, by recursive simulations to obtain symmetric output swing [22] .
Fig. 2(a) shows the transfer characteristics ( I D - V GS ) of the simulated devices with and without TAT model for ppn, pnpn, and HGD pnpn TFETs. When gate voltage ( V GS ) is low, TAT is dominant over BTB tunneling due to thick tunneling barrier between source and channel, which is proven by the fact that the I off makes a difference near V GS = 0 V depending on whether TAT model is turned on or not. As VGS increases, the effect of TAT is weakened and BTB tunneling begins to dominate. Tunneling probability, T ( E ), induced by Wentzel-Kramers-Brillouin (WKB) approximation is expressed as
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where m * is the reduced effective mass in the average sense of electron ( me * ) and hole ( mh * ) effective masses, Eg is bandgap energy, e is electron charge, ξ is the electric field, and ħ is the reduced Planck’s constant [28 , 29] . Aided by the equation for Hurkx’s BTB tunneling model, S for TFET can be formulated in a closed form as below.
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where constant in the denominator is determined by device dimensions and material properties [30] . Higher V GS increases S from Eq. (2), by which it is expected that TFET is suitable to low-power operation for steeper switching slope. S of the devices in Figs. 1(a) - (c) are extracted to be 31.5 mV/dec, 22.4 mV/dec, and 22.3 mV/dec, respectively, as shown in Fig. 2(a) . Slopes much steeper than 60 mV/dec are obtained and further improvements are made in the devices with pnpn and HGD pnpn structures. Transconductances ( g m ’s) of the devices are depicted in Fig. 2(b) , which shows prominent enhancement as the device is evolved to have from ppn to pnpn and HGD pnpn structures.
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(a) Transfer characteristics (ID-VGS) of PPN structure, PNPN structure, and HGD PNPN structure with and without TAT. (b) Transconductance of PPN structure, PNPN structure, and HGD PNPN structure with TAT.
Figs. 3(a) and (b) show the output characteristics ( I D - V DS ) of the designed devices with and without TAT models at different gate voltages, V GS =0.6 V and 1.0 V, respectively. Superlinear behaviors of I D in the low V DS region are observed as reported in a previous literature [31] . In both cases, I D of ppn TFET is increased by an amount of 15% of its initial value by activating the TAT model in the simulation compared with the current obtained without the model, while pnpn and HGD pnpn devices demonstrate negligibly small change. Increment in I D of ppn TFET is originating from a fact that its tunneling barrier is not thin enough to suppress the TAT current and substantially retards the BTB tunneling as described in Figs. 4(a) and (b) . On the other hand, pnpn and HGD pnpn TFETs are immune to TAT so that BTB tunneling is more readily dominant in the operations [32] , of which merit comes with circuit performances clearly as will be shown in a later section.
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(a) ID-VDS of TFETs with and without TAT at VGS = 0.6 V, (b) at VGS = 1.0 V.
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Energy band diagrams of depletion layer of each device at (a) VGS = 0.6 V, (b) VGS = 1.0 V.
Specific device performances such as on-state current, off-state current, on / off ratio, threshold voltage and subthreshold swing are summarized in Table 1 .
Summary of specific device performances.
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Summary of specific device performances.
3. Circuit Performances
Fig. 5(a) depicts voltage transfer characteristics (VTCs) of a CS amplifier using Ge/GaAs heterojunction TFET. The circuit simulations have been also carried out with and without TAT model to study in comparison its effect on circuit performances. First of all, the operating point ( Q -point) needs to be positioned in order to have maximum slope on the VTC curve at Q -point, which leads to the maximum amplification. Input bias was varied with device types for obtaining the optimum condition, which were V IN = 1.16 V for ppn TFET, V IN = 0.78 V for pnpn TFET, and V IN = 0.62 for HGD pnpn TFET. Along with output voltage ( V OUT ) of the Ge/GaAs TFET-embedded CS amplifier, the slope of VTC curve (d V OUT /d V IN ) is plotted as a function of V IN as shown in Figs. 5(b) - (d) . The maximum d V OUT / d V IN values were -6.66 V/V for ppn TFET, -7.82 V/V for pnpn TFET, and -11.28 V/V for HGD pnpn TFET. The DC performance of CS amplifier as an inverter is also improved as the main transistor is evolved from ppn TFET to pnpn and HGD pnpn TFETs. The next important step in biasing an amplifier should be to check if there is no distortion in output swing. Although it was verified that the amplitude of small-signal voltage (| v in | = 10 mV) was not large enough to make any distortion in output swing at the selected Q -point above, the output bias for Q -point was further adjusted to V DS = 1 V so that wide enough output window as well as symmetry in maximum swing could be more stably secured [22] . For this goal, drain resistance can be precisely controlled in through recursive analyses of load-line at the Q -point. Considering the conditions for BTB tunneling, input voltages of the CS amplifiers with ppn, pnpn, and HGD pnpn TFETs were set to 0.59 V, 0.74 V, and 1.15 V, respectively. The CS amplifier with ppn TFET shows V IN shift as depicted in Fig. 5(b) , which is mainly due to the increase of I D caused by TAT as previously mentioned in Fig. 3(a) . Considering the effect of TAT, the input bias was set to V IN = 1.11 V for the CS amplifier with ppn TFET. After further adjusting of the bias conditions, the derivatives of >VTC at the Q-points ( dV OUT / dV IN ) as the most crucial factor in small-signal amplification, have been slightly changed to -5.3 V/V (14.5 dB), -6.6 V/V (16.4 dB), and -9.21 V/V (19.4 dB) for the CS amplifiers with ppn, pnpn, and HGD pnpn TFETs, respectively. The prominently high g m (as was confirmed by Fig. 2(b) ) of HGD pnpn TFET plays a major role in enhancing the amplification ratio.
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Voltage transfer characteristics (VTCs) of (a) TFETs; (b) PPN TFET with and without TAT; (c) PNPN TFET with and without TAT, and (d) HGD PNPN TFET with and without TAT.
Figs. 6(a) and (b) demonstrate the frequency responses of the CS amplifiers with ppn, pnpn, and HGD pnpn TFETs regarding voltage gain ( A v ) and phase change, respectively. The results were obtained by device-circuit mixed-mode simulations at the final Q -points. The A v values in decibel (dB) correspond to the maximum slopes on the VTC curves (amplification ratios) obtained in the optimization processes travelled above. In Fig. 6(a) , the unity gain frequencies ( f unity ) (intercept crossing 0 dB) of the CS amplifiers with ppn, pnpn, and HGD pnpn TFETs, are 8 THz, 9.5 THz, and 10 THz, respectively. This figure of merit (FoM) is one of the crucial in factors in the analog circuits, which implies that circuits embedding the TFETs in this work would have a wide range of operating frequency and its importance is more revealed as the system employs a negative feedback [33] . Fig. 6(b) shows phase shifts of -270°, of which system can be mathematically described by a transfer function with two right-half-plane (RHP) poles and one left-half-plane (LHP) zero [22] . The little curvatures infer that the poles and zero are closely located in the s -plane.
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(a) Magnitude response of TFETs; (b) Phase shift response of TFETs.
In Fig. 7 , current gain and unilateral power gain of the circuits have been extracted. The cut-off frequency ( f T ), which is defined as the frequency interception with the unity current gain (0dB), is generally specified as
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where C gg is sum of gate-source capacitance and gatedrain capacitance [34] . Table 2 shows capacitances and transconductances extracted by radio-frequency gate-allaround TFETs modeling in the different Q -points [35] . These capacitances of each device are extracted for further analyzing into high frequency response. The extracted f T of PPN, PNPN, and HGD PNPN TFET are revealed as 1.68THz, 0.76THz, and 0.487THz, respectively. The PPN and PNPN device, which have relatively high input biases, can have high gate-source capacitances and high transconductances. While HGD PNPN device has low input bias, HGD device has high gate-source capacitance due to high-k hetero-gate-dielectric near the source. For this reason, f T of HGD pnpn device is lower than ppn device.
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Current gains and unilateral power gains of each PPN, PNPN, and HGD PNPN TFET.
Capacitances and transconductances of each PPN, PNPN and HGD PNPN TFET at each input bias.
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Capacitances and transconductances of each PPN, PNPN and HGD PNPN TFET at each input bias.
On the other hand, Unilateral power gain ( U max ), which is the measurement of the quality of active devices over the entire frequency range of interest, can be extracted as
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where Ys are linear two port network parameter [36] . The maximum oscillation frequency ( f max ), which are crossing 0dB of U max in Fig. 7 , are 9THz, 16THz, and 18THz, respectively.
This result reveals that low-power operation is made possible by adopting the HGD pnpn TFETs in highfrequency circuit applications.
4. Conclusion
In this work, high-frequency characteristics of GAA Ge/GaAs heterojunction HGD pnpn TFET have been analyzed with a particular interest in frequency responses, by device-circuit mixed-mode simulations. The study has been carried out in comparison with devices with ppn and pnpn (but without HGD) channel doping profiles for more stringently verifying the superiority of the pnpn HGD device. Higher current drivability and transconductance and immunity to TAT mechanism were obtained from the pnpn HGD TFET and a common-source amplifier with the device was schemed for having a closer look into the contributions of the device in circuit applications. Voltage characteristics of devices are discussed with details in steps determining the circuit Q -points. At the optimum operating condition, the amplifier demonstrated A v =19.4 dB, f unity (frequency at unity A v ) =10THz, and f T =0.487 THz, and f max =18THz GAA Ge/GaAs heterojunction HGD pnpn TFET has a number of advantageous features for driving transistor in advanced integrated circuits for low-power high-frequency applications.
Acknowledgements
This work was supported in part by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (MEST) (No.2013-011522, 2012-0005671), and in part by Samsung Electronics Co. This work was also supported by Global Ph.D. Fellowship Program through the NRF funded by the MEST (2013H1A2A1034363).
BIO
Hee Bum Roh He received the B.S. degree in electrical engineering from the School of Electronics Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2014. He is currently working toward the M.S. degree in electrical engineering with School of Electrical Engineering and Computer Science, Seoul National University (SNU). His research interests include design, fabrication, and characterization of Organic FET, OLED, and Thin film transistors.
Jae Hwa Seo He received the B.S. degree in electrical engineering from the School of Electronics Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2012. He is currently working toward the M.S. degree in electrical engineering with the School of Electronics Engineering (SEE), Kyungpook National University (KNU). His research interests include design, fabrication, and characterization of nanoscale CMOS, tunneling FET, III-V compound transistors, and junctionless silicon devices.
Young Jun Yoon He received the B.S. degree in electrical engineering from the School of Electronics Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2013. He is currently working toward the M.S. degree in electrical engineering with the School of Electronics Engineering (SEE), Kyungpook National University (KNU). His research interests include design, fabrication, and characterization of nanoscale tunneling FET, GaN-based transistors, and GaNbased circuit.
Jin-Hyuk Bae He received the B.S. degree in electronics and electrical engineering from Kyungpook National University, Daegu, Korea in 2004, and the M.S. and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea in 2006 and 2010, respectively. For the period from 2010 to 2012, he worked as a post-doctoral research fellow with Ecole Nationale Superiere des Mines de Saint-Etienne, Gardanne, France. In 2012, he joined the faculty in the School of electronics engineering, Kyungpook National University, Korea, where he is currently an Assistant Professor. His research interests include interfacial engineering and physics of organic based and metal-oxide based electronic devices, and their applications.
Eou-Sik Cho He was born in Seoul, Korea, in 1972. He received the B.S., M.S. and Ph. D degrees in the School of Electrical Engineering from Seoul National University, Seoul, Korea in 1996, 1998, and 2004, respectively. From 2004 to 2006, he was a senior engineer with the Samsung Electronics, where he worked on the process development of large size TFT-LCD. Since 2006, he has been a member of the faculty of Gachon University(Seongnam, Korea), where he is currently an Associate Professor with the Department of Electronic Engineering. His current research interests include fabrication of TFT devices, laser etching of thin films, and touch panel.
Jung-Hee Lee He received the B.S. and M.S. degrees in electronic engineeering from Kyungpook National University, Daegu, in 1979 and 1983, respectively, the M.S. degree in electrical and computer engineering from Florida Institute of Technology, Melbourne, in 1986, and the Ph.D. degree in electrical and computer engineering from North Carolina State University, Raleigh, in 1990. His doctoral research concerned carrier collection and laser properties in monolayer-thick quantum-well heterostructures. From 1990 to 1993, he was with the Compound Semiconductor Research Group, Electronics and Telecommunication Research Institute, Daejeon, Korea. Since 1993, he has been a Professor with the School of Electronics Engineering (SEE), Kyungpook National University, Daegu. He is the author or coauthor of more than 200 publications on semiconductor materials and devices. His current research is focused on the growth of nitride-based epitaxy, the fabrication and characterization of gallium-nitride-based electronic and optoelectronic devices, atomic layer epitaxy for metal-oxide-semiconductor application, and characterizations and analyses for the 3-D devices such as fin-shaped FETs.
Seongjae Cho He received the B.S. and Ph.D. degrees in electronic engineeering from Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea, in 2004 and 2010, respectively. He worked as an Exchange Researcher at the National Advanced Industrial Science and Technology (AIST), Tsukuba, Japan, in 2009. He worked as a Postdoctoral Researcher at Seoul National University in 2010, and at the Department of Electrical Engineering, Stanford University, from 2010 to 2013. He has been working as an Assistant Professor at the Department of Electronic Engineering and the Department of IT Convergence Engineering, Gachon University, Seongnam-si, Korea, since 2013. His main research interests include nanoscale CMOS devices, emerging memory technologies, photonic devices, and integrated systems.
In Man Kang He received the B.S. degree in electronic and electrical engineering from School of Electronics and Electrical Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2001, and the Ph.D. degree in electrical engineering from School of Electrical Engineering and Computer Science (EECS), Seoul National University (SNU), Seoul, Korea, in 2007. He worked as a teaching assistant for semiconductor process education from 2001 to 2006 at Inter-university Semiconductor Research Center (ISRC) in SNU. From 2007 to 2010, he worked as a senior engineer at Design Technology Team of Samsung Electronics Company. In 2010, he joined KNU as a full-time lecturer of the School of Electronics Engineering (SEE). Now, he has worked as an assistant professor. His current research interests include CMOS RF modeling, silicon nanowire devices, tunneling transistor, low-power nano CMOS, and III-V compound semiconductors. He is a member of IEEE EDS.
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