In a singlephase gridconnected power system consisting of a DC/DC converter and a DC/AC converter, the current drawn from renewable energy sources has a tendency to be pulsated and contains secondorder frequency ripple components, which results in several drawback such as a power harvesting loss and a shortening of the energy source’s life. This paper presents a new secondorder harmonic current reduction scheme with a fast dclink voltage loop for twostage dcdcac grid connected systems. In the frequency domain, an adequate control design is performed based on the small signal transfer function of a twostage dcdcac converter. To verify the effectiveness of proposed control algorithm, a 1 kW hardware prototype has been built and experimental results are presented.
1. Introduction
With increasing demand for clean and infinite energy resources, renewable energy sources, like photovoltaic, fuel cell and wind power, have experienced rapid growth over the past few years
[1
,
2]
. One of the prospective uses for renewable energy sources is the installation of distributed power systems to the existing power grid for supplying adequate energy. The distributed power systems include a power electronics converter to improve a system’s performance and reliability.
In a singlephase gridconnected power system, consisting of a DC/DC converter and a DC/AC converter, the converter has a pulsated instantaneous output power as shown in
Fig. 1
. If the DC/AC converter has a large enough dclink capacitance, the capacitor can smoothen the dclink voltage, but the input current will have low frequency ripple components, where the frequency corresponds to the secondorder frequency. This low frequency current ripple flows into a renewable energy source, and finally gives large negative effects on the energy harvesting and energy source’s expectancy.
Twostage gridconnected inverter under singlephase electrical utility
In order to reduce the low frequency current ripple at renewable energy sources, severalschemes such large electrolytic capacitors, usually in the range of mF
[3]
, extra power decoupling circuits
[4

7]
and active power filters
[8]
have been proposed in prior studies, and some of them are popularly used because of their simplicity and effectiveness. However, the schemes that use extra circuits grapple with the problems of a short system lifespan, large volume or high cost. Active control schemes using existing dclink capacitors in a twostage dcdcac converter, can suppress these difficulties. Some authors proposed a feed forward compensator
[9]
, and the compensator produced a ripple cancellation duty ratio based on the correlation between the instantaneous output power and the dclink voltage. However, this has the drawbacks of poor disturbance rejection and robustness in terms of parameter variations. These are inherent problems commonly found in most feed forward compensators. These demerits were solved by the proper design of a twoloop feedback compensator
[10]
. However, this scheme leads to the problem of slow dynamics in the outer voltage loop. This slow dynamics causes a slow transient response of the dclink voltage. Moreover, the dclink capacitor may experiences large overshoot or undershoot voltages unless the dclink capacitor is sufficiently large.
In this paper, a novel low frequency current reduction scheme is presented. The proposed scheme is based on the common twoloop feedback scheme, but reconstructs the control structure by changing the feedback control configuration. The superiority of proposed control mechanism especially in terms of the faster dynamics of the outer voltage loop is verified by investigating the fundamental mechanism. A quasinotch filter is adapted to improve the control structure and to alleviate hardware implementation concerns. A proper control design of the twostage DC/DC/AC converter is presented based on smallsignal modelling, and several experiments are performed to verify that the proposed scheme achieves a ripplefree dc current from renewable energy sources. The experiments also verify that it has much faster dynamics in terms of the dclink voltage loop with a fast settling time. In addition, maximum power point tracking (MPPT) experiments are performed to demonstrate the superiority of the propose scheme.
2. Principle of Proposed and Conventional Scheme
 2.1 Principle of proposed scheme
Fig. 2
represents a twostage DC/DC/AC gridconnected power system with the proposed low frequency current reduction scheme for a singlephase electrical utility. A nonisolated type DC/DC boost converter is used to maintain a sufficiently high dc bus voltage,
v_{d}
, even when renewable energy sources drop to low voltage levels. For the secondstage converter, a singlephase DC/AC fullbridge inverter topology is used and the output current,
i_{s}
, is regulated with the output inductor,
L_{s}
. The input current of the DC/DC boost converter,
i_{g}
, is controlled by the dcdc converter’s control loop. In the DC/AC inverter control loop, the current compensator,
C_{is}
, regulates
i_{s}
in accordance with its reference,
i_{s}
^{*}
. The dclink voltage,
v_{d}
, is regulated by the outer voltage loop, denoted by a dotted line.
Proposed secondorder harmonic current reduction scheme
As seen from
Fig. 2
, the current reference,
i_{g}
^{*}
, of the DC/DC converter is given externally in the proposed scheme. Thus the current control loop achieves total isolated from the dclink voltage. With the isolated control structure, the interference, caused by the dclink voltage, can be eliminated against a rippleless dc current regulation. Thus the control structure provides more a favorable control platform for achieving fast dynamics in the voltage loops, while providing low frequency ripple current reduction.
 2.2 Comparison of conventional and proposed scheme
Fig. 3
shows the control structure for the conventional scheme introduced in
[10]
. In this scheme, the current loop is coupled with the voltage output loop. Even with a large capacitor, the dclink voltage,
v_{d}
, contains some low frequency ripple components. As a result, the outer voltage loop is easily disturbed by these low frequency components, unless the voltage loop is designed with a strong attenuation in the low frequency region. In a previous study of
[10]
, in order to achieve a strong attenuation, the voltage compensator was designed with a low crossover frequency at the expense of the dynamic response.
Block diagram of conventional current ripple reduction scheme
Fig. 4
shows a simulation comparison between the conventional and proposed schemes under the same crossover frequency of 16 Hz in the voltage control loop. It is clearly seen that the input current of the proposed scheme shows a smaller ac ripple due to the isolated control structure even under the same crossover frequency.
Performance comparison of current reduction scheme
Following sections describe the detailed controller structure and compensator design for performance verification.
3. Compensator Design of Proposed Scheme
 3.1 Properties of the quasinotch filter
The current loop of the dcdc converter requires a proper design with an extremely high loop gain at the secondorder frequency to achieve an effective low frequency current ripple reduction. With a sufficiently high control loop gain, the current,
i_{g}
, becomes a rippleless dc current by suppressing the impact of the low frequency ripple current.
However, designing with a high gain is impractical due to several difficulties such as component tolerances, temperature variations, and parasitic effects. An alternative way to achieve a current ripple reduction is to design the voltage loop gain of the DC/AC inverter so that it is much smaller than the current loop gain of the DC/DC converter. As a promising solution, this paper adapts a quasinotch filter, which provides strong attenuation in a specific frequency range, to the outer voltage loop of the DC/AC inverter, and consequently, it provides a sufficiently small loop gain of the voltage loop, while permitting a high crossover frequency with fast dynamics.
CQRF(s)
, shows the transfer function of the quasinotch filter, and its attenuation level at
ω_{o}
,
Q
. They are given as (1) and (2), where
Q_{z}
is the quality factor of the resonant zero,
Q_{p}
is the quality factor of the resonant pole, and
ω_{o}
is the resonant frequency. Eq. (2) can be derived from (1) by letting
s=jω_{o}
, and expressing in decibels
[11]
, where
j
is the square root of −1.
The quasinotch filter attenuates the gain in a specific frequency range, like the standard notch filter. However, its phase drop is adjusted by the strength of the attenuation. With this adjustable phase drop providing a flexible compensator design, it is possible to increase the crossover frequency even beyond the secondorder frequency.
Fig. 5
presents the frequency response of the quasinotch filter under
Q_{p}
=10 with several
Q_{z}
s.
Quasinotch filter with varying resonant zero under fixed resonant pole
 3.2 Control loop and compensator design
Closedloop block diagrams of the DC/DC converter and the DC/AC inverter are illustrated in
Fig. 6
, where the smallsignal transfer function blocks:
G_{ig}
— dutytoinput current,
G_{is}
— dutytooutput current,
G_{vdis}
— output currenttodc link voltage transfer function,
C_{ig}
— input current compensator,
C_{is}
— output current compensator,
C_{vs}
— dc link voltage compensator,
H_{ig}
— input current sensor gain,
H_{is}
— output current sensor gain,
H_{vs}
— dclink voltage sensor gain, and
F_{m}
— PWM gain. The smallsignal transfer functions of
G_{ig}
,
G_{is}
, and
G_{vdis}
, can be easily derived by using the averaged PWM switch model in
[12]
.
Closedloop control block diagram of the proposed scheme
After deriving the smallsignal transfer functions, proper compensators are designed in the frequency domain.
Fig. 7
and
Fig. 8
show the compensator design results of the dcdc converter and the dcac inverter in gain/phase plots. The compensators are designed with the following circuit parameters:
v_{g}
= 50~70V,
v_{d}
= 250V,
v_{s}
= 110V,
L_{g}
=3.3mH,
C_{d}
= 1880μF, and
L_{s}
= 3mH, which correspond to the 1kW hardware prototype specifications used in the experiments.
Loop gain and closedloop response of the current loop
Gain / phase plots of the voltage loop including current loop of dcac converter
For the DC/DC converter, the current loop is designed with the onezero twopole PID compensator shown in (3) with
C_{ig}
(0) = 27000,
ω_{pg}
= 3000 rad/sec, and
ω_{zg}
= 270 rad/sec. The resultant loop gain, shown in
Fig. 7 (a)
, shows that the phase margin is higher than 160 degrees and the crossover frequency is about 100 Hz. For the current loop of the DC/AC inverter, the proportionalresonant type (PR) compensator shown in (4) is used to achieve a desirable high gain at a line frequency of 60 Hz, where
C_{is}
(0) = 970,
k_{ps}
= 0.2, and
ω_{ps}
= 380 rad/sec. As seen in
Fig. 7(b)
, the phase margin of the current loop is higher than 170 degrees and the crossover frequency is about 4 kHz. The voltage loop of the dcac inverter is composed of the twopole one zero PID compensator in (5) with
C_{vs}
(0) = 1.5,
ω_{pv}
= 27000 rad/sec, and
ω_{zv}
= 76 rad/sec and the quasinotch filter in (1) designed with
Q_{z}
= 500,
Q_{p}
= 10, and
ω_{o}
= 753.98 rad/sec.
Fig. 8
shows the results of the gain/phase plots of the loop gain. As in the figure, it is clear that the attenuation is more than −20dB with a double fundamental frequency of 120Hz.
4. Experimental Result
A 1 kW hardware prototype has been built to verify the proposed control scheme, as shown in
Fig. 9
, and a digital signal processor is used to implement the proposed compensators. A programmable dc power supply equipped with solar array simulation (SAS) control software from Regatron is used to emulate the renewable energy output of a PV array. The dclink command is set to 250V.
Experimental setup of twostage singlephase gridconnected inverter
Figs. 10
and
Fig. 11
show the steadystate operation waveforms under a 7A input current command. Without the low frequency current reduction scheme, the low frequency ripple current is exhibited in the input current as shown in
Fig. 10
. The Total Harmonic Distortion (THD) is measured at 2.9 %.
Steadystate waveforms without the proposed scheme
Steadystate waveforms with the proposed scheme
On the other hand, with the proposed low frequency current reduction scheme, shown in
Fig. 11
, the input current achieves a ripplefree dc current since the dclink capacitor takes over most parts of the ripple components. This is due to sufficient attenuation of voltage loop gain by the quasinotch filter. In the proposed scheme, the THD of the output current is slightly higher at 4.8%. However, this still satisfies international standards and regulations.
Fig. 12
shows the transient responses of the proposed and conventional schemes.
Fig. 12(a)
is the experimental result under the conventional scheme with a 2 Hz crossover frequency, and
Fig. 12(b)
is the test result under the proposed scheme. It is clearly seen that the proposed scheme of
Fig. 12(b)
exhibits improvements in terms of a fast transient response, due to the high crossover frequency of the voltage control loop.
Dynamic transient waveforms under increasing input current.
Fig. 13
shows the maximum power point tracking(MPPT) experimental results using SAS control software from Regatron, where x denotes the maximum and minimum operating points during 2 seconds and o denotes the averaged operating point.
Figure 13(a)
shows the case without the low frequency current reduction scheme and
Figure 13(b)
illustrates the experimental result with the proposed low frequency current reduction scheme. It can be seen that the range of the operating point with the proposed scheme is closer to the averaged operating point, due to the reduction of the low frequency current ripple. As a result, the MPPT efficiency with the proposed scheme is 96.43%, which is about 3% higher than the efficiency without the scheme at 93.57%. The performance results of the conventional and the proposed schemes are summarized in
Table 1
.
Experimental waveform of the maximum power point tracking
Performance Summary of conventional scheme and proposed scheme
Performance Summary of conventional scheme and proposed scheme
5. Conclusion
In this paper, a novel low frequency current reduction scheme is proposed for a two stage DC/DC/AC gridinterconnected power system. By isolating the current closed loop of the DC/DC converter from the dclink capacitor and incorporating a quasinotch filter into the voltage loop of the DC/AC inverter, a fast dclink voltage control can be achieved. The fundamental theory of the proposed control scheme was introduced, and its superiority in terms of achieving fast dynamics was clearly explained. The experimental results show that the novel current reduction scheme achieves a ripple free dc input current with a fast dclink voltage regulation, and thus reduces the settling time of the dclink voltage control.
BIO
Hongju Jung He received the B.S. and M.S. degrees in electrical engineering from Kwangwoon University, Seoul, Korea, in 1998 and 2000, respectively. He is currently pursuing a Ph.D. degree in the Energy Electronics Control System Lab, Hanyang University, Seoul, Korea. Since 2000, he was a Senior Researcher at the Hyosung Power & Industrial Systems R&D Center, Gyeonggido, Korea. His main research interests include power converter system for renewable energies and VSC HVDC converter System.
RaeYoung Kim He received the B.S. and M.S. degrees from Hanyang University, Seoul, Korea, in 1997 and 1999, respectively, and the Ph.D. degree from Virginia Polytechnic Institute and State University, Blacksburg, in 2009, all in electrical engineering. From 1999 to 2004, he was a Senior Researcher at the Hyosung Heavy Industry R&D Center, Seoul, Korea. In 2009, he was a Postdoctoral Researcher at National Semiconductor Corporation, working on smart home energy management system. Since 2010, he has been with Hanyang University, where he is currently a Professor in the Department of Electrical and Biomedical Engineering. His research interests include modeling and control of power converter systems, softswitching techniques, energy management systems in smart grid applications, power converter systems for renewable energies, and motor drive systems. Dr. Kim received the First Prize Paper Award at the IEEE Industry Applications Society (IAS) Annual Meeting in 2007. Since 2009, he has been a member of the IAS Industry Power Converters Committee, and also served as a Reviewer for the IEEE Transaction On Industrial Electronics and the IEEE Transaction On Industry Applications.
2009
Renewable Energy Policy Network for the 21st Century. Renewables global status report
2009
International Energy Outlook 2009, Energy Information Administration, Official Energy statistics from the U.S. Government 2009
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