This paper shows the design and control methods of the bidirectional DCDC converter to generate the proper DClink voltage of a PMSM drive. Conventionally, because the controllable power of the PWM based voltage source inverter is limited by its DClink voltage, the DCDC converter is used for boosted DClink voltage if the inverter source cannot generate enough operating voltage for the PMSM drive. In this paper, to obtain more utilization of this DCDC converter, optimal DClink voltage control for PMSM drive will be explained. First, the process and current path of the DCDC converter will be illustrated, and a control method of this converter for variable DClink voltage will then be explained. Finally, an improvement analysis of the optimal DClink voltage control method, especially on the deadtime effect, will be explained. The DCDC converter of the proposed control method is verified by the experiments by comparing with the conventional constant voltage control method.
1. Introduction
Research on vehicles that use electrical energy has been carried out to address the depletion of fossil fuel and volatile energy prices. Carrying the battery of low output voltage for light weight and small size, a DCDC converter is used to obtain enough DClink voltage to operate the PMSM drives. As shown in Fig.1, this DCDC converter is located between the battery and the inverter to boost the voltage for sufficient DClink to operate the PMSM.
[1

6]
In the conventional research, the control methods of this DCDC converter application are generally used for a constant DClink voltage and the management of regenerative energy
[1

2]
. Combining a supercapacitor and renewable source increases the efficiency of the motor drive due to the regenerative energy control
[3]
. Recently, to increase the utilization of this DCDC converter, the research of an optimal DClink voltage control method has been carried out. This variable DClink voltage control reduces the current ripple of the inverter and improves the operation efficiency of the PMSM drive
[4

5]
. For the conventional DCDC converter topologies for the optimal DClink voltage control, fullbridge converter
[4]
and halfbridge converter
[5]
topologies are generally used. Halfbridge type DCDC converters have the advantage of reducing the switching device; however, the output voltage should be more than the input voltage. Therefore, the controllable optimal DClink voltage is limited.
On the other hand, fullbridge DCDC converters have the advantage of having a controllable output voltage less than the input voltage; however, the fullbridge DCDC converter needs more switching device than the half– bridge type DCDC converter. Moreover, each switch is discontinuously controlled according to the buckboost operation modes
[4]
. The problem of this discontinuous control method illustrated in
[4]
is that, only one switch controls the regenerating and motoring mode in the fullbridge converter topology. To adapt this control method, detecting the operation mode is essential, and the transition is unavoidable for boost and buck operation. Therefore, the DClink voltage control performance is deteriorated and complex by the control method of
[4]
.
In this paper, the topology of attaching an additional switch to a general halfbridge type DCDC converter to extend the controllable output DClink voltage is first illustrated. Second, the designated DCDC converter is controlled by only one controller for motoring and regenerating operation modes. Therefore, the proposed control method does not need a detecting operation mode and specific transition method for the controlled switch. Third, the analysis of the inverter efficiency improvement with the proposed controlled converter especially on the deadtime effect is explained. Comparison experiments are then performed for the verification of the analyzed improvement.
Bidirectional DCDC converter using electrical vehicle system.
2. Design and operation modes of the bidirectional DCDC Converter
 2.1 Design of bidirectional DCDC converter
Fig. 2
shows the conventional and the semifull bridge type DCDC converters used for optimal DClink voltage control. As aforementioned, in the semifull bridge converter, a switch is added to the conventional halfbridge converter.
Comparison of bidirectional DCDC converters for optimal DClink voltage control: (a) halfbridge type; (b) fullbridge type; (c) semifull bridge type
The advantage of this proposed converter is that its controllable range of output voltage is the same as that of the fullbridge converter in motoring operation. However, regenerative operation for the buck mode output voltage is impossible with the proposed converter. In this case, the DClink voltage is increased because of the regenerative operation of the inverter. However, when the DClink voltage is more than the input voltage, the regenerative operation is started by the halfbridge arm, and it keeps the DClink voltage as the input voltage.
In this case, a problem arises in that the semifull bridge converter cannot control the output voltage to the voltage reference. However, when the DClink voltage is controlled to be optimal, a low DClink voltage means that the regenerative output power is also small. In this case, it is better to accumulate regenerative energy on the DClink capacitor because of the power loss from the current passing through the DCDC converter. Moreover, in the case of low voltage and high current regenerative power, the conducted and switched power loss is increased by the resistance of the DCDC converter switches. In this case, accumulating the regenerative energy to DClink capacitor is more efficient than accumulating the regenerative energy to the battery.
 2.2 Operation modes of bidirectional DCDC converter
The Semifull bridge type DCDC converter has three operation modes: buckmode operation, boostmode operation and regenerative buckmode operation.
2.1.1 Buckmode operation
Fig. 3
shows the buckmode operation of the bidirectional DCDC converter. Switch
S_{1}
is turned on and off for the general operation of the buck converter topology. In this mode,
S_{3}
is always turned on and
S_{2}
is always turned off. The voltage gain of buckmode is described as follows according to the duty of
S_{1}
.
Buckmode operation according to whether the switch is on or off.
The current and voltage ripples of this mode are illustrated in
[1]
. As illustrated on
[1]
, these ripples are greater than buckmode operation. Note that the inductor and capacitor of this converter should be determined by the allowable ripple amount of buck mode. Therefore, and capacitor can be obtained as following Eqs.
[11]
where, Δ
i
, Δ
v
are allowable current and voltage ripple, respectively,
T_{s}
is switching period.
2.1.2 Boostmode operation
Fig. 4
shows the boost mode operation. As shown in the figure, boost mode operation is affected by the
S_{2}
. Switch
S_{1}
should be always turned on at this mode, and
S_{3}
should be complementarily operated from
S_{2}
. The voltage gain of the boost mode is obtained by the following equations.
Boostmode operation according to whether the switch is on or off.
From (3), as the duty ratio of
S_{2}
increases, the voltage gain increases similarly to the general boost converter. However, due to the complementary switching of
S_{3}
, instantaneous transition of the regenerative and generative operation is achieved. Regenerative operation analysis will be explained in the next chapter.
2.1.3. Regenerative buckmode operation
Fig. 5
shows the regenerative buck mode operation where the regenerative current flows to the battery by the switch of
S_{3}
operation. The following equation is described by the voltage gain according to the duty of
S_{3}
.
Regenerative buckmode operation according to whether the switch is on or off.
As shown in (4), voltage gain is the same as the buck converter operation. If the duty of
S_{3}
is increased, regenerative energy also increases.
3. Proposed Control Method of Bidirectional DCDC Converter for Optimal DClink Voltage
Fig. 6
shows the proposed overall control block diagram, which is briefly composed of the inverter control block and the DCDC converter control block diagram. Among these, the inverter control block uses the general vector control method.
Overall control block diagram for optimal DClink voltage
The proposed DCDC converter control block diagram is composed of the voltage reference generator for the optimal DClink voltage of the PMSM drive, the DClink voltage controller, and the PWM generator for the DCDC converter switch control according to the operation modes illustrated in chapter 2.
 3.1 Proposed PWM Generator for affection the input voltage
As shown in
Fig. 7
, the peak value of the carrier varies according to the battery voltage, which is the input of the DCDC converter. To operate for buck mode, if the voltage controller output is less than the input battery voltage, the voltage reference is compared with the carrier which value is from zero to the battery voltage. And then, the output duty
D_{buck}
controls the switch
S_{1}
. During this operation, switch
S_{2}
and
S_{3}
should be turned off and turned on, respectively. To achieve this operation, the lower carrier wave for boost mode operation has an offset, the amount of which is the input battery voltage. Therefore, the lower carrier has a value from the battery voltage to twice the battery voltage. This configuration of the carrier keeps the duty
D_{boost}
for
S_{2}
turned on and the duty
D_{regen _ boost}
for
S_{3}
turned off during the buckmode operation.
Proposed PWM Generator for controlling the bidirectional power operations
On the other hand, the boost and regenerative buck mode operation is activated when the DClink voltage is more than the battery voltage as aforementioned in Chapter II. Because these modes are always complementarily operated, the duty of
S_{2}
and
S_{3}
is configured as
During these modes, switch
S_{1}
is always high due to the configuration of proposed PWM generator. This switch operation is used for the bidirectional power flow of the boost and the regenerative buck operations.
Fig. 8
shows the PWM generator operation of
Fig. 7
according to the controller output voltage reference. The switching operation illustrated in chapter 2 is achieved by the proposed PWM generator as shown in the figure.
Carrier and reference voltage composition for PWM switching
As aforementioned, in the case of the buck operation, the voltage reference is increased until the output voltage reaches the input voltage. In this case, the regenerative buck PWM switch is always high and the boost PWM switch is off. When the voltage reference is more than input voltage, buck PWM switch is always high, at the same time, the boost PWM switch and the regenerativebuck PWM switch are complementarily switching for boosted output voltage.
 3.2 Effect of the optimal DClink voltage control on the SVPWM duty
If the inverter generates pure ac voltage, an increase of the output voltage results in extending the controllable region without the current ripple. However, because general control method for the inverter uses the PWM switching, the excessive DClink voltage increases the current ripple of PMSM.
The steady state of a phase current ripple by the PWM is calculated using the following equations.
where
S_{a}
is the switching function,
L_{s}
is a phase inductance,
R_{s}
is a phase resistance,
δ
is the voltage angle,
ω_{r}
is motor speed,
L_{d}
is the daxis inductance,
L_{q}
is the qaxis inductance, and
θ_{r}
is rotor position.
From the equations, a phase current ripple by PWM is determined by the DClink voltage, the speed of PMSM, and the phase current magnitude. Therefore, a phase current ripple can be reduced when there is a small voltage difference between the DClink voltage and the backEMF magnitude of the motor. The optimum voltage of DClink used in this paper is described as (7).
In (7), the gain
K
is set as
for linear modulation of the SVPWM. From this equation, the effective and zero vectors of the SVPWM are obtained using the following equations.
As shown in the equations, when the DClink voltage is controlled by the optimal value as (7), the variation of the voltage reference magnitude disappears on the vectors of the SVPWM. These equations mean that the ratio of the fundamental component and the ripple component from the current controller can be fixed regardless of the modulation amplitude. The problem using the conventional fixed DClink voltage is that the current ripple affected by the voltage reference is magnified at the low modulation amplitude. In contrast, with the proposed control method, the affect of the ripple component is fixed regardless of the modulation amplitude.
Fig. 9
shows the SVPWM switching with the varied DClink voltage. As shown in this figure, despite the fixed phase voltage reference magnitude, the modulation amplitude is varied because the peak value of the carrier is varied by the DClink voltage. If the DClink voltage is small, the PWM duty is increased as the circumstance A. In contrast, if the DClink voltage is high, the duty is decreased as the circumstance B. This means that the output power can be controlled by the DClink voltage, even though the modulation amplitude of the SVPWM is optimally fixed.
SVPWM switching with the varied DClink voltage
 3.3 Reduction of the deadtime effect by the optimal DClink voltage
Fig. 10
shows the distorted output voltage from the deadtime in the PWM inverter operation. Assuming that the varied voltage reference can be ignored during the switching period, the inverter output voltage, which is the PWM duty from the SVPWM voltage reference, is reduced by the deadtime.
Deadtime effect of PWM inverter
Reduced duty variation can be easily compensated by the constant switch onoff operation. However, the distorted voltage is varied according to the direction of the phase current, and this distorted voltage is expressed as follows.
where
T_{d}
is deadtime,
T_{on}
is switchon time, and
T_{off}
is switchoff time.
From this voltage error, the harmonic current ripple can be described as follows
[7]
.
where
Z_{L}
is the motor impedance and
φ
is the difference between the voltage and current angle.
From (13), the phase and dqaxis currents have the 6th harmonic component by the deadtime. Conventional research for reducing this effect has been developed
[7

10]
. The most common deadtime compensation method is the deadtime of each switches are differently applied according to the phase current direction
[8]
. However, this method needs a Zero Crossing Circuit (ZCC) for detecting the direction of the phase current, and the detecting error occurs at a nearly zero point of the phase current because of the sensing ripple. On the other hand, a compensation method for the voltage which derives from the deadtime effect has been developed
[7]
. This method is based on the fact that the harmonic caused by the deadtime effect is a specific component according to the rotor position. Therefore, it can be compensated by extracting the current ripple component by the PLL from the rotor position. However, this method is affected by the correctness of the feedforward term of the current controller. Besides, this compensation voltage is affected by the antiwindup of the current controller.
With the proposed varied DClink voltage control method, the error voltage from deadtime is described in the following equations.
Because the inverter current for the PMSM drive exists as (5), which is the integration of the voltage difference between the inverter and the backEMF, the deadtime effect can be removed on the phase current if the DClink voltage is controlled to be perfectly optimal. Practically, the deadtime effect cannot be totally removed by the optimally controlled DClink voltage because the modulated voltage from the SVPWM is varied according to the voltage angle, despite having the same magnitude as the reference voltage.
Because none of the conventional methods reduce the deadtime effect, but rather compensates it, this effect remains on the phase current in the case of specific motor parameters or operating circumstances. Moreover, if the error is too large to compensate, these compensation methods can no longer retain the deadtime ripple component. As a result, in contrast to conventional methods, due to the optimally controlled DClink voltage, proposed method reduces the deadtime effect regardless of the motor parameters.
4. Experimental results
Tables 1
and
2
show the parameters used in the experiment. The control frequency of the DCDC converter is 20 [kHz] and that of the inverter is 10 [kHz], respectively.
Parameters of the converter
Parameters of the converter
Parameters of the PMSM
Fig. 11
shows the experimental setup. As shown in the figure, the experimental setup is composed of the MGset and the DCDC converter. The MGset is composed of the test PMSM and induction motor for the load. The source of the load motor is from 3ph of the ACsource, which is regulated by the ACDC PWM converter. The source of the proposed DCDC converter is from the series connected leadacid batteries and its voltage is 98 [V].
Experimental setup: (a) DCDC converter setup; (b) MGset.
The inductor and capacitor of the proposed DCDC converter is designed so that the current ripple is 2 [A] and the voltage ripple is 5 [V]. However, because the calculated capacitance does not consider the ESR(Equivalent Series Resistor), capacitor is selected by experimental trial and error to satisfy the voltage ripple.
As aforementioned in chapter II, this limitation is determined on the buckoperation region. In the boost operation, the voltage and current ripples are reduced because a higher voltage to regulate the current is alternately applied to the inductor.
Fig. 12
shows the experimental result of the optimal DClink voltage control method according to the motor speed and dqaxis currents. In the case where the motor speed and load torque are zero, theoretically, the necessary DClink voltage is also zero.
Experimental results of the optimal DClink voltage control: (a) motoring operation; (b) Regenerating operation
However, the limitation of the minimum DClink voltage is needed for initial operation current control. In this paper, this minimum limitation is set as 50 [V]. Because this target voltage is on the buck mode operation, the output voltage has the ripple of the designed DCDC converter parameter. However, in boost mode operation, the voltage ripple is hardly seen because of the aforementioned alternative boost and regenerative buck operation. As shown in the figure, the DClink voltage is increased according to the motor speed. In this case, the DClink voltage starts to increase when the calculated optimal DClink voltage is more than the minimum limitation voltage.
During the target speed of 2000 [rpm] operation, the torque reference of 5 [Nm] is applied to the PMSM to generate this torque. The generated torque increases the DClink voltage because of the backEMF from the applied dqaxis currents. The increased DClink voltage occurs in both the regenerating and motoring operations.
Fig. 13
shows a comparison of the dqaxis currents between the conditions of the rated DClink voltage and the optimally controlled DClink voltage. As shown in the figure, the current ripple is reduced by the proposed control method. In the case of the constant DClink voltage, the current ripple is increased when the controlled current value is low. The reason for this phenomenon is that the current ripple of the inductance load is increased when the gap of the applied voltage and backEMF is large. However, with the proposed control method, the current ripple is reduced because of the small voltage gap.
Comparison of the dqaxis currents ripple: (a) Conventional fixed DClink voltage; (b) Proposed varied DClink voltage.
Fig. 14
shows the comparison result of the deadtime effect between the rated DClink voltage and the proposed varied DClink voltage. The applied deadtime is 5 [us] in both cases. When the rated DClink voltage is applied, the 6th harmonics of the phase current is comparatively large because of the excessive deadtime. However, the effect of the deadtime is reduced with the proposed control method as shown in the figure. The THD of the conventional method is 7[%]; however, with the optimal DClink voltage control method, the THD can be reduced to 5.6[%].
Comparison of the phase current ripple: (a) Conventional DClink voltage control condition; (b) Proposed DClink voltage control condition
Fig. 15
shows the comparison of the deadtime compensation effect. The excessive deadtime makes the phase current has large amount of harmonics as shown in
Fig. 15(a)
. With the general deadtime compensation method of
[8]
, the phase current is more sinusoidal than the
Fig. 15(a)
as described on
Fig. 15(b)
. However, with the varied DClink voltage condition, not only the deadtime effect is reduced, but also the current ripple is reduced as shown on
Fig.15(c)
.
Comparison of the deadtime compensation: (a) Conventional DClink voltage control condition with no deadtime compensation; (b) Conventional DClink voltage control condition with deadtime compensation; (c) Proposed DClink voltage control condition with deadtime compensation.
Table 3
shows the efficiency comparison of the conventional and proposed DClink voltage condition. The applied deadtime is 5[us]. In the proposed control method, the DC/DC converter operates in buck mode at 500[rpm], and boost mode at 2500[rpm]. In conventional method, all results are obtained at the rated DClink voltage condition. As shown on the table, the total efficiency is almost same because increased inverter efficiency is counterbalanced by the DC/DC converter efficiency. It is caused by the efficiency of the buck mode operation which has comparatively lower efficiency than the boost mode operation. Despite of this problem, it can be overcome by adapting ZVZCS(Zero Voltage Zero Current Switching) resonant converter. Moreover, the improvement of inverter efficiency at overall operating area has many advantages in the traction system for the robust control and noise problem.
The efficiency comparison of the conventional and proposed DClink voltage condition
The efficiency comparison of the conventional and proposed DClink voltage condition
5. Conclusion
This paper illustrates the design and control methods of bidirectional DCDC converter for the optimal DClink voltage of PMSM drive. To control the DClink voltage optimally, the DClink voltage is controlled by the reference considers the backEMF voltage of PMSM.
The DCDC converter topology is composed to operate buck, boost and regenerativebuck for wide controllable voltage. To control these operations with smooth transition, the PWM generator consists of double carriers affected by the input voltage is proposed. Also, the analysis of optimally controlled DClink voltage on PMSM drive, especially on the improvement of deadtime effect is illustrated in this paper.
Many comparison experiments are performed for verifying the proposed control algorithm and analysis. These results show that the optimally controlled DClink voltage makes to reduce the dq axis current ripples on low speed and high current operation. Although the total efficiency improvement is insufficient, high performance motor drive due to the reduction of dq axis current ripple can give many advantages for EV/HEV traction system using the bidirectional DC/DC converter.
BIO
TaeHoon Kim He received the B.S. and M.S. degrees in electrical engineering from Sungkyunkwan University, Suwon, Korea, in 1988 and 1990, respectively. From 1995, he joined LG precision, and currently, he is a research engineer of Maritime R&D center in LIG Nex1. His research interests include power electronics for military application.
JungHyo Lee He received the B.S. degree in electrical engineering from Konkuk University, Seoul, Korea, in 2006, and the M.S. and the Ph.D. degrees in electrical engineering from Sungkyunkwan University, Suwon, Korea, in 2008 and 2013, respectively. From 2013, He has been a senior researcher of automotive component R&D Team in LG Innotek. His research interests include converters and inverters for motor drive application.
ChungYuen Won He received the B.S. degree in electrical engineering from Sungkyunkwan University, Suwon, Korea, in 1978, and the M.S. and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1980 and 1987, respectively. From 1990 to 1991, he was with the Department of Electrical Engineering, University of Tennessee, Knoxville, as a Visiting Professor. Since 1988, he has been with a member of the faculty of Sungkyunkwan University, where he is a Professor in the College of Information and Communication Engineering. He is also the Director of Samsung Energy Power Research Center. He was the President of the Korean Institute of Power Electronics in 2010. Since 2011, he has been the Director of the Korean Federation of Science and Technology Societies. His current research interests include the power electronic of electric machines, electric / hybrid vehicle drives, and power converters for renewable energy systems.
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