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Analysis of Tunnelling Rate Effect on Single Electron Transistor
Analysis of Tunnelling Rate Effect on Single Electron Transistor
Journal of Electrical Engineering and Technology. 2014. Sep, 9(5): 1670-1676
Copyright © 2014, The Korean Institute of Electrical Engineers
  • Received : June 24, 2013
  • Accepted : March 10, 2014
  • Published : September 01, 2014
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About the Authors
L Sheela.
Corresponding Author: Dept. of Electrical and Electronics Engineering, Regional Centre of Anna University, Tirunelveli, TamilNadu, India. (sheelarctvl@gmail.com)
N. B. Balamurugan
Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering, Madurai, Tamilnadu, India. (nbbalamurugan@tce.edu)
S. Sudha
Dept. of Electrical and Electronics Engineering, Regional Centre of Anna University, Tirunelveli, TamilNadu, India. ({cutesuthi, jasmine.agla }@gmail.com)
J. Jasmine
Dept. of Electrical and Electronics Engineering, Regional Centre of Anna University, Tirunelveli, TamilNadu, India. ({cutesuthi, jasmine.agla }@gmail.com)

Abstract
This paper presents the modeling of Single Electron Transistor (SET) based on Physical model of a device and its equivalent circuit. The physical model is derived from Schrodinger equation. The wave function of the electrode is calculated using Hartree-Fock method and the quantum dot calculation is obtained from WKB approximation. The resulting wave functions are used to compute tunneling rates. From the tunneling rate the current is calculated. The equivalent circuit model discuss about the effect of capacitance on tunneling probability and free energy change. The parameters of equivalent circuit are extracted and optimized using genetic algorithm. The effect of tunneling probability, temperature variation effect on tunneling rate, coulomb blockade effect and current voltage characteristics are discussed.
Keywords
1. Introduction
According to International Technology Roadmap for Semiconductors (ITRS), when MOSFET dimension is scaled down beyond 10nm, it has more limitations such as short channel effects. The above drawback leads to emerge of new devices such as single electron transistor that performs at nano scale level. SET has more attention because of its small size, extremely low power dissipation and its similar structure of MOSFET.
SET consists of two small tunnel junctions and an “island” between them, usually with a third gate electrode capacitively coupled to the island as in Fig. 1 [1] . A transfer-Hamiltonian approach is used to compute the tunneling rates for the coupling of the quantum dot levels [2] . A 3D simulator of semiconducting nano crystal based single electron transistor is presented. The analysis is based on the self consistent solution of Poisson and Schrodinger Equations [3] . The quantum dots are modulated using a quantizer block in order to correlate the signal quantified to the energy levels, also introduced a clock, to get different starting time for the island event [4] . A SET was developed based on orthodox theory of Single Electrons using Master Equation (ME) [5] . Their model proposes the current - voltage characteristics based on circuit simulator SPICE with conventional electronic elements. An analytical model for I-V characteristics of Single Electron Transistor is developed to calculate the current carried by one extra electron on the central island and with tunneling rates given by orthodox theory phenomena [7] . Shahhosei, investigated the effects of asymmetry in the source and drain capacitance of metallic island Single Electron Transistor. Their technique was extended to model the Kink effect appearing in the device, next to the threshold voltage [8] . Adaptive Monte Carlo algorithm is developed for the simulation of single electron transition [9] . The aim of their work is to model SET, build a simulator and to simulate current voltage characteristics of SET using Graphical User Interface (GUI) in MATLAB [10] .
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Structure of Single Electron transistor
Our aim is to model the single electrode and the single dot using HF and WKB respectively. The tunneling rates are calculated from the Fermi golden rule. The effect of temperature on tunneling of electron from source to dot and dot to drain is also analyzed. In other method tunneling rate is calculated from the electrical equivalent circuit and the parameters are extracted and optimized using genetic algorithm.
This paper is organized as follows: Section II explain the Mathematical modeling of SET that includes M element calculation, tunneling rates and drain current calculation. In section III, we present the equivalent circuit modeling of SET with Tunneling rate calculation; drain current calculation and optimization techniques. In section IV, the results are analyzed. Conclusion is drawn in section V.
2. Mathematical Modeling
Modeling is the technique of representing a observable fact with a set of mathematical equations. Predictions can be made based on the behavior and performance of the system by changing its variables. This is also favorable approach to test the most optimal and the best performance of a device before the real fabrication. In our approach, the basic idea is to decompose the problem in two stages, M element [9] and tunneling rates and drain calculation.
- 2.1 M-Element calculation
The matrix element (M) represents the tunnel transmission through a barrier with energies close to E s . The matrix element is calculated using Bardeen formula.
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Where m - mass of electron, ħ - Reduced plank’s constant, ψ elec and ψ dot are the wave functions of electrode quantum dot. While ψ elec and ψ dot are calculated from the Poisson-Schrodinger equation. ψ elec is calculated by Hartree Fock approximation, it is beneficial that the Hartree Fock approximation supports anti symmetry. The Hartree Fock approximation is applied for SET to find the wave function of electrode given below
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where ϵ 1 is the spin constant. In SET only one electron wave function is present (i. e) ψ will be Φ 1 (1). The ψ dot is calculated from Wetzel Kramers Brilloun approximation, as given in Eq. (3)
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The total energy and the potential energy is used to calculate the E- v ( x ). According to carrier conduction in a Si - based Single Electron Transistor, effect of gate bias, the quantum dot width is 20 Å. The ψ elec and ψ dot are used in the computation of M-element.
- 2.2 Tunneling rates and drain current calculation
The tunneling rates from source to dot and dot to drain are calculated using Fermi Golden Rule [3] . The Fermi Golden Rule approximates the sum by an integral with respect to energy. So the tunneling rate from source to dot is,
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And tunneling rate from dot to drain is,
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Where f(E s ) is the electrode Fermi function, g Es is the number of electrons on the energy level E s , ρ(Es) is the electrode density and I Es is the number of free states on the energy level E s . The calculated tunneling rates are substituted to the master equation from which the drain current I d can be found.
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The multiplication of the probability and the difference rate [Γ d , D (N)-Γ S , d (N)] describes the net current flowing through from source to drain.
3. Equivalent Circuit Modeling
An SET can be visualized as having a double barrier potential. The double junction is a circuit consists of two tunnel junctions in series, which form an island between them. The junctions are biased with a voltage source connected between the source and drain. For very small bias, no current own as the electrons and do not have enough energy to overcome the barrier. The equivalent circuit of SET is shown in Fig. 2 from which the tunneling rate and drain current is calculated.
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Equivalent circuit of SET
- 3.1 Tunneling rate and drain-current calculation
The probability distribution of electrons in the SET dot is obtained from the stochastic process, allowing the calculation of device characteristics [8 , 10] . The goal is to simulate tunneling rate calculation and current-voltage characteristics based on equivalent circuit. On the occurrence of electron tunneling, the free energy change of the system before and after tunnel event plays a key role.
In order to calculate total charging energy, the voltage applied on the tunnel capacitor is determined. Finally, the total charging energy on the SET system can be calculated as follows:
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Since the values of external power supply are kept constant, the effect on electron tunnelling process only influences the terms of Q G 2 /2C Σ . It is also necessary to calculate the work done by external voltage source due to tunnel event, which in turn is necessary for the tunneling rate calculation. There are two types of tunnel events, i.e., electron tunnels through the capacitor C 1 as shown in Fig. 3 and Fig. 4 indicates the electron tunnelling through the capacitor C 2 . The amount of the work done by external voltage source is different from one event to another. The charge carriers enter via junction1 (C 1 and R 1 ) are kept in same state due to high resistance, eventually another electron leaves through junction2 (C 2 and R 2 ).
The most important requirement for the occurrence of single electron tunnelling is that the total energy of the transistor must decrease due to one electron tunnelling [4] . This condition is called as Coulomb blockade. The free energy of the complete SET circuit can be calculated from work done by voltage source. The free energy is defined by the difference in the total charging energy and total work done by the power supply, as follows:
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The charge flow in SET circuit when an electron tunnel through the capacitor C1
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The charge flow in single electron transistor circuit when an electron tunnel through the capacitor C2
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Change in free energy before and after electron tunneling will determine occurrence of electron tunneling. The free energy before and after tunneling through C 1 can be calculated from Eqs. (9) and (10).
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On the other hand, when the electron tunnel through the capacitor C 2 the free energy change when the before and after tunneling is calculated as follows:
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Where Q=Ne-Q 0 . Using the values of ∆F, single electron tunneling rates across each of two junctions is determined. Each rate depends on both the tunneling resistance of the junction and the total energy change of the system due to the tunneling event. The rate of tunneling probability is described as per Eqs. (13) and (14).
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Considering the standard boundary conditions and applying normalization and transformations, finally, the current can be calculated by,
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The electron tunnelling rate, which is represented by Г±, can be easily obtained from the basic rule calculation.
- 3.2 Optimization technique
Parameter extraction is the minimization of difference in measured parameter and modeled parameter. Two methods available for parameter extraction are: direct extraction and optimization. In the former method lot of presumptions are needed to get accurate results. Also, the mathematical model equation is complicated and hard to solve. Hence we adapted the optimization method. Optimization method is further classified to numerical optimization and stochastic search algorithm. Some of the numerical optimization techniques are Gradient based method such as Levenberg-Marquardt method. The major drawbacks of numerical optimization are: 1) It is more sensitive to initial values 2) Poor convergence. Fuzzy logic can be used to improve the output of the numerical methods. Since fuzzy logic utilizes the fitting rules, formulation of rules is a tedious task. These consequences are overcome by the stochastic search algorithm. Stochastic search algorithms are especially works driven by evolutionary computation (EC). Earlier genetic algorithm was used for parameter extraction Although genetic algorithm is easy to code, it lacks in precision and has poor convergence.
The optimization technique is modeled with the definitions such as f(Vd, Vg, Vs)=Id , f-Ids-Vds or Ids-Vgs current equations, Vd - Drain voltage, Vg -Gate voltage, V s - Source voltage, I d - Drain current. The initial population creation is done with parameter vector as chromosome and the creation of population of solutions is done by considering the range and resolution of the parameters The fitness function is chosen as Rank Based method The selection of members for cross over are based on Roulette Wheel selection, the cross over type is multipoint cross over, the cross over probability is chosen as input parameter.
4. Results and Discussion
- 4.1 Mathematical model
To find out the Id-Vgs characteristics it is important to know about tunneling rates of SET. The tunneling rates are calculated using Fermi Golden rule. The calculated tunneling rates are simulated in MAPLE. Here the energy level taken in the range of 0.125 to -0.125 eV.
From Fig. 5 shows the plot for tunneling rate and energy level. It is clear that, when we increase the energy level, the tunneling rate will increase gradually from source to dot and also from dot to drain of single electron transistor When the voltage is applied to the device, a electron moves from source to dot initially, thereby reducing energy level of dot based on the tunneling rate to accept that electron
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Plot between tunneling rate and energy level
In semiconductor devices, leakage in p-n junction increases due to increase in temperature. But for quantum devices, electron transport occurs by thermionic emission; that is conduction mechanism may be assisted by tunneling. From Figs. 6 and 7 , we analysed that when temperature of SET is increased, it remain turned off or remain in same state. As the temperature is reduced, the thermionic emission current falls and tunneling effects begins to dominate the conduction process.
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The classical turning points for the tunneling rates for negative temperature range.
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The classical truning points for the tunneling rates for positive temperature range
From the graph as in Fig. 8 , it is clear that, the energy of the device will increase with respect to the voltage that is temperature dependent. It reflects the changes in electro static and chemical potential at electron charging steps. The I d -V gs characteristics of Single Electron Transistor are shown in the Fig. 9 . The position and width of the current peaks are clearly linked to the bias dependence of the chemical potentials and energy levels. The shape of the conductance peak is mainly determined by temperature dependent distribution of electrons in quantum dot and not by the tunneling rates.
Fig. 8 . Plot between energy and gate voltage with temperature differences
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Plot between energy and gate voltage with temperature differences
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Id-Vgs characteristics of SET with Coulomb blockade
- 4.2 Equivalent circuit model
The characteristics of SET are calculated for the parameters of C 1 = 0. 1 zF(zeto), C 2 = 10 aF, C G = 1F, R 1 = 15* µOhm, R 2 = 250* µOhm, elemental charge Q = 1.0 e -20 C for different voltage levels and background charge =0. The current-drain voltage characteristics for SET are shown in Fig. 10 The calculation was carried out for an operating temperature of 10K, V G = 0V and the elemental charge Q 0 is assumed as zero.
Fig. 10 . Coulomb Blockade observations for different variable drain voltage
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Coulomb Blockade observations for different variable drain voltage
If |V| < e / ΣC, current is zero. The state at which the current is zero is called coulomb blockade that suppresses tunneling of electron at low bias condition. When external voltage V is increased above the threshold voltage by charging energy, coulomb blockade can be removed and the current flow.
It is also clear form Fig. 11 that the small values of input voltage V reaches the threshold voltage Vt for long event oftime. So, the capacitor takes a long time for charging and progressive rise in rates. Figs. 12 and 13 shows the electrical characteristics of SET at different temperature range of 1000K and 10K respectively. The coulomb oscillations of SET are clear at low temperature (10K). IV characteristics show some suppression of coulomb blockade by broadening at high temperature. It also reveals the fact that it is not possible to obtain coulomb blockade in device characteristics at high temperature.
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Differential conductivity of SET for different voltage potential
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Typical electrical characteristics of SET at temperature of 100
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Typical electrical characteristics of SET at temperature of 10K
The parameters are being extracted and also being optimized. The I-V characteristics of single electron transistor are obtained using the optimization technique called Genetic Algorithm. From Figs. 14 - 16 , we foung convergence of electrical characteristics is very close to current voltage characteristics without coulomb blockade effects. The chosen genetic algorithm parameter are: population size-50, number of generations -500 and mutation rate-0. 4, and also it produces maximum error of less than 0. 05% with CPU time: ~3 minutes. From these performance metrics it is clearly shown that GA takes little more CPU time and has a slower convergence rate to obtain better results and also it produces better performance when compared with equivalent circuit model.
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GA Result : Ids-Vgs for Vds = 0. 05V
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GA Result Ids-Vgs for Vds= 2. 5 V
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GA Error Value Calculation
From the curves it is evident that the GA has produced accurate results with error not greater than 0. 05%.
5. Conclusion
In our paper, we showed that biased dependent tunneling rates are calculated accurately from self consistent wave function in the electrode. The resulting I d -V gs characteristics with coulomb oscillations are consistent with experimental results [3] . The shape of the conductance peak is mainly determined by temperature dependent distribution of electrons in quantum dot. The influence of temperature and device parameters on current-voltage characteristics reveal the fact that at high temperature coulomb blockade is not possible. The parameters of SET are also extracted using equivalent circuit model. The simulated results are obtained by direct method. I d -V d characteristics are optimized using genetic algorithm that demostrates the improvement in terms of stablity, arruracy and convergence.
BIO
L. Sheela rece ived her B.E Degree in Electrical and Electronics Engineering from Mepco Schlenk Engineering College, Sivakasi, Tamilnadu, India. She had received her M.E degree in Applied Electronics from P.S.G. College of Technology, Combatore, India. She is currently working as a Assistant Professor in Department of Electrical and Electronics Engineering, Anna University: Regional Centre, Tirunelveli, Tamilnadu, India. She is pursuing her research in the area of Modeling and simulation of Nanodevices. She has published 4 papers in International Conferences and 3 papers in journals. Her research also includes MEMS.
N. B. Balamurugan received his B. E and M. E degrees, both in Electronics and Communication Engineering from the Thiagarajar College of Engineering(TCE), Tamilnadu, India. He has obtained his Ph. D degree in nanoelectronics at Anna University, India. From 1998 to 2004, he worked as a lecturer in R.V.S. College of Engineering and Technology, Tamilnadu, India. He is currently as an Assistant Professor in the Department of Electronics and Communication Engineering, Thiagarajar College of Engineering (TCE), Tamilnadu, India. He has published more than 50 research papers as sole or joint author in the field of device modeling and simulation. His research interests include modeling and simulation of semiconductor device structures.
S. Sudha received BE Degree in Information Technology and ME Degree in Electrical Engineering from Anna University, Chennai, Tamilnade. Her interests are Nano Electronics and Networking.
J. Jasmine received BE Degree and ME degree in Electrical Engineering from Anna University, Chennai, Tamilnadu. Her interests are Nano Electronics and Signal Processing.
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