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Analysis of an Interleaved Resonant Converter for High Voltage and High Current Applications
Analysis of an Interleaved Resonant Converter for High Voltage and High Current Applications
Journal of Electrical Engineering and Technology. 2014. Sep, 9(5): 1632-1642
Copyright © 2014, The Korean Institute of Electrical Engineers
  • Received : October 04, 2013
  • Accepted : May 07, 2014
  • Published : September 01, 2014
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About the Authors
Bor-Ren Lin
Corresponding Author: Dept. of Electrical Engineering, National Yunlin University of Science and Technology, Taiwan. (linbr@yuntech.edu.tw)
Chih-Chieh Chen
Dept. of Electrical Engineering, National Yunlin University of Science and Technology, Taiwan. (inbr@yuntech.edu.tw)

Abstract
This paper presents an interleaved resonant converter to reduce the voltage stress of power MOSFETs and achieve high circuit efficiency. Two half-bridge converters are connected in series at high voltage side to limit MOSFETs at Vin /2 voltage stress. Flying capacitor is used between two series half-bridge converters to balance two input capacitor voltages in each switching cycle. Variable switching frequency scheme is used to control the output voltage. The resonant circuit is operated at the inductive load. Thus, the input current of the resonant circuit is lagging to the fundamental input voltage. Power MOSFETs can be turn on under zero voltage switching. Two resonant circuits are connected in parallel to reduce the current stress of transformer windings and rectifier diodes at low voltage side. Interleaved pulse-width modulation is adopted to decrease the output ripple current. Finally, experiments are presented to demonstrate the performance of the proposed converter.
Keywords
1. Introduction
Power converters for medium or high power applications have been proposed and applied for many industry applications, such as fuel-cell power system [1] , charge system [2] and ship power system [3] . For three-phase AC/DC power conversion systems, the front stage is a power factor corrector (PFC) and the second stage a DC/DC converter. The DC bus voltage of a three-phase PFC may be equal to 800V. In DC/DC converter, power MOSFETs with 900V voltage stress will result in high turn-on resistance. Three-level converters [4 - 9] with low voltage stress and high switching frequency have been presented in DC/DC converters for high voltage applications. Based on the neutral-point clamped diodes or flying capacitor, the voltage stress of active switches is clamped at Vin /2. However, two input split capacitor voltages maybe unbalanced and will increase the voltage stress of active switches beyond Vin /2. In [1] and [10] , flying capacitor is adopted to the conventional three-level neutral point clamped converter to automatically balance two input capacitor voltages. Three-level zero voltage switching (ZVS) converters [11 - 17] have been presented to reduce the switching losses and increase the circuit efficiency. Pulse-width modulation (PWM) schemes are adopted to generate the PWM signals for active switches and to regulate output voltage. However, the ZVS condition of active switches is related to the load condition and input voltage so that it is difficult to implement ZVS turn-on for all switches over the entire load range. In order to extend the ZVS condition over the whole load range, resonant converters [18 - 22] have been proposed to achieve ZVS turn-on over the wide load range and input voltage variation. However, the ripple current at the output capacitor in resonant converter is higher than the output ripple current in the conventional half-bridge or full-bridge PWM converter. In order to limit the output ripple voltage in the desired ripple voltage specification, several capacitors are connected in parallel to reduce the resultant series equivalent resistance. Therefore, the large capacitance is normally adopted at the output side in the resonant converters. In order to reduce the output capacitance and output ripple current in the resonant converters, parallel resonant converter with interleaved PWM scheme has been presented in [23 - 25] .
A new parallel resonant converter is presented for high input voltage and high load current applications. Two circuit modules connected in parallel in order to share load power and reduce the current stress of all passive and active power components. These two circuit modules are controlled with the phase shift of one-fourth switching period in order to reduce the ripple current at the output capacitor. Thus, the size of output capacitor can be reduced. In each circuit module, two half-bridge converters are connected in series at the primary side to reduce the voltage stress of each active switch at Vin /2. Flying capacitor is connected between two half-bridge converters such that two input capacitor voltages can be automatically balanced in each switching cycle. Series-parallel resonant tank is adopted in each half-bridge converter to achieve ZVS turn-on for all switches over the entire load range. Finally, experiments were provided to verify the performance of the proposed converter.
2. Circuit Configuration
Fig. 1 gives the circuit configuration of the proposed converter for three-phase switching mode power supplies. The three-phase AC/DC converter with power factor correction is used in the front stage to reduce line current harmonics and provide a stable DC bus voltage for second stage DC/DC converter. The DC bus voltage is about 750V-800V for three-phase 480V utility input with power factor correction. The proposed parallel DC/DC converter with low voltage stress MOSFETs is adopted in the second stage for high load current applications. Two circuit modules are adopted in the proposed converter to share load current and reduce the current rating of active and passive components. The first circuit module includes Cin1-Cin2, Cf1, S1-S4, CS1-CS4, Cr1-Cr2, Lr1-Lr2, T1- T2, D1-D4 and Co . In the same manner, the components of Cin1-Cin2, Cf2, S5-S8, CS5-CS8, Cr3-Cr4, Lr3-Lr4, T3- T4, D5-D5 and Co are included in the circuit module 2. Cin1 and Cin2 are two input capacitances. Cr1-Cr4 are the series resonant capacitances. Lr1-Lr4 are the series resonant inductances. Lm1-Lm4 are the magnetizing inductances of transformers T1-T4 , respectively. D1-D8 are the rectifier diodes and T1-T4 are the isolated transformers. Cf1 and Cf2 are the flying capacitances. Each circuit module includes two resonant converters with half- bridge converter leg. In circuit module 1, the first resonant converter includes the components of S1, S2, Cr1, Lr1, T1, D1, D2 and Co . The second resonant converter includes S3, S4, Cr2, Lr2, T2, D3, D4 and Co . Co is the output capacitance. The primary sides of two resonant converters are connected in series in order to limit the voltage stress of each active switch at Vin /2. Active switches S1 and S3 have the same PWM waveforms. In the same manner, S2 and S4 have the same PWM signals. However, the PWM waveforms of S1 and S2 are complementary each other to avoid the short circuit in each half-bridge leg. In order to balance two input capacitor voltages vCin1 and vCin2 , Cf1 is connected between the AC terminals b and c and Cf2 is connected between the AC terminals f and g . If S1 and S3 are in the on-state and S2 and S4 are in the off-state, then vCf1=vCin1 . On the other hand, vCf1=vCin2 if S2 and S4 are in the on-state. Since each active switch has the equal turn-on time, the flying capacitor voltage can be derived as vCf1=vCf2= vCin1=vCin2=Vin /2 and two capacitor voltages vCin1 and vCin2 are automatically balanced in each switching cycle. The frequency modulation scheme is used to regulate output voltage Vo . If the operated switching frequency is lower than the series resonant frequency, active switches S1-S8 are turned on at ZVS and rectifier diodes D1-D8 are turned off at ZCS. Thus, the switching losses of active switches are reduced and the reverse recovery problem of rectifier diodes is improved. In the proposed converter, each resonant converter supplies one-fourth of load power to output load for the medium/high load current applications.
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Circuit configuration of the proposed converter with two circuit modules.
3. Operation Principle
The circuit operations of the proposed converter are discussed with the following assumptions to simplify the system analysis. (1) Transformers T1-T4 are identical with the same turns ratio n=np/ns1=np/ns2 and same magnetizing inductances Lm1=Lm2=Lm3=Lm4=Lm , (2) S1 - S8 have the same output capacitance CS , (3) Cin1=Cin2 , (4) Cr1=Cr2 =Cr3=Cr4=Cr , and (5) Lr1=Lr2=Lr3=Lr4=Lr . The main PWM waveforms of the proposed converter during one switching cycle are given in Fig. 2 . Due to the on/off conditions of switches (2) S1 - S8 and rectifier diodes (2) D1 - D8 , the proposed converter has twelve operation modes in one switching period. The corresponding equivalent circuits of twelve operation modes are shown in Fig. 3 . Before time t0 , (2) S1 - S4 are all turned off in circuit module 1. iLr1 and iLr2 are positive and negative, respectively. Therefore, CS1 and CS3 are discharged and CS2 and CS4 are charged. Since iLr1 < iLm1 and iLr2 > iLm2 , diodes D2 and D3 are in the on-state. In circuit module 2, S6 and S8 are in the on-state and diodes D5 and D8 are conducting. Lr3 and Cr3 are resonant with the applied voltage Vin /2 - nVo - vCr3 ( t0 + Ts ), and Lr4 and Cr4 are resonant with the applied voltage nVo - vCr4 ( t0 + Ts ).
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Key waveforms of the proposed converter.
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Operation modes of the proposed converter during one switching cycle: (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6 (g) mode 7 (h) mode 8 (i) mode 9 (j) mode 10 (k) mode 11 (l) mode 12.
Mode 1 [t0≤t1]: At t0 , capacitances CS1 and CS3 are discharged to zero voltage in circuit module 1. Since iLr1 and iLr2 are positive and negative, respectively, the antiparallel diodes of S1 and S3 are conducting. Therefore, S1 and S3 can be turned on at this moment to achieve ZVS. In this mode, iLr1 < iLm1 and iLr2 > iLm2 . Thus, D2 and D3 are conducting and the magnetizing voltages vLm1 = - nVo and vLm2 = nVo . The magnetizing current iLm1 decreases with the slope of - nVo/Lm and iLm2 increases with the slope of nVo/Lm . In module 1, Lr1 and Cr1 are resonant with the applied voltage nVo - vCr1 ( t0 ), Lr2 and Cr2 are resonant with the applied voltage Vin /2 - nVo - vCr2 ( t0 ), and the flying capacitor voltage vCf1 = vCin1 . In module 2, S6 and S8 are turned on and D5 and D8 are in the on-state. Lr3 and Cr3 are resonant with the applied voltage Vin /2 - nVo - vCr3 ( t0 ), Lr4 and Cr4 are resonant with the applied voltage nVo - vCr4 ( t0 ), and the flying capacitor voltage vCf2 = vCin2 . The inductor currents iLr1 - iLr4 and capacitor voltages vCr1 - vCr4 in this mode are given as:
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where
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and
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. The inductor currents iLr1 and iLr4 decrease and iLr2 and iLr3 increase in this mode.
Mode 2 [t1≤t2]: At t1 , iLr3=iLm3 and iLr4=iLm4 . Thus, D5 D8 are in the off-state. Since S6 and S8 are still in the on-state, Cr3 , Lr3 and Lm3 are resonant with the applied voltage Vin /2 - vCr3 ( t1 ) and Cr4 , Lr4 and Lm4 are resonant with the applied voltage - vCr4 ( t1 ) in circuit module 2. The inductor currents iLr3 iLr4 and capacitor voltages vCr3 - vCr4 are expressed as:
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where
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and
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. The operations of circuit module 1 in this mode are the same as the operation in mode 1.
Mode 3 [t2≤t3]: At t2 , S6 and S8 are turned off. Since iLr3 ( t2 ) and iLr4 ( t2 ) are positive and negative, respectively, CS6 and CS8 are charged and CS5 and CS7 are discharged in this mode. Diodes D6 and D7 are conducting. Thus, the magnetizing voltages vLm3 = - nVo and vLm4 = nVo , and iLm3 decreases and iLm4 increases in this mode. If the energy stored in Lr3 and Lr4 is greater than the energy stored in CS5 CS8 , then CS5 and CS7 can be discharged to zero voltage.
Mode 4 [t3≤t4]: At t3 , CS5 and CS7 are discharged to zero voltage. Since iLr3 ( t3 )>0 and iLr4 ( t3 )<0, the anti-parallel diodes of S5 and S7 are conducting. Therefore, S5 and S7 can be turned on at this moment to achieve ZVS. Diodes D6 and D7 are conducting so that vLm3 = - nVo and vLm4 = nVo . In circuit module 2, Lr3 and Cr3 are resonant with the applied voltage nVo vCr3 ( t3 ) and Lr4 and Cr4 are resonant with the applied voltage Vin /2 - nVo vCr4 ( t3 ). The inductor currents iLr3 and iLr4 and the capacitor voltages vCr3 and vCr4 are expressed as:
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Mode 5 [t4≤t< t5]: At t5 , iLm1=iLr1 and iLm2=iLr2 . Thus, D1 D4 are all turned off. Components Cr1 , Lr1 and Lm1 are resonant with the applied voltage - vCr1 ( t4 ) and Cr2 , Lr2 and Lm2 are resonant with the applied voltage Vin /2 - vCr2 ( t4 ). The inductor currents iLr1 and iLr2 and capacitor voltages vCr1 and vCr2 are given as:
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Mode 6 [t5≤t< t6]: At t5 , S1 and S3 are turned off and D1 and D4 are conducting. The magnetizing voltages vLm1=nVo and vLm2= - nVo . Since iLr1 ( t5 )<0 and iLr2 ( t5 )>0, CS1 and CS3 are charged and CS2 and CS4 are discharged. CS2 and CS4 can be discharged to zero voltage if the energy stored in Lr1 and Lr2 is greater than the energy stored in CS1 - CS4 . At t6 , vCS2=vCS4=0 . The anti-parallel diodes of S2 and S4 are conducting.
Mode 7 [t6≤t< t7]: At t6 , CS2 and CS4 are discharged to zero voltage in circuit module 1. Since iLr1 ( t6 )<0 and iLr2 ( t6 )>0, the anti-parallel diodes of S2 and S4 are conducting. Thus, S2 and S4 can be turned on at this moment to achieve ZVS. In module 1, Lr1 and Cr1 are resonant with the applied voltage Vin /2 - nVo vCr1 ( t6 ), Lr2 and Cr2 are resonant with the applied voltage nVo vCr2 ( t6 ), and the flying capacitor voltage vCf1=vCin2 . The operation of circuit module 2 in this mode is the same as the operation in the previous mode.
Mode 8 [t7≤t< t8]: At t7 , iLr3=iLm3 and iLr4=iLm4 . Thus, D5 - D8 are all turned off. In circuit module 2, Cr3 , Lr3 and Lm3 are resonant with the applied voltage - vCr3 ( t7 ) and Cr4 , Lr4 and Lm4 are resonant with the applied voltage Vin /2 - vCr4 ( t7 ). The operations of circuit module 1 in this mode are the same as the operation in the previous mode.
Mode 9 [t8≤t< t9]: At t8 , S5 and S7 are turned off. Since iLr3 ( t8 )<0 and iLr4 ( t6 )>0, CS6 and CS8 are discharged and CS5 and CS7 are charged in this mode. Diodes D5 and D8 are conducting. CS6 and CS8 can be discharged to zero voltage if the energy stored in Lr3 and Lr4 is greater than the energy stored in CS5 - CS8 .
Mode 10 [t9≤t< t10]: At t9 , CS6 and CS8 are discharged to zero voltage. Since iLr3 ( t9 )<0 and iLr4 ( t9 )>0, the anti- parallel diodes of S6 and S8 are conducting. Thus, S6 and S8 can be turned on under ZVS. In circuit module 2, Lr3 and Cr3 are resonant with the applied voltage Vin /2 - nVo vCr3 ( t9 ) and Lr4 and Cr4 are resonant with the applied voltage nVo - vCr4 ( t9 ).
Mode 11 [t10≤t< t11]: At t10 , iLm1=iLr1 and iLm2=iLr2 . Thus, D1 - D4 are all turned off. In circuit module 1, Cr1 , Lr1 and Lm1 are resonant with the applied voltage Vin /2 - vCr1 ( t10 ) and Cr2 , Lr2 and Lm2 are resonant with the applied voltage - vCr2 ( t10 ). The operation of circuit module 2 is the same as the operation in the previous mode.
Mode 12 [t11≤t< ts+t0]: At t11 , S2 and S4 are turned off and D2 and D3 are conducting. The magnetizing voltages vLm1= - nVo and vLm2=nVo . Since iLr1 ( t11 )>0 and iLr2 ( t11 )<0, CS1 and CS3 are discharged and CS2 and CS4 are charged. CS1 and CS3 can be discharged to zero voltage if the energy stored in Lr1 and Lr2 is greater than the energy stored in CS1 CS4 . At Ts + t0 , vCS1=vCS3=0 . The anti- parallel diodes of S1 and S3 are conducting. Then, the operations of the proposed converter in a switching period are completed.
4. System Analysis
In this section, the system analysis of the proposed converter is presented. The duty cycle of each active switch is equal to 0.5. The pulse frequency modulation is adopted to regulate output voltage. The analysis of the proposed converter is based on the fundamental harmonic approach. The fundamental switching frequency is adopted to derive the system transfer function for each resonant converter. All harmonics of the switching frequency are neglected in the following discussion. The PWM signals of two circuit modules are interleaved by one-fourth of switching period. Each resonant circuit supplies one-fourth of load power to output load. Since the duty ratio of S1 - S8 is equal to 0.5, the AC terminal voltages vab , vcd , vef and vgh are the square waveforms between 0 and Vin /2. The capacitor voltage vCf1=vCin1 in modes 1-5 and vCf1=vCin2 in modes 7-11. The time periods in these two intervals are the same. Thus, the input capacitor voltages can be compensated and identical each other vCin1=vCf1=vCin2 . Based on the Fourier series analysis, the AC terminal voltage vab can be expressed as:
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where vab,dc , vab,f and vab,h are the dc component, fundamental frequency component and harmonic components of vab , respectively. The secondary side of resonant converter is driven by a quasi-sinusoidal current. If iLr1 > iLm1 , D1 is conducting and the magnetizing voltage vLm1=nVo . On the other hand, vLm1= - nVo if iLr1 < iLm1 and D2 is conducting. The transformer primary voltage vLm1 can be considered as a quasi-square waveform with ± nVo . The peak voltage of vLm1 at the fundamental frequency is expressed as
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Lm1,f = 4 nVo . The average output current of each center-tapped rectifier is equal to Io /4 and the peak value of diode currents is given as
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D1 =
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D2 = πIo /8 . The load resistance reflected to the primary side of T1 is given as Rac,T 1 =
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Lm1,f /(
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D1 / n ) = 32 n 2 Ro π 2 . Therefore, the resonant tank by Lr1 , Cr1 and Lm1 is excited by an effectively sinusoidal input voltage Vab,f and drives the effective AC resistive road Rac,T1 . Thus, the AC voltage gain of the resonant tank by Lr1 , Cr1 and Lm1 at fundament frequency can be obtained as:
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where
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,
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, k = Lr1 / Lm1 and fs is the switching frequency. At no-load condition ( Q =0) and fs = ∞ condition, the AC voltage gain of each resonant converter is expressed as | GAC ( f )| Q=0,fs=∞ ≈1/(1+ k ). If the minimum DC voltage gain of the resonant converter is greater than 0, | GAC ( f )| Q=0,fs=∞ , then the output voltage can be controlled from no load to full load condition.
5. Design Example and Experimental Results
A laboratory prototype was implemented with the following specifications: Vin =750 V - 800 V , Vo =24 V , Io = 60 A , and resonant frequency fr =120 k Hz. Transformers T1 - T4 were implemented with TDK EER-42 magnertic core with Ae =194mm 2 . The primary and secondary winding turns of T1 - T4 are 48 turns and 6 turns, respectively. The minimum and maximum voltage gains of resonant converter are given as:
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where Vf is the voltage drop on diodes D1 - D8 . At full load, the AC equivalent resistances Rac,T1 - Rac,T4 are given as:
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In this prototype, the inductance ratio k=Lr1/Lm1 is selected as 1/8 and the quality factor Q at full load is selected as 0.3. Thus, the AC voltage gain of the proposed converter at no load condition ( Q =0) is obtained as | GAC ( f )| Q=0,fs=∞ ≈0.889. In (23), the minimum DC voltage gain GDC,min of the proposed converter is 0.992 and greater than the AC voltage gain at no load condition. Thus, the output voltage at no load condition can be controlled. From the given series resonant frequency fr , the selected quality factor Q , the inductance ratio k and the AC equivalent resistance Rac,T1 , the series resonant inductances Lr1 - Lr4 , the magnetizing inductances Lm1 - Lm4 and the resonant capacitances Cr1 - Cr4 can be obtained as:
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Since two flying capacitors Cf1 and Cf2 are used to balance two input capacitor voltages VCin1 and VCin2 , the voltage stresses of S1 - S8 can be limited at Vin,max /2.
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The MOSFETs IRFP460 with 500V voltage stress and 20A current stress are adopted for active switches S1 - S8 . The voltage stress and average current of rectifier diodes D1 - D8 are obtained as:
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The fast recovery diodes 30CPQ150 with 150V voltage stress, 30A current stress and 0.8V voltage drop are used for diodes D1 - D8 . The input capacitances Cin1 and Cin2 are 680 n F/450V, the flying capacitances Cf1 and Cf2 are 680 n F/630V, and the output capacitance Co is 2820 µ F/ 100V (6 × 470 µF /100 V ).
A laboratory prototype with the circuit parameters derived in the previous section was implemented and tested to verify the effectiveness of the proposed converter. The measured gate voltages of S1 - S8 with input voltage Vin =800V and 25% load and full load are shown in Fig. 4 . The PWM signals of S5 - S8 are phase-shifted one-fourth of switching period with respectively to PWM signals of S1 - S4 , respectively. Fig. 5 gives the measured results of gate voltage, drain voltage and drain current of switch S1 at 5% load with different input voltage cases. Before switch S1 is turned on, the drain current is negative to discharge the drain-to-source capacitor. Thus, switch S1 can be turned on under ZVS when drain voltage is decreased to zero voltage. In the same manner, Fig. 6 shows the measured gate voltage, drain voltage and drain current of S1 at full load and different input voltage conditions. From measured results shown in Figs. 5 and 6 , S1 is turned on at ZVS from 5% load to full load. Similarly, S2 - S8 can also be turned on under ZVS from 5% load to full load. Fig. 7 illustrates the measured waveforms of two input capacitor voltages and two flying capacitor voltages at full load and Vin =800V. Two input capacitor voltages and two flying capacitor voltages are all balanced at 400V. Fig. 8 gives the measured waveforms of inductor currents iLr1 - iLr4 at full load. Four inductor currents iLr1 - iLr4 are balanced. Fig. 9 shows the measured waveforms of four resonant capacitor voltages vCr1 - vCr4 at full load condition. Fig. 10 gives the test results of the rectifier output currents io1 - io4 at full load condition. The rectifier output currents io1 - io4 are almost balanced. It is clear that output currents io3 and io4 are phase-shifted one-half of switching cycle with respectively to io1 and io2 . The ripple current of io2 is about 30A. However, the ripple current of the resultant output current io1 + io2 + io3 + io4 is about 10A. The measured output ripple voltage is 2.1V at full load. Fig. 11 shows the measured circuit efficiencies of the proposed converter at different input voltage and load current conditions.
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Measured waveforms of the gate voltages vS1,gs - vS8,gs with Vin=800V and (a) 25% load (b) full load.
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Experimental results of gate voltage, drain voltage and drain current of switch S1 at 5% load with (a) Vin=750V (b) Vin=800V.
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Experimental results of gate voltage, drain voltage and drain current of switch S1 at full load with (a) Vin=750V (b) Vin=800V.
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Measured waveforms of two input capacitor voltages and two flying capacitor voltages at full load and Vin=800V.
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Measured waveforms of inductor currents iLr1 - iLr4 at full load with (a) Vin=750V (b) Vin=800V.
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Measured waveforms of resonant capacitor voltages vCr1 - vCr4 at full load with (a) Vin=750V (b) Vin= 800V.
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Measured waveforms of the center-tapped rectifier output currents io1–io4 at full load with (a) Vin= 750V (b) Vin=800V.
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Measured efficiencies of the proposed converter at different input voltage and load current conditions.
6. Conclusion
A new parallel resonant converter is presented for high input voltage and high load current applications. The main functions of the proposed converter are low voltage stress of MOSFETs, ZVS turn-on for all MOSFETs, no reverse recovery loss on rectifier diodes, low current rating of transformer windings and less ripple current on output capacitor. Two resonant circuit modules with interleaved PWM scheme are adopted in the proposed converter to reduce the current stress of active and passive components and reduce the ripple current at output side. In each circuit module, one flying capacitor is added between two half- bridge legs to balance two input capacitor voltages. Two resonant converters are connected in series in order to reduce the voltage stress of each MOSFET at Vin /2. The pulse frequency modulation scheme is used to regulate output voltage. The switching frequency is controlled to be less than the series resonant frequency so that MOSFETs can be turned on at ZVS and rectifier diodes can be turned off at ZCS. The switching loss of MOSFETs is reduced and the reverse recovery loss of rectifier diodes is overcome. Finally, experiments based on a laboratory prototype are provided to verify the effectiveness of the proposed converter.
Acknowledgements
This project is supported by the National Science Council of Taiwan under Grant NSC102-2221-E-224-022-MY3
BIO
Bor-Ren Lin received the B.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and the M.S. and Ph.D. degrees in electrical engineering from the University of Missouri-Columbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings - Power Electronics and the Journal of Power Electronics. His main research interests include power-factor correction, multilevel converters, active power filters, and soft-switching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of the Research Excellence Awards in 2004, 2005, 2007 and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, the IEEE-Power Electronics and Drive Systems 2009 Conference, and the 2014 IEEE-International Conference Industrial Technology.
Chih-Chieh Chen received his M.S. in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC, in 2013. His research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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