This paper presents an interleaved resonant converter to reduce the voltage stress of power MOSFETs and achieve high circuit efficiency. Two halfbridge converters are connected in series at high voltage side to limit MOSFETs at
V_{in}
/2 voltage stress. Flying capacitor is used between two series halfbridge converters to balance two input capacitor voltages in each switching cycle. Variable switching frequency scheme is used to control the output voltage. The resonant circuit is operated at the inductive load. Thus, the input current of the resonant circuit is lagging to the fundamental input voltage. Power MOSFETs can be turn on under zero voltage switching. Two resonant circuits are connected in parallel to reduce the current stress of transformer windings and rectifier diodes at low voltage side. Interleaved pulsewidth modulation is adopted to decrease the output ripple current. Finally, experiments are presented to demonstrate the performance of the proposed converter.
1. Introduction
Power converters for medium or high power applications have been proposed and applied for many industry applications, such as fuelcell power system
[1]
, charge system
[2]
and ship power system
[3]
. For threephase AC/DC power conversion systems, the front stage is a power factor corrector (PFC) and the second stage a DC/DC converter. The DC bus voltage of a threephase PFC may be equal to 800V. In DC/DC converter, power MOSFETs with 900V voltage stress will result in high turnon resistance. Threelevel converters
[4

9]
with low voltage stress and high switching frequency have been presented in DC/DC converters for high voltage applications. Based on the neutralpoint clamped diodes or flying capacitor, the voltage stress of active switches is clamped at
V_{in}
/2. However, two input split capacitor voltages maybe unbalanced and will increase the voltage stress of active switches beyond
V_{in}
/2. In
[1]
and
[10]
, flying capacitor is adopted to the conventional threelevel neutral point clamped converter to automatically balance two input capacitor voltages. Threelevel zero voltage switching (ZVS) converters
[11

17]
have been presented to reduce the switching losses and increase the circuit efficiency. Pulsewidth modulation (PWM) schemes are adopted to generate the PWM signals for active switches and to regulate output voltage. However, the ZVS condition of active switches is related to the load condition and input voltage so that it is difficult to implement ZVS turnon for all switches over the entire load range. In order to extend the ZVS condition over the whole load range, resonant converters
[18

22]
have been proposed to achieve ZVS turnon over the wide load range and input voltage variation. However, the ripple current at the output capacitor in resonant converter is higher than the output ripple current in the conventional halfbridge or fullbridge PWM converter. In order to limit the output ripple voltage in the desired ripple voltage specification, several capacitors are connected in parallel to reduce the resultant series equivalent resistance. Therefore, the large capacitance is normally adopted at the output side in the resonant converters. In order to reduce the output capacitance and output ripple current in the resonant converters, parallel resonant converter with interleaved PWM scheme has been presented in
[23

25]
.
A new parallel resonant converter is presented for high input voltage and high load current applications. Two circuit modules connected in parallel in order to share load power and reduce the current stress of all passive and active power components. These two circuit modules are controlled with the phase shift of onefourth switching period in order to reduce the ripple current at the output capacitor. Thus, the size of output capacitor can be reduced. In each circuit module, two halfbridge converters are connected in series at the primary side to reduce the voltage stress of each active switch at
V_{in}
/2. Flying capacitor is connected between two halfbridge converters such that two input capacitor voltages can be automatically balanced in each switching cycle. Seriesparallel resonant tank is adopted in each halfbridge converter to achieve ZVS turnon for all switches over the entire load range. Finally, experiments were provided to verify the performance of the proposed converter.
2. Circuit Configuration
Fig. 1
gives the circuit configuration of the proposed converter for threephase switching mode power supplies. The threephase AC/DC converter with power factor correction is used in the front stage to reduce line current harmonics and provide a stable DC bus voltage for second stage DC/DC converter. The DC bus voltage is about 750V800V for threephase 480V utility input with power factor correction. The proposed parallel DC/DC converter with low voltage stress MOSFETs is adopted in the second stage for high load current applications. Two circuit modules are adopted in the proposed converter to share load current and reduce the current rating of active and passive components. The first circuit module includes
C_{in1}－C_{in2}, C_{f1}, S_{1}－S_{4}, C_{S1}－C_{S4}, C_{r1}－C_{r2}, L_{r1}－L_{r2}, T_{1}－ T_{2}, D_{1}－D_{4}
and
C_{o}
. In the same manner, the components of
C_{in1}－C_{in2}, C_{f2}, S_{5}－S_{8}, C_{S5}－C_{S8}, C_{r3}－C_{r4}, L_{r3}－L_{r4}, T_{3}－ T_{4}, D_{5}－D_{5}
and
C_{o}
are included in the circuit module 2.
C_{in1}
and
C_{in2}
are two input capacitances.
C_{r1}－C_{r4}
are the series resonant capacitances.
L_{r1}－L_{r4}
are the series resonant inductances.
L_{m1}－L_{m4}
are the magnetizing inductances of transformers
T_{1}－T_{4}
, respectively.
D_{1}－D_{8}
are the rectifier diodes and
T_{1}－T_{4}
are the isolated transformers.
C_{f1}
and
C_{f2}
are the flying capacitances. Each circuit module includes two resonant converters with half bridge converter leg. In circuit module 1, the first resonant converter includes the components of
S_{1}, S_{2}, C_{r1}, L_{r1}, T_{1}, D_{1}, D_{2}
and
C_{o}
. The second resonant converter includes
S_{3}, S_{4}, C_{r2}, L_{r2}, T_{2}, D_{3}, D_{4}
and
C_{o}
.
C_{o}
is the output capacitance. The primary sides of two resonant converters are connected in series in order to limit the voltage stress of each active switch at
V_{in}
/2. Active switches
S_{1}
and
S_{3}
have the same PWM waveforms. In the same manner,
S_{2}
and
S_{4}
have the same PWM signals. However, the PWM waveforms of
S_{1}
and
S_{2}
are complementary each other to avoid the short circuit in each halfbridge leg. In order to balance two input capacitor voltages
v_{Cin1}
and
v_{Cin2}
,
C_{f1}
is connected between the AC terminals
b
and
c
and
C_{f2}
is connected between the AC terminals
f
and
g
. If
S_{1}
and
S_{3}
are in the onstate and
S_{2}
and
S_{4}
are in the offstate, then
v_{Cf1}=v_{Cin1}
. On the other hand,
v_{Cf1}=v_{Cin2}
if
S_{2}
and
S_{4}
are in the onstate. Since each active switch has the equal turnon time, the flying capacitor voltage can be derived as
v_{Cf1}=v_{Cf2}= v_{Cin1}=v_{Cin2}=V_{in}
/2 and two capacitor voltages
v_{Cin1}
and
v_{Cin2}
are automatically balanced in each switching cycle. The frequency modulation scheme is used to regulate output voltage
V_{o}
. If the operated switching frequency is lower than the series resonant frequency, active switches
S_{1}－S_{8}
are turned on at ZVS and rectifier diodes
D_{1}－D_{8}
are turned off at ZCS. Thus, the switching losses of active switches are reduced and the reverse recovery problem of rectifier diodes is improved. In the proposed converter, each resonant converter supplies onefourth of load power to output load for the medium/high load current applications.
Circuit configuration of the proposed converter with two circuit modules.
3. Operation Principle
The circuit operations of the proposed converter are discussed with the following assumptions to simplify the system analysis. (1) Transformers
T_{1}－T_{4}
are identical with the same turns ratio
n=n_{p}/n_{s1}=np/n_{s2}
and same magnetizing inductances
L_{m1}=L_{m2}=L_{m3}=L_{m4}=L_{m}
, (2)
S_{1}  S_{8}
have the same output capacitance
C_{S}
, (3)
C_{in1}=C_{in2}
, (4)
C_{r1}=C_{r2} =C_{r3}=C_{r4}=C_{r}
, and (5)
L_{r1}=L_{r2}=L_{r3}=L_{r4}=L_{r}
. The main PWM waveforms of the proposed converter during one switching cycle are given in
Fig. 2
. Due to the on/off conditions of switches (2)
S_{1}  S_{8}
and rectifier diodes (2)
D_{1}  D_{8}
, the proposed converter has twelve operation modes in one switching period. The corresponding equivalent circuits of twelve operation modes are shown in
Fig. 3
. Before time
t_{0}
, (2)
S_{1}  S_{4}
are all turned off in circuit module 1.
i_{Lr1}
and
i_{Lr2}
are positive and negative, respectively. Therefore,
C_{S1}
and
C_{S3}
are discharged and
C_{S2}
and
C_{S4}
are charged. Since
i_{Lr1}
<
i_{Lm1}
and
i_{Lr2}
>
i_{Lm2}
, diodes
D_{2}
and
D_{3}
are in the onstate. In circuit module 2,
S_{6}
and
S_{8}
are in the onstate and diodes
D_{5}
and
D_{8}
are conducting.
L_{r3}
and
C_{r3}
are resonant with the applied voltage
V_{in}
/2 
nV_{o}

v_{Cr3}
(
t_{0}
+
T_{s}
), and
L_{r4}
and
C_{r4}
are resonant with the applied voltage
nV_{o}

v_{Cr4}
(
t_{0}
+
T_{s}
).
Key waveforms of the proposed converter.
Operation modes of the proposed converter during one switching cycle: (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6 (g) mode 7 (h) mode 8 (i) mode 9 (j) mode 10 (k) mode 11 (l) mode 12.
Mode 1 [t_{0}≤t1]:
At
t_{0}
, capacitances
C_{S1}
and
C_{S3}
are discharged to zero voltage in circuit module 1. Since
i_{Lr1}
and
i_{Lr2}
are positive and negative, respectively, the antiparallel diodes of
S_{1}
and
S_{3}
are conducting. Therefore,
S_{1}
and
S_{3}
can be turned on at this moment to achieve ZVS. In this mode,
i_{Lr1}
<
i_{Lm1}
and
i_{Lr2}
>
i_{Lm2}
. Thus,
D_{2}
and
D_{3}
are conducting and the magnetizing voltages
v_{Lm1}
= 
nV_{o}
and
v_{Lm2}
=
nV_{o}
. The magnetizing current
i_{Lm1}
decreases with the slope of 
nV_{o}/L_{m}
and
i_{Lm2}
increases with the slope of
nV_{o}/L_{m}
. In module 1,
L_{r1}
and
C_{r1}
are resonant with the applied voltage
nV_{o}

v_{Cr1}
(
t_{0}
),
L_{r2}
and
C_{r2}
are resonant with the applied voltage
V_{in}
/2 
nV_{o}

v_{Cr2}
(
t_{0}
), and the flying capacitor voltage
v_{Cf1}
=
v_{Cin1}
. In module 2,
S_{6}
and
S_{8}
are turned on and
D_{5}
and
D_{8}
are in the onstate.
L_{r3}
and
C_{r3}
are resonant with the applied voltage
V_{in}
/2 
nV_{o}

v_{Cr3}
(
t_{0}
),
L_{r4}
and
C_{r4}
are resonant with the applied voltage
nV_{o}

v_{Cr4}
(
t_{0}
), and the flying capacitor voltage
v_{Cf2}
=
v_{Cin2}
. The inductor currents
i_{Lr1}

i_{Lr4}
and capacitor voltages
v_{Cr1}

v_{Cr4}
in this mode are given as:
where
and
. The inductor currents
i_{Lr1}
and
i_{Lr4}
decrease and
i_{Lr2}
and
i_{Lr3}
increase in this mode.
Mode 2 [t_{1}≤t2]:
At
t_{1}
,
i_{Lr3}=i_{Lm3}
and
i_{Lr4}=i_{Lm4}
. Thus,
D_{5}
－
D_{8}
are in the offstate. Since
S_{6}
and
S_{8}
are still in the onstate,
C_{r3}
,
L_{r3}
and
L_{m3}
are resonant with the applied voltage
V_{in}
/2 －
v_{Cr3}
(
t_{1}
) and
C_{r4}
,
L_{r4}
and
L_{m4}
are resonant with the applied voltage －
v_{Cr4}
(
t_{1}
) in circuit module 2. The inductor currents
i_{Lr3}
－
i_{Lr4}
and capacitor voltages
v_{Cr3}

v_{Cr4}
are expressed as:
where
and
. The operations of circuit module 1 in this mode are the same as the operation in mode 1.
Mode 3 [t_{2}≤t3]:
At
t_{2}
,
S_{6}
and
S_{8}
are turned off. Since
i_{Lr3}
(
t_{2}
) and
i_{Lr4}
(
t_{2}
) are positive and negative, respectively,
C_{S6}
and
C_{S8}
are charged and
C_{S5}
and
C_{S7}
are discharged in this mode. Diodes
D_{6}
and
D_{7}
are conducting. Thus, the magnetizing voltages
v_{Lm3}
= －
nV_{o}
and
v_{Lm4}
=
nV_{o}
, and
i_{Lm3}
decreases and
i_{Lm4}
increases in this mode. If the energy stored in
L_{r3}
and
L_{r4}
is greater than the energy stored in
C_{S5}
－
C_{S8}
, then
C_{S5}
and
C_{S7}
can be discharged to zero voltage.
Mode 4 [t_{3}≤t4]:
At
t_{3}
,
C_{S5}
and
C_{S7}
are discharged to zero voltage. Since
i_{Lr3}
(
t_{3}
)>0 and
i_{Lr4}
(
t_{3}
)<0, the antiparallel diodes of
S_{5}
and
S_{7}
are conducting. Therefore,
S_{5}
and
S_{7}
can be turned on at this moment to achieve ZVS. Diodes
D_{6}
and
D_{7}
are conducting so that
v_{Lm3}
= －
nV_{o}
and
v_{Lm4}
=
nV_{o}
. In circuit module 2,
L_{r3}
and
C_{r3}
are resonant with the applied voltage
nV_{o}
－
v_{Cr3}
(
t_{3}
) and
L_{r4}
and
C_{r4}
are resonant with the applied voltage
V_{in}
/2 －
nV_{o}
－
v_{Cr4}
(
t_{3}
). The inductor currents
i_{Lr3}
and
i_{Lr4}
and the capacitor voltages
v_{Cr3}
and
v_{Cr4}
are expressed as:
Mode 5 [t_{4}≤t< t_{5}]:
At
t_{5}
,
i_{Lm1}=i_{Lr1}
and
i_{Lm2}=i_{Lr2}
. Thus,
D_{1}
－
D_{4}
are all turned off. Components
C_{r1}
,
L_{r1}
and
L_{m1}
are resonant with the applied voltage －
v_{Cr1}
(
t_{4}
) and
C_{r2}
,
L_{r2}
and
L_{m2}
are resonant with the applied voltage
V_{in}
/2 －
v_{Cr2}
(
t_{4}
). The inductor currents
i_{Lr1}
and
i_{Lr2}
and capacitor voltages
v_{Cr1}
and
v_{Cr2}
are given as:
Mode 6 [t_{5}≤t< t_{6}]:
At
t_{5}
,
S_{1}
and
S_{3}
are turned off and
D_{1}
and
D_{4}
are conducting. The magnetizing voltages
v_{Lm1}=nV_{o}
and
v_{Lm2}= － nV_{o}
. Since
i_{Lr1}
(
t_{5}
)<0 and
i_{Lr2}
(
t_{5}
)>0,
C_{S1}
and
C_{S3}
are charged and
C_{S2}
and
C_{S4}
are discharged.
C_{S2}
and
C_{S4}
can be discharged to zero voltage if the energy stored in
L_{r1}
and
L_{r2}
is greater than the energy stored in
C_{S1} － C_{S4}
. At
t_{6}
,
v_{CS2}=v_{CS4}=0
. The antiparallel diodes of
S_{2}
and
S_{4}
are conducting.
Mode 7 [t_{6}≤t< t_{7}]:
At
t_{6}
,
C_{S2}
and
C_{S4}
are discharged to zero voltage in circuit module 1. Since
i_{Lr1}
(
t_{6}
)<0 and
i_{Lr2}
(
t_{6}
)>0, the antiparallel diodes of
S_{2}
and
S_{4}
are conducting. Thus,
S_{2}
and
S_{4}
can be turned on at this moment to achieve ZVS. In module 1,
L_{r1}
and
C_{r1}
are resonant with the applied voltage
V_{in}
/2 －
nV_{o}
－
v_{Cr1}
(
t_{6}
),
L_{r2}
and
C_{r2}
are resonant with the applied voltage
nV_{o}
－
v_{Cr2}
(
t_{6}
), and the flying capacitor voltage
v_{Cf1}=v_{Cin2}
. The operation of circuit module 2 in this mode is the same as the operation in the previous mode.
Mode 8 [t_{7}≤t< t_{8}]:
At
t_{7}
,
i_{Lr3}=i_{Lm3}
and
i_{Lr4}=i_{Lm4}
. Thus,
D_{5} － D_{8}
are all turned off. In circuit module 2,
C_{r3}
,
L_{r3}
and
L_{m3}
are resonant with the applied voltage －
v_{Cr3}
(
t_{7}
) and
C_{r4}
,
L_{r4}
and
L_{m4}
are resonant with the applied voltage
V_{in}
/2 －
v_{Cr4}
(
t_{7}
). The operations of circuit module 1 in this mode are the same as the operation in the previous mode.
Mode 9 [t_{8}≤t< t_{9}]:
At
t_{8}
,
S_{5}
and
S_{7}
are turned off. Since
i_{Lr3}
(
t_{8}
)<0 and
i_{Lr4}
(
t_{6}
)>0,
C_{S6}
and
C_{S8}
are discharged and
C_{S5}
and
C_{S7}
are charged in this mode. Diodes
D_{5}
and
D_{8}
are conducting.
C_{S6}
and
C_{S8}
can be discharged to zero voltage if the energy stored in
L_{r3}
and
L_{r4}
is greater than the energy stored in
C_{S5} － C_{S8}
.
Mode 10 [t_{9}≤t< t_{10}]:
At
t_{9}
,
C_{S6}
and
C_{S8}
are discharged to zero voltage. Since
i_{Lr3}
(
t_{9}
)<0 and
i_{Lr4}
(
t_{9}
)>0, the anti parallel diodes of
S_{6}
and
S_{8}
are conducting. Thus,
S_{6}
and
S_{8}
can be turned on under ZVS. In circuit module 2,
L_{r3}
and
C_{r3}
are resonant with the applied voltage
V_{in}
/2 －
nV_{o}
－
v_{Cr3}
(
t_{9}
) and
L_{r4}
and
C_{r4}
are resonant with the applied voltage
nV_{o} － v_{Cr4}
(
t_{9}
).
Mode 11 [t_{10}≤t< t_{11}]:
At
t_{10}
,
i_{Lm1}=i_{Lr1}
and
i_{Lm2}=i_{Lr2}
. Thus,
D_{1} － D_{4}
are all turned off. In circuit module 1,
C_{r1}
,
L_{r1}
and
L_{m1}
are resonant with the applied voltage
V_{in}
/2 －
v_{Cr1}
(
t_{10}
) and
C_{r2}
,
L_{r2}
and
L_{m2}
are resonant with the applied voltage －
v_{Cr2}
(
t_{10}
). The operation of circuit module 2 is the same as the operation in the previous mode.
Mode 12 [t_{11}≤t< t_{s}+t_{0}]:
At
t_{11}
,
S_{2}
and
S_{4}
are turned off and
D_{2}
and
D_{3}
are conducting. The magnetizing voltages
v_{Lm1}= － nV_{o}
and
v_{Lm2}=nV_{o}
. Since
i_{Lr1}
(
t_{11}
)>0 and
i_{Lr2}
(
t_{11}
)<0,
C_{S1}
and
C_{S3}
are discharged and
C_{S2}
and
C_{S4}
are charged.
C_{S1}
and
C_{S3}
can be discharged to zero voltage if the energy stored in
L_{r1}
and
L_{r2}
is greater than the energy stored in
C_{S1}
－
C_{S4}
. At
T_{s}
+
t_{0}
,
v_{CS1}=v_{CS3}=0
. The anti parallel diodes of
S_{1}
and
S_{3}
are conducting. Then, the operations of the proposed converter in a switching period are completed.
4. System Analysis
In this section, the system analysis of the proposed converter is presented. The duty cycle of each active switch is equal to 0.5. The pulse frequency modulation is adopted to regulate output voltage. The analysis of the proposed converter is based on the fundamental harmonic approach. The fundamental switching frequency is adopted to derive the system transfer function for each resonant converter. All harmonics of the switching frequency are neglected in the following discussion. The PWM signals of two circuit modules are interleaved by onefourth of switching period. Each resonant circuit supplies onefourth of load power to output load. Since the duty ratio of
S_{1} － S_{8}
is equal to 0.5, the AC terminal voltages
v_{ab}
,
v_{cd}
,
v_{ef}
and
v_{gh}
are the square waveforms between 0 and
V_{in}
/2. The capacitor voltage
v_{Cf1}=v_{Cin1}
in modes 15 and
v_{Cf1}=v_{Cin2}
in modes 711. The time periods in these two intervals are the same. Thus, the input capacitor voltages can be compensated and identical each other
v_{Cin1}=v_{Cf1}=v_{Cin2}
. Based on the Fourier series analysis, the AC terminal voltage
v_{ab}
can be expressed as:
where
v_{ab,dc}
,
v_{ab,f}
and
v_{ab,h}
are the dc component, fundamental frequency component and harmonic components of
v_{ab}
, respectively. The secondary side of resonant converter is driven by a quasisinusoidal current. If
i_{Lr1}
>
i_{Lm1}
,
D_{1}
is conducting and the magnetizing voltage
v_{Lm1}=nV_{o}
. On the other hand,
v_{Lm1}= － nV_{o}
if
i_{Lr1}
<
i_{Lm1}
and
D_{2}
is conducting. The transformer primary voltage
v_{Lm1}
can be considered as a quasisquare waveform with ±
nV_{o}
. The peak voltage of
v_{Lm1}
at the fundamental frequency is expressed as
_{Lm1,f}
= 4
nV_{o}/π
. The average output current of each centertapped rectifier is equal to
I_{o}
/4 and the peak value of diode currents is given as
_{D1}
=
_{D2}
=
πI_{o}
/8 . The load resistance reflected to the primary side of
T_{1}
is given as
R_{ac,T}
_{1}
=
_{Lm1,f}
/(
_{D1}
/
n
) = 32
n
^{2}
R_{o}
π
^{2}
. Therefore, the resonant tank by
L_{r1}
,
C_{r1}
and
L_{m1}
is excited by an effectively sinusoidal input voltage
V_{ab,f}
and drives the effective AC resistive road
R_{ac,T1}
. Thus, the AC voltage gain of the resonant tank by
L_{r1}
,
C_{r1}
and
L_{m1}
at fundament frequency can be obtained as:
where
,
,
k
=
L_{r1}
/
L_{m1}
and
f_{s}
is the switching frequency. At noload condition (
Q
=0) and
f_{s}
= ∞ condition, the AC voltage gain of each resonant converter is expressed as 
G_{AC}
(
f
)
_{Q=0,fs=∞}
≈1/(1+
k
). If the minimum DC voltage gain of the resonant converter is greater than 0, 
G_{AC}
(
f
)
_{Q=0,fs=∞}
, then the output voltage can be controlled from no load to full load condition.
5. Design Example and Experimental Results
A laboratory prototype was implemented with the following specifications:
V_{in}
=750
V
－ 800
V
,
V_{o}
=24
V
,
I_{o}
= 60
A
, and resonant frequency
f_{r}
=120
k
Hz. Transformers
T_{1} － T_{4}
were implemented with TDK EER42 magnertic core with
A_{e}
=194mm
^{2}
. The primary and secondary winding turns of
T_{1} － T_{4}
are 48 turns and 6 turns, respectively. The minimum and maximum voltage gains of resonant converter are given as:
where
V_{f}
is the voltage drop on diodes
D_{1} － D_{8}
. At full load, the AC equivalent resistances
R_{ac,T1} － R_{ac,T4}
are given as:
In this prototype, the inductance ratio
k=L_{r1}/L_{m1}
is selected as 1/8 and the quality factor
Q
at full load is selected as 0.3. Thus, the AC voltage gain of the proposed converter at no load condition (
Q
=0) is obtained as 
G_{AC}
(
f
)
_{Q=0,fs=∞}
≈0.889. In (23), the minimum DC voltage gain
G_{DC,min}
of the proposed converter is 0.992 and greater than the AC voltage gain at no load condition. Thus, the output voltage at no load condition can be controlled. From the given series resonant frequency
f_{r}
, the selected quality factor
Q
, the inductance ratio
k
and the AC equivalent resistance
R_{ac,T1}
, the series resonant inductances
L_{r1} － Lr_{4}
, the magnetizing inductances
L_{m1} － L_{m4}
and the resonant capacitances
C_{r1} － C_{r4}
can be obtained as:
Since two flying capacitors
C_{f1}
and
C_{f2}
are used to balance two input capacitor voltages
V_{Cin1}
and
V_{Cin2}
, the voltage stresses of
S_{1} － S_{8}
can be limited at
V_{in,max}
/2.
The MOSFETs IRFP460 with 500V voltage stress and 20A current stress are adopted for active switches
S_{1} － S_{8}
. The voltage stress and average current of rectifier diodes
D_{1} － D_{8}
are obtained as:
The fast recovery diodes 30CPQ150 with 150V voltage stress, 30A current stress and 0.8V voltage drop are used for diodes
D_{1} － D_{8}
. The input capacitances
C_{in1}
and
C_{in2}
are 680
n
F/450V, the flying capacitances
C_{f1}
and
C_{f2}
are 680
n
F/630V, and the output capacitance
C_{o}
is 2820
µ
F/ 100V (6 × 470
µF
/100
V
).
A laboratory prototype with the circuit parameters derived in the previous section was implemented and tested to verify the effectiveness of the proposed converter. The measured gate voltages of
S_{1} － S8
with input voltage
V_{in}
=800V and 25% load and full load are shown in
Fig. 4
. The PWM signals of
S_{5} － S_{8}
are phaseshifted onefourth of switching period with respectively to PWM signals of
S_{1} － S_{4}
, respectively.
Fig. 5
gives the measured results of gate voltage, drain voltage and drain current of switch
S_{1}
at 5% load with different input voltage cases. Before switch
S_{1}
is turned on, the drain current is negative to discharge the draintosource capacitor. Thus, switch
S_{1}
can be turned on under ZVS when drain voltage is decreased to zero voltage. In the same manner,
Fig. 6
shows the measured gate voltage, drain voltage and drain current of S1 at full load and different input voltage conditions. From measured results shown in
Figs. 5
and
6
,
S_{1}
is turned on at ZVS from 5% load to full load. Similarly,
S_{2} － S_{8}
can also be turned on under ZVS from 5% load to full load.
Fig. 7
illustrates the measured waveforms of two input capacitor voltages and two flying capacitor voltages at full load and
V_{in}
=800V. Two input capacitor voltages and two flying capacitor voltages are all balanced at 400V.
Fig. 8
gives the measured waveforms of inductor currents
i_{Lr1} － i_{Lr4}
at full load. Four inductor currents
i_{Lr1} － i_{Lr4}
are balanced.
Fig. 9
shows the measured waveforms of four resonant capacitor voltages
v_{Cr1} － v_{Cr4}
at full load condition.
Fig. 10
gives the test results of the rectifier output currents
i_{o1} － i_{o4}
at full load condition. The rectifier output currents
i_{o1} － i_{o4}
are almost balanced. It is clear that output currents
i_{o3}
and
i_{o4}
are phaseshifted onehalf of switching cycle with respectively to
i_{o1}
and
i_{o2}
. The ripple current of
i_{o2}
is about 30A. However, the ripple current of the resultant output current
i_{o1}
+
i_{o2}
+
i_{o3}
+
i_{o4}
is about 10A. The measured output ripple voltage is 2.1V at full load.
Fig. 11
shows the measured circuit efficiencies of the proposed converter at different input voltage and load current conditions.
Measured waveforms of the gate voltages v_{S1,gs} － v_{S8,gs} with V_{in}=800V and (a) 25% load (b) full load.
Experimental results of gate voltage, drain voltage and drain current of switch S_{1} at 5% load with (a) V_{in}=750V (b) V_{in}=800V.
Experimental results of gate voltage, drain voltage and drain current of switch S_{1} at full load with (a) V_{in}=750V (b) V_{in}=800V.
Measured waveforms of two input capacitor voltages and two flying capacitor voltages at full load and V_{in}=800V.
Measured waveforms of inductor currents i_{Lr1} － i_{Lr4} at full load with (a) V_{in}=750V (b) V_{in}=800V.
Measured waveforms of resonant capacitor voltages v_{Cr1} － v_{Cr4} at full load with (a) V_{in}=750V (b) V_{in}= 800V.
Measured waveforms of the centertapped rectifier output currents i_{o1}–i_{o4} at full load with (a) V_{in}= 750V (b) V_{in}=800V.
Measured efficiencies of the proposed converter at different input voltage and load current conditions.
6. Conclusion
A new parallel resonant converter is presented for high input voltage and high load current applications. The main functions of the proposed converter are low voltage stress of MOSFETs, ZVS turnon for all MOSFETs, no reverse recovery loss on rectifier diodes, low current rating of transformer windings and less ripple current on output capacitor. Two resonant circuit modules with interleaved PWM scheme are adopted in the proposed converter to reduce the current stress of active and passive components and reduce the ripple current at output side. In each circuit module, one flying capacitor is added between two half bridge legs to balance two input capacitor voltages. Two resonant converters are connected in series in order to reduce the voltage stress of each MOSFET at
V_{in}
/2. The pulse frequency modulation scheme is used to regulate output voltage. The switching frequency is controlled to be less than the series resonant frequency so that MOSFETs can be turned on at ZVS and rectifier diodes can be turned off at ZCS. The switching loss of MOSFETs is reduced and the reverse recovery loss of rectifier diodes is overcome. Finally, experiments based on a laboratory prototype are provided to verify the effectiveness of the proposed converter.
Acknowledgements
This project is supported by the National Science Council of Taiwan under Grant NSC1022221E224022MY3
BIO
BorRen Lin received the B.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and the M.S. and Ph.D. degrees in electrical engineering from the University of MissouriColumbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings  Power Electronics and the Journal of Power Electronics. His main research interests include powerfactor correction, multilevel converters, active power filters, and softswitching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of the Research Excellence Awards in 2004, 2005, 2007 and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, the IEEEPower Electronics and Drive Systems 2009 Conference, and the 2014 IEEEInternational Conference Industrial Technology.
ChihChieh Chen received his M.S. in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC, in 2013. His research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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