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A Novel Single Phase Soft Switched PFC Converter
A Novel Single Phase Soft Switched PFC Converter
Journal of Electrical Engineering and Technology. 2014. Sep, 9(5): 1592-1601
Copyright © 2014, The Korean Institute of Electrical Engineers
  • Received : October 06, 2013
  • Accepted : April 21, 2014
  • Published : September 01, 2014
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About the Authors
Nihan ALTINTAŞ
Corresponding Author: Dept. of Electrical Engineering, Yildiz Technical University, Turkey (naltin@yildiz.edu.tr)

Abstract
In this study, a novel single phase soft switched power factor correction (PFC) converter is developed with active snubber cell. The active snubber cell provides boost switch both to turn on with zero voltage transition (ZVT) and to turn off with zero current transition (ZCT). As the switching losses in the proposed converter are too low, L and C size can be reduced by increasing the operating frequency. Also, all the semiconductor devices operate with soft switching. There is no additional voltage stress in the boost switch and diode. The proposed converter has a simple structure, low cost and ease of control as well. It has a simple control loop to achieve near unity power factor with the aid of the UC3854. In this study, detailed steady state analysis of the proposed converter is presented and this theoretical analysis is verified by a prototype of 100 kHz and 500 W converter. The measured power factor and efficiency are 0.99 and 97.9% at full load.
Keywords
1. Introduction
AC-DC converters have been used in the power electronic systems and introduce harmonic currents from the ac mains. These harmonic currents cause some problems such as voltage distortion, poor power factor at input ac mains and noise. Single-phase power factor correction (PFC) topologies have been used in the power electronic systems to meet harmonic current limits defined by IEC 61000-3-2 [1 - 3] .
The boost converter is the most popular topology for PFC applications because of their high power density, low-distorted input current, fast transient response and ease of control [4] . The boost PFC converter is operated in continuous conduction mode (CCM) at medium power level application [5] .
A higher power density and faster transient response can be achieved by increasing switching frequency. However, as the switching frequency rises, switching losses and electromagnetic interference (EMI) noises increase. This aim can be realized by using the soft switching (SS) techniques implemented with snubber cells instead of hard switching (HS) techniques [6 , 7] . SS techniques are based on Zero Voltage Switching (ZVS), Zero Current Switching (ZCS), Zero Voltage Transition (ZVT), and Zero Current Transition (ZCT) methods [8 - 20] .
Recently, a lot of papers have been proposed to realize soft switching for the boost PFC converter. In the basic ZVT converter [8] , the main switch turns on with ZVT perfectly with the help of a snubber cell. In the basic ZCT converter [9] , the main switch turns off under ZCS and ZVS with the help of a snubber cell. A lot of papers are developed to solve the problems in basic ZVT and ZCT converters [10 - 17] . In these methods, there are still some problems along with significant switching losses. In order to solve these problems, ZVT and ZCT converters which are formed by combining the ZVT and ZCT methods, are suggested in [18 - 20] . The main switch is turned on and off with exactly at zero voltage and zero current. Also, the auxiliary switch operates under by soft switching.
In this study, a novel single phase soft switched power factor correction (PFC) converter is developed with active snubber cell. The active snubber cell provides boost switch both to turn on with zero voltage transition (ZVT) and to turn off with zero current transition (ZCT). It has a simple control loop to achieve near unity power factor with the aid of the UC3854. The detailed steady state analysis of the proposed converter is presented and this theoretical analysis is verified by a prototype of 100 kHz and 500 W converter.
2. Operation Modes and Analysis
- 2.1 Definitions and assumptions
The proposed new single phase soft switched PFC converter circuit is shown in Fig. 1 . In this circuit, v ac is line voltage, i ac is line current, D r1 -D r4 are rectifier diodes, V i is input voltage source, V o is output voltage, L F is boost inductor, C F is output filter capacitor, S 1 is boost switch and D F is boost diode. The boost switch consists of a boost transistor T 1 and its body diode D 1 . In the soft switching circuit, S 2 is auxiliary switch, L sa and L sb are snubber inductors, C s is snubber capacitor, D 3 and D 4 are auxiliary diodes. The snubber capacitor C p is assumed to be the sum of the parasitic capacitor of S 1 and D F .
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Circuit scheme of the proposed converter
In the steady-state analysis of the circuit, V o and I i are assumed constant for one switching cycle. Besides semiconductor devices and resonant circuits are assumed ideal. Also, the reverse recovery times of all diodes are not taken into account.
- 2.2 Operation stages
One switching period of the proposed new converter consist of 12 stages. The equivalent circuit diagrams of the operation stages are given in Fig. 2 . The key waveforms concerning these stages are shown in Fig. 3 . The detailed analysis of every stage of the proposed converter is presented below.
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Equivalent circuit schemes of the operation stages in the proposed converter
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The key waveforms of the proposed converter
Stage 1 [ t0 < t < t1 : Fig. 2(a) ]: At t = t0 , iT1 = 0 , iT2 = 0 , iDF = Ii , iLsa = 0 , iLsb = 0 and vCs = 0 are valid. At the beginning of this stage, D F is in the on state and conducts the input current. S 1 and S 2 are in the off state. At t=t0 , when the control signal is applied to the gate of S 2 , a resonance starts between L sa , L sb and C s . Due to the resonance, C s capacitor charges, S 2 current rises and D F current falls simultaneously. For this stage, the following state equations can be written generally as,
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At t = t 1 , i S2 reaches I i and i DF falls to zero and this stage is finished. Due to the series connected snubber inductance, S 2 and D 3 are turned on with ZCS. The boost diode D F is turned off with nearly ZCS and ZVS. At the end of this mode,
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can be written.
Stage 2 [ t12: Fig. 2(b) ]: At t=t1, iT1=0, iT2=Ii, iDF=0, iLsa=ILsa1, iLsb=Ii, vCs=VCs1 and vCp=Vo are valid. S 1 and D F are in the off state. S 2 is in the on state and conducts input current I i .
At t = t 1 , a resonance starts between C p , L sa , L sb and C s . i Lsa and i Lsb current rises and the capacitor voltage of v Cp decreases by the resonance. For this stage, the following state equations can be written generally as,
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At t = t 2 , v Cp becomes 0 and the energy which is stored in the C p , is transferred from capacitor to resonant circuit. At the same time, D 1 turns on with ZVS and this stage ends. At the end of this mode,
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can be written.
Stage 3 [ t25: Fig. 2(c) ]: At the beginning of this stage, iT1=0, iT2=ILsb2, iDF=0, iLsa=ILsa2, iLsb=ILsb2, vCs=VCs2 and vCp=0 are existent. In this mode, the resonant which is between L sa , L sb and C s is still continued. For this stage,
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are written. In this stage three different operation modes are occurred. At t=t 2 , D 1 is turned on and conducts the excess of i Lsb current from I i . The interval of this mode is time for the boost switch S1 to turn on with ZVT. It should be noted that the gate signal of S 1 must be applied during this time. As a result, S 1 will be turn on perfectly under ZVS and ZCS provided by ZVT. At t=t 3 , i Lsb drops to input current level and D 1 is turned off under ZCS. Just before D 1 is turned off, S 1 is turned on with ZVT. The boost switch current starts to rise and when it reaches to I i , the current of S 2 becomes 0 at t=t 4 . Just after t=t 4 , D 2 is turned on. In the on state of D 2 , the gate signal of S 2 is removed, so that S 2 is perfectly turned off under ZCT. This stage ends when i D2 is equal to zero at the instant t 5 . At the end of this stage,
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can be written.
Stage 4 [ t56: Fig. 2(d) ]: This stage begins when D 2 turns off. At t=t5, iT1=Ii, iT2=0, iDF=0, iLsa=ILsa5, iLsb=0, vCs=VCs5 and vCp=0 . While S 1 conducts input current, The current through the main transistor is equal to input current. At the same time, a resonance occurs through L sa -C s -D 3 . For this resonance,
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are achieved. The energy in L sa is transferred to C s with this resonance. At t=t 6 , Lsa current is equal to zero and the current direction change is blocked by D 3 . v Cs reaches its maximum level and this stage is finished. At the end of this mode,
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can be written. Where
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Stage 5 [ t67: Fig. 2(e) ]: In this stage, the boost switch S 1 conducts I i and the auxiliary circuit is not active. This stage is the on state of the standard PWM boost converter. For this mode,
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can be written.
Stage 6 [ t79: Fig. 2(f) ]: At the beginning of this stage, iT1=Ii, iT2=0, iDF=0, iLsa=0, iLsb=0, vCs=VCsmax and vCp=0 are valid. At t=t 7 , when the gate signal is applied to the S 2 , a resonance starts between L sb and C s by the way of C s -L sb -S 2 -S 1 . For this stage, the following state equations can be written generally as,
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S 2 is turned on with ZCS through L sb . The L sb current rises and the boost switch current falls due to the resonance. At t=t 8 , when i S2 reaches input current level, i S1 becomes zero. Just after this time, D 1 is turned on with ZCS and the current trough the boost switch is negative. If the gate signal of S 1 is removed, S 1 will turn off perfectly under ZVS and ZCS provided by ZCT. A new resonance occurs through the way of C s -L sb -T 2 -D 1 . D 1 conducts the excess of i Lsb from I i . At t=t 9 , v Cs voltage falls to zero and i Lsb reaches its maximum value and this stage finishes. At the end of this mode,
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is valid. Here,
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Stage 7 [ t910: Fig. 2(g) ]: At the beginning of this stage, iT1=0, iT2=ILsbmax, iDF=0, iLsa=0, iLsb=ILsbmax, vCs=0 and vCp=0 are valid. At t=t 9 , while v Cs starts to be positive, the diode D 3 is turned on with ZCS. A new resonance is occurred between L sb , L sa and C s . For this state,
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can be written. D 1 current becomes zero when i Lsb falls again to I i . At t=t 10 , D 1 is turned off under ZCS and this stage ends. At the end of this mode,
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are valid. t 8 -t 10 is the on state time interval of D 1 and it is also equal to the ZCT time of the converter. The control signal of S 1 must be removed during this time and so the boost switch is turned off perfectly under ZCS and ZVS provided by ZCT.
Stage 8 [ t1011: Fig. 2(h) ]: At t=t10, iT1=0, iT2=Ii, iDF=0, iLsa=ILsa10, iLsb=Ii, vCs=VCs10 and vCp=0 are valid. Just after this time, a resonance occurs between C p , L sa , L sb and C s with the input current. The state equations are formed for this mode as follows.
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i Lsb continues to decrease due to the resonance and becomes zero at t=t 11 . The auxiliary switch current becomes negative. The control signal of S 2 must be removed during this interval, in which D 2 is in the on state. The auxiliary switch S 2 is turned off perfectly under ZCS and ZVS provided by ZCT. i S2 becomes zero at t=t 12 and this stage ends. At the end of this mode,
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are valid.
Stage 9 [ t1213: Fig. 2(i) ]: At the beginning of this stage, iT1=0, iT2=0, iDF=0, iLsa=ILsa12, iLsb=0, vCs=VCs12 and vCp=VCp12 are valid. There are two different closed circuits for this interval. For the first one, C p is charged linearly with I i and the second one, a resonance occurs between L sa and C s via the path L sa -C s -D 3 . For this mode,
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can be written. The sum of the v Cp and v Cs voltages becomes equal to output voltage at t=t 13 . D 4 is turned on with ZVS and this mode is finished. At the end of this mode,
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are valid.
Stage 10 [ t1314: Fig. 2(j) ]: At t=t13, iT1=0, iT2=0, iDF=0, iLsa= ILsa13, iLsb=0, vCs=VCs13 and vCp=Vo-VCs13 are existent. In this stage, a resonance between L sa , C s and C p starts under the input current. At t=t 14 , i Lsa current becomes zero. This mode is finished. The energy stored in the L sa is transferred to the capacitors and to the load. For this mode, the following equations are derived.
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Stage 11 [ t1415: Fig. 2(k) ]: At t=t14, iT1=0, iT2=0, iDF=0, iLsa= 0, iLsb=0, vCs=VCs14 and vCp=Vo-VCs14 are valid. C p is charged linearly with I i and C s is discharged. For this mode,
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can be written. v Cp reaches V o and v Cs falls to 0 simultaneously at t 15 . D F is turned on with ZVS and D,,,, is turned off with ZVS, and this mode finishes.
Stage 12 [ t1516: Fig. 2(l) ]: At t=t 15 , i T1 =0, i T2 =0, i DF =I i , i Lsa = 0, i Lsb =0, v Cs =0 and v Cp =V o are valid. In this stage, the boost diode continues conducting the input current and the auxiliary circuit is not active. This stage is the off state of the PWM boost converter. For this mode,
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can be written.
At t=t 16 =t 0 , one switching period is completed by applying the control signal to boost switch again, and new switching period is started.
3. Converter Features
- 3.1 Main futures
The proposed converter is endowed with the active snubber cell which overcomes most of the drawbacks of the conventional PFC converter. Also, it has achieved nearly unity power factor at overall load range.
  • 1) The boost switch is turned on with ZVT and turn off with ZCT, perfectly. The auxiliary switch is turned on with ZCS and turned off with ZCT
  • 2) The boost switch is not subjected to any additional voltage stress. The current stress of main switch is at acceptable levels but this is the disadvantage of this converter.
  • 3) The main diode is not subjected to any additional voltage and current stresses.
  • 4) The soft switching operation of the new converter is maintained for the overall line and load ranges.
  • 5) The converter can operate at considerably high frequencies and acts as a normal PWM converter. Also the circulating energy is quite small.
  • 6) The sum of transient intervals is a very little part of the switching cycle.
  • 7) Nearly unity power factor is achieved at full load condition and even light load condition.
- 3.2 Comparison of the proposed PFC converter and the PFC converter in[20]
In the proposed PFC converter, all semiconductor devices in the circuit are switched under soft switching. The boost switch is perfectly turned on and off with ZVT and ZCT, respectively. The auxiliary switch is turned on with ZCS and turned off with ZCT. But the PFC converter in [20] , the boost switch and auxiliary switch are turned off with near ZVS. So that, the turn off switching losses are occurred in this case. As a result of this, the switching frequency can be selected higher than [20] and the efficiency of the proposed converter will be higher than [20] . The soft switching capabilities of the proposed converter and the PFC converter of [20] are summarized in the Table 1 .
Switching states
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Switching states
4. Design Procedure
A procedure for the design of the proposed converter is presented in this section. The design of the main power circuit can be found in any standard power electronics textbook so that only the design of the snubber circuit components is presented. In this study, the average control technique is used in the control circuit.
  • 1) Cpis assumed to be the sum of parasitic capacitor of the main switch and the other parasitic capacitors incorporating it.
  • 2) The tZCTinterval must be chosen at least as fall time of the boost switch (tf1).
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3) In order to turn off the auxiliary switch with ZCT, the value of Lsa must be at least 2 times of Lsb value.
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4) Lsb is selected to allow a current rise rate to be the maximum input current at most, within the auxiliary switch turn-on process and its current rise time.
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5) The value of Cs depends on the values of Cp, Lsa and Lsb. Also, the resonance current maximum value should be higher than the input current, the tZCT operation should be provided and the total resonance interval should not affect the PWM operation.
In order to give an idea about the selection of the components of the snubber cell, a design example is given below. Some values of the components used in experimental circuit are given in Table 2 . According to design procedure and Table 2 , snubber circuit components are determined. The capacitor C p is assumed to be the sum of the parasitic capacitor of main switch and the other parasitic capacitors incorporating it. In the experimental circuit, C p is approximately 1 nF. The L sb value is selected as 2 µH from (54). L sa is selected as 4 µH from (53). If the maximum value of the main switch current is assumed to be twice the input current, by using the characteristic curves shown in Fig. 4 , the value of C s is selected as 4.7 nF.
Some values of the components used in experimental circuit witching states
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Some values of the components used in experimental circuit witching states
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Variation of maximum current through the main switch with snubber inductance Lsa for different snubber capacitor Cs
5. Experimental Results
The experimental circuit scheme of the converter is shown in Fig. 5 .
The converter is to be designed according to the following specifications: output voltage V o = 400 V, input voltage V ac =85-265 V, output power P o = 500 W, switching frequency f s = 100 kHz. L F boost inductance is designed to provide PFC and to operate in CCM. C F output capacitor is selected to have constant voltage. The control circuit associated with the UC3854 integrated circuit is designed as suggested in [21] . Due to the well-known, the control circuit design procedure is not given here. UC3854A integrated circuit generates the control signal of the boost switch. The auxiliary switch control signal is produced by using the control signal of the boost switch with the help of the analog card.
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Experimental circuit scheme of the proposed converter
In the Fig. 6(a) , the control signals of the main and auxiliary switches are shown. The auxiliary switch operates twice in a one switching period of the main switch.
The voltage and current waveforms of the boost switch S 1 are shown in the Fig. 6(b) . It can be seen that turn on and turn off process of the S 1 is realized with soft switching. There is no overlap between current and voltage waveforms of S 1 . From the S 1 current waveform, the body diode is turned on firstly and then the control signals of the S1 is removed during the turn on and turn off process of the switch. So, ZVT turn on and ZCT turn off processes is perfectly realized. Also, there is no any additional voltage stress on the main switch and it has got an acceptable current stress.
The boost diode is turned on under ZVS and turned off under ZCS and ZVS. It can be seen in Fig. 6(c) , there is no any additional voltage and current stresses on the boost diode.
The auxiliary switch voltage and current waveforms are shown in Fig. 6(d) . The auxiliary switch is operated in both ZVT and ZCT processes of the boost switch. It means that the operating frequency of the auxiliary switch is two times of the boost switch operating frequency. Also, the auxiliary switch conduction time is very short. The auxiliary switch is turned on under near ZCS due to the serial connected inductance and is turned off with ZCT perfectly due to the removal of drive signal while the body diode is conducting. By the way, there are no additional voltage stresses on the auxiliary switch while its operate under soft switching.
Fig. 6(e) shows the voltage and current waveforms of D 3 . Reverse recovery current of the diode and a discharge current of the capacitor are shown in that figure.
The voltage and current waveforms of the snubber capacitor are shown in Fig. 6(f) . The voltage across the snubber capacitor starts to increase when the resonance is started with the auxiliary transistor turn on in the ZVT interval of the boost switch. It becomes zero nearly half of the output voltage at the end of the ZVT interval. At the end of the ZCT interval, the capacitor voltage is equal to zero.
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Some oscillograms with the scales of 5 V/div, 1 µs/div for only (a), 200 V/div, 2 A/div, 1 µs/div for (b)-(g): (a) Control signals of S1 and S2; (b) Voltage and current of S1; (c) Voltage and current of DF; (d) Voltage and current of S2; (e) Voltage and current of D3; (f) Voltage and current of Cs.
The input voltage and current waveforms are given in Fig. 7 . The power factor of the proposed converter is near unity with 0.99. Also, it is seen that the proposed PFC converter operates in CCM. Fig. 8 presents the response of the power factor for universal input line voltage for full load condition. It can be observed that the proposed converter will exhibit a power factor of near 0.99 at any power line voltage between 85 and 260 V rms . The proposed converter is tested at universal input line voltage and very wide load ranges. It is observed that it keeps operating under soft switching conditions successfully for the whole line and load ranges.
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The input voltage and current waveforms with the scales of 100 V/div, 5 A/div and 5 ms/div.
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The input voltage and current waveforms with the scales of 100 V/div, 5 A/div and 5 ms/div.
In the Fig. 9 , efficiency waveform of the proposed converter is given for the range of universal input line voltage at full load. The efficiency value is increasing along with the line voltage. Basically, losses depend on current in the converters. In order to obtain the same output power, the input current decreases when the input line voltage increases.
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Converter efficiency at full load and varying line voltage.
In the Fig. 10 , efficiency variations of the proposed converter and the converter in [20] are given for 220 V rms input voltages. It can be seen that the efficiency values of the proposed converter which operates at 100 kHz are higher than the converter in [20] which operates at 50 kHz. The main reason of the efficiency improvement is all switches operate under exact soft switching in the proposed converter. The overall efficiency of the proposed converter is measured about 97.9% at the nominal output power.
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Efficiency curves of the proposed converter and the converter in [20].
6. Conclusion
In this study, a novel snubber circuit is used in the PFC converter. This snubber circuit provides ZVT turn on and ZCT turn off together for the boost switch of the converter. Also, it is implemented by using only one quasi resonant circuit without an important increase in cost and complexity. The proposed converter solves many drawbacks of the PFC converters presented earlier. All semiconductor devices in the circuit are switched under soft switching. The boost switch is not subjected to any additional voltage stress. The boost diode is not subjected to any additional voltage and current stresses. A detailed steady-state analysis of the proposed converter is presented. The theoretical analysis of the proposed converter is exactly verified by 500 W and 100 kHz prototype. The average current mode control method is used in the proposed converter. The power factor of the proposed converter is measured nearly 0.99. Additionally, at nominal output power, the converter efficiency is reach approximately 97.9%.
Nomenclature
CF Output capacitor CP Parasitic capacitor Cs Snubber capacitor DF Boost diode D1 Body diode of the boost switch D2 Body diode of the auxiliary switch D3,4 Auxiliary diode Dr1,r2,r3,r4 Rectifier diode fs Switching frequency iac Line current iDF Boost diode current Ii Input current Io Output current iLsa, iLsb Snubber inductor current iS1 Boost switch current LF Boost inductance Lsa, Lsb Snubber inductor RL Load S1 Boost switch S2 Auxiliary switch tf1 Current fall time of boost switch tr2 Current rise time of auxiliary switch tZVT ZVT interval tZCT ZCT interval vac Line voltage vCp Parasitic capacitor voltage vCs Snubber capacitor voltage VCsmax Maximum snubber capacitor voltage vD3 Auxiliary diode voltage vS1 Boost switch voltage vS2 Auxiliary switch voltage Vi Rectified input voltage Vo Output voltage Z1,2 Resonant impedance 𝜔1,2,3 Radial resonant frequency
BIO
Nihan ALTINTAŞ She received the B.S., M.S. and Ph.D. degrees in electrical engineering from Yıldız Technical University, Turkey, in 2004, 2007 and 2012 in electrical engineering at Yıldız Technical University. Her research has been concentrated on the areas of DC-DC converters, power factor correction techniques, and soft switching techniques in power electronics. She was also employed in three research projects concerning power electronics.
References
Singh S. , Singh B. 2011 “PFC Bridge Converter for Voltage-controlled Adjustable-speed PMBLDCM Drive” Journal of Electrical Eng. & Tech. 6 215 - 225    DOI : 10.5370/JEET.2011.6.2.215
Kalpana R. 2010 “Direct Single-stage Power Converter with Power Factor Improvement for Switched Mode Power Supply” Journal of Electrical Eng. & Tech. 5 468 - 476    DOI : 10.5370/JEET.2010.5.3.468
Zhonghu B. , Chen M. , Miller S. K. T. , Yasuyuki N. , Jian S. 2007 “Recent developments in single-phase power factor correction” Power Conversion Conference 1520 - 1526
Garcia O. , Cobos J.A. , Prieto R. , Alou P. , Uceda J. 2003 “Single Phase Power Factor Correction: A Survey” IEEE Trans. Power Electronics 18 749 - 755    DOI : 10.1109/TPEL.2003.810856
Qiao C. , Smedley K.M. 2001 “A topology Survey of Single-Stage Power Factor Corrector with a Boost Type Input Current Shaper” IEEE Trans. Power Electronics 16 360 - 368    DOI : 10.1109/63.923768
Bodur H. , Bakan A.F. 2002 “A New ZVT-PWM DC-DC Converter” IEEE Trans. Power Electronics 17 40 - 47    DOI : 10.1109/63.988668
Bodur H. , Bakan A.F. 2004 “A New ZVT-ZCT-PWM DCDC Converter” IEEE Trans. Power Electronics 19 676 - 684    DOI : 10.1109/TPEL.2004.826490
Hua G. , Leu C.S. , Jiang Y. , Lee F.C. 1994 “Novel Zero-Voltage-Transition PWM Converters” IEEE Trans. Power Electronics 9 213 - 219    DOI : 10.1109/63.286814
Hua G. , Yang E.X. , Jiang Y. , Lee F.C. 1994 “Novel Zero- Current-Transition PWM Converters” IEEE Trans. Power Electronics 9 601 - 606    DOI : 10.1109/63.334775
Mao H. , Lee F. C. , Zhou X. , Dai H. , Cosan M. , Boroyevich D. 1997 “Improved Zero-Current-Transition Converters for High-Power Applications” IEEE Trans. Industrial Application 33 1220 - 1232    DOI : 10.1109/28.633800
Cho J.G. , Baek J.W. , Rim G.H. , Kang I. 1998 “Novel Zero-Voltage-Transition PWM Multiphase Converters” IEEE Trans. Power Electronics 13 152 - 159    DOI : 10.1109/63.654970
Tseng C.J. , Chen C.L. 1998 “Novel ZVT-PWM Converters with Active Snubbers” IEEE Trans. Power Electronics 13 861 - 869    DOI : 10.1109/63.712292
Smith K.M. , Smedley K.M. 1999 “Properties and Synthesis of Passive Lossless Soft-Switching PWM Converters” IEEE Trans. Power Electronics 14 890 - 899
Yu H. , Song B. M. , Lai J. S. 2002 “Design of a Novel ZVT Soft-Switching Chopper” IEEE Trans. Power Electronics 17 101 - 108    DOI : 10.1109/63.988675
Wang C.M. 2006 “Novel Zero-Voltage-Transition PWM DC-DC Converters” IEEE Trans. Industrial Electronics 53 254 - 262    DOI : 10.1109/TIE.2005.862253
Huang W. , Moschopoulos G. 2006 “A New Family of Zero-Voltage-Transition PWM Converters with Dual Active Auxiliary Circuits” IEEE Trans. Power Electronics 21 370 - 379    DOI : 10.1109/TPEL.2005.869749
Das P. , Moschopoulos G. 2007 “A Comparative Study of Zero-Current-Transition PWM Converters” IEEE Trans. Industrial Electronics 54 1319 - 1328    DOI : 10.1109/TIE.2007.891663
Stein C. M. de O. , Hey H. L. 2000 “A true ZCZVT commutation cell for PWM converters” IEEE Trans. Power Electronics 15 185 - 193    DOI : 10.1109/63.817376
Aksoy I. , Bodur H. , Bakan A.F. 2010 “A New ZVT-ZCT-PWM DC-DC Converter” IEEE Trans. Power Electronics 25 2093 - 2105    DOI : 10.1109/TPEL.2010.2043266
Mesh M. , Panda A.K. 2012 “Increase of Efficiency of an AC-DC Power Factor Correction Boost Converter by a Novel Soft-switching Technique” Int. Journal of Electric Power Comp. and Sys. 40 57 - 73
Todd P.C. 1996 “UC3854 Controlled Power Factor Correction Circuit Design”, UNITRODE Product & Applications Handbook