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A 2D Analytical Modeling of Single Halo Triple Material Surrounding Gate (SHTMSG) MOSFET
A 2D Analytical Modeling of Single Halo Triple Material Surrounding Gate (SHTMSG) MOSFET
Journal of Electrical Engineering and Technology. 2014. Jul, 9(4): 1355-1359
Copyright © 2014, The Korean Institute of Electrical Engineers
  • Received : October 21, 2013
  • Accepted : January 14, 2014
  • Published : July 01, 2014
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About the Authors
P. Suveetha Dhanaselvam
Corresponding Author: Dept. of Electronics and Communication Engineering, Velammal College of Engg & Technology, Madurai, India. (suveethaj@gmail.com)
N. B. Balamurugan
Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering, Madurai, India. (nbbalamurugan@tce.edu.in)
G. C. Vivek Chakaravarthi
Dept. of Electronics and Communication Engineering, Velammal College of Engg & Technology, Madurai, India.
R. P. Ramesh
Dept. of Electronics and Communication Engineering, Velammal College of Engg & Technology, Madurai, India.
B. R. Sathish Kumar
Dept. of Electronics and Communication Engineering, Velammal College of Engg & Technology, Madurai, India.

Abstract
In the proposed work a 2D analytical modeling of single halo Triple material Surrounding Gate (SH-TMSG) MOSFET is developed. The Surface potential and Electric Field has been derived using parabolic approximation method and the simulation results are analyzed. The essential substantive is provided which elicits the deterioration of short channel effects and the results of the analytical model are delineated and compared with MEDICI simulation results and it is well corroborated.
Keywords
1. Introduction
The constant decrease in the device dimensions has been an inevitable factor to achieve the high speed, high packing density and excellent performance. The scaling down of traditional planar MOSFET’s persuades short channel effects such as threshold voltage roll off, Drain induced barrier lowering(DIBL), drive ability degradation and hot carrier effects which in turn put the ultimate performance under threat. Threshold voltage roll off is the ramification of shortening channel length while the strong electric field near the drain induces hot carrier effect. DIBL occurs when the drain voltage increases, the channel length also increases and gate loses its control which owing to the channel becomes more attractive to electrons and the barrier is lowered. The selection of surrounding gate MOSFET [1 - 5] is to overcome the scaling limitations as it possess high packing density with improved gate controllability and short channel immunity as the gate is all around the silicon pillar and therefore, control over the channel is increased. In addition, the surrounding gate also includes gate engineering which produces dual material surrounding gate MOSFET [6 - 8] . It is extended further by increasing the number of gate materials and this developed a device called Triple material Surrounding gate (TMSG) MOSFET [9] . We have already derived the analytical model for TMSG MOSFET [10 - 11] which proved more advantageous than DMSG MOSFET. The threshold voltage roll off is one of the challenging issues in the short channel effects occurring in nanoscale MOSFET devices. It can be reduced further by introducing halo or pocket implants [12 - 13] . Hence, the short channel effects can be further reduced by our novel structure which incorporates the advantages of triple material gate surrounding gate MOSFET’s and halo called single halo triple material surrounding gate (SHTMSG) SOI MOSFET is proposed.
2. Proposed Model
The single halo triple material surrounding gate (SHTMSG) SOI MOSFET is shown in Fig. 1. The surrounding gate MOSFET consists of three gate material of different work functions. In this TMSG structure, halo is introduced for the first time to form a device structure called Single halo triple material surrounding gate (SHTMSG) MOSFET. The lengths of the gate materials are L 2 , L 3 L 2 and L 4 L 3 respectively. The model considers single halo doping in the channel near the source and triple material gate. The length L 1 is halo doped with doping concentration N h whereas the other regions are doped with N c , assuming N h is greater than N c . Considering the gate structure and halo doping, the structure is divided in to four regions.
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Cross sectional diagram of Single halo Triple material surrounding gate (SHTMSG) MOSFET
Due to the cylindrical symmetry of the device structure, a cylindrical coordinate system is used and it consists of a radial direction r , a vertical direction z , and an angular component θ . The symmetry of the structure implies that the potential and electric field have no variation in the θ direction. Hence a two dimensional analysis is sufficient.
The surface potential and the electric field is derived by solving the Poisson equation. Neglecting the influence of the charge carriers and fixed oxide charges on the electrostatics of the channel, the 2D Poisson equation of potential distribution in the silicon pillar can be given as
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, i =1, 2, 3, 4
Where N 1 = N h , N 2 = N 3 = N 4 = N c , L 0 = 0 , φi ( r , z ) represents the potential distribution.
Using parabolic approximation method, the Poisson equation is solved and the solution is given as
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Where the arbitrary constants c 1 ( z ), c 2 ( z ), c 3 ( z ) are found out by solving and substituting the boundary conditions.
The Poisson’s equation is solved separately under different regions using the following boundary conditions.
(a) The electric field in the centre of the silicon pillar is zero by symmetry given as
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(b) The electric flux at the gate/oxide interface is continuous for metal gates:
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where i =1, 2, 3, 4
(c) The surface potentials at the interfaces of the dissimilar metals are continuous:
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(d) The electric field at the interfaces of the dissimilar metals are continuous:
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(e) The potential at the source end is
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Where built in potential is given by
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kB is the Boltzmann Constant and
T is the temperature
(f) The potential at the drain end is
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Using the boundary conditions (3)-(10) the surface potential is determined using parabolic approximation method:
Surface potential is expressed as
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Where
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VFBn =φMnφsi n=1,2,3,4 Where
φ Mn represents the work function of the gate materials
φ si is the silicon work function which is given by
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The solution of the equations using complementary function and particular integral is obtained as
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Substituting the boundary conditions the expressions of the constants are determined and given in Eqs. (18)-(25)
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Where
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β 1 = e KL1 , β 2 = e KL2 , β 3 = e KL3 , β 4 = e KL4 , β 5 = e K ( L + L 1 + L 2 ) β 1 -1 = e -K L1 , β 2 -1 = e -K L2 , β 3 -1 = e -K L3 , β 4 -1 = e -K L4
The Electric field is defined as the derivative of surface potential. The electric field pattern determines the electron transport velocity through the channel.
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In the case of the SH-TMSG structure, due to the coexistence of three metal gates with different work functions as well due to the halo structure, the surface potential minimum is solely determined by the halo part, which lies in the metal gate with higher work function.
Therefore the minimum surface potential of the silicon pillar under the gate can be calculated as, differentiating φ S1 ( z ) with respect to z and equating to zero.
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The threshold voltage is defined as the gate voltage in region 1 at which the minimum surface potential is twice the bulk potential,
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By substituting V gs = V t in Eq. (28) and solving for V t , threshold voltage is obtained as
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3. Results and Discussions
The performance of the single halo Triple material surrounding gate (SH-TMSG) MOSFET is studied by analyzing the surface potential and electric field. The analytical models are verified by MEDICI simulation. Simulation parameters: V gs = 0.2 V , V ds = 0.6 V , t ox = 4 nm , t si = 50 nm , N h = 3×10 17 cm −3 , N c = 4×10 16 cm −3 , N D =10 20 cm −3 , L 1 = 40 nm , L 2 = 50 nm , L 3 = 70 nm , L 4 = 90 nm
The surface potential distribution of SHTMSG and TMSG structure is plotted in Fig. 2. It can be seen that the minimum surface potential occurs in the halo part for SHTMSG and it is still lower compared to TMSG structure. The minimum surface potential for TMSG MOSFET occurs in the first metal gate and it is higher when compared. In the proposed SH-TMSG structure, there is an extra potential step on the right of the minimum surface potential when compared. This improves the short channel effects and current drive capability effectively.
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Surface potential distribution of single halo triple material surrounding gate (SH-TMSG) MOSFET
The electric field of SH-TMSG structure is shown in Fig. 3. It can be observed that the electric field has an extra peak over the halo boundary and this improves the performance of the device. Compared to TMSG structure the number of peaks is more in SH-TMSG, thus improving SCEs. The increase in halo concentration improves the first peak and increase in the work function of the first metal gate improves the second peak thus increasing the speed up of the carriers. This produces better performance and current drive capability.
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Electric field of single halo triple material surrounding gate (SH-TMSG) MOSFET
Performance analysis of SHTMSG MOSFET
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Performance analysis of SHTMSG MOSFET
4. Conclusion
The 2D analytical model is developed for surface potential and electric field of single halo triple material surrounding gate MOSFET(SHTMSG). It is shown that SHTMSG shows better performance in suppressing the shortchannel effects and hotcarrier effects. The peaks and stepup obtained in the halo boundary of the device makes the carriers travel through the channel more quickly. SHTMSG provides more flexible process for optimizing the performance.
BIO
P. Suveetha Dhanaselvam She received her B.E degree in Electronics and Communication Engineering and her M. E degree in Applied Electronics. She is pursuing Ph.D in triple material nanoscale MOSFETs. Her research interests include device modeling and simulation.
N. B. Balamurugan He received his B.E and M.E degrees, both in electronics and communication engineering from the Thiagarajar College of Engineering (TCE), Tamilnadu, India. He has obtained his Ph.D degree in nanoelectronics at Anna University. He is currently as an Associate Professor in Thiagarajar College of Engineering (TCE), Tamilnadu, India. His research interests include modeling and simulation of novel structures on SOI MOSFETs.
G. C. Vivek Chakaravarthi He pursues B.E in Electronics and Communication Engineering in Velammal College of Engineering and Technology, Madurai. He is interested in analog VLSI.
R. P. Ramesh He pursues B.E in Electronics and Communication Engineering in Velammal College of Engineering and Technology, Madurai. He is interested in nanoscale MOS devices.
B. R. Sathish Kumar He pursues B.E in Electronics and Communication Engineering in Velammal College of Engineering and Technology, Madurai. He is interested in modeling and simulation of MOS devices
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