This paper proposes a novel test circuit for SiC transistors. Onstate resistance under practical application conditions is an important characteristic for the device reliability and conduction efficiency of SiC transistors. In order to measure the onstate resistance in practical applications, high voltage is needed, and high current is also necessary to ignite performance for the devices. A softswitching circuit based on synchronous buck topology is developed in this paper. To provide highvoltage and highcurrent stresses for the devices without additional spikes and oscillations, a resonant circuit has been introduced. Using the novel circuit technology, softswitching can be successfully realized for all the switches. Furthermore, in order to achieve accurate measurement of onstate resistance under switching operations, an active clamp circuit is employed. Operation principle and design analysis of the circuit are discussed. The dynamic measurement method is illustrated in detail. Simulation and experiments were carried out to verify the feasibility of the circuit. A special test circuit has been developed and built. Experimental results confirm that the proposed circuit gives a good insight of the devices performance in real applications.
1. Introduction
Siliconcarbide (SiC) transistors are gaining popularity for their enormous potential
[1

4]
. Recent demonstrations show that SiC transistors can attain outstanding properties such as higher electron density, lower draintosource onresistance, lower thermal resistance, and higher breakdown voltage in comparison to silicon (Si) counterparts
[5

10]
. Although much progress has been achieved in the development of new power devices, power converters that employ SiC transistors have not become commercially available, because device performance issues under switching operation have not been sufficiently discussed yet
[11

14]
.
To improve these promising nextgeneration power devices, it is also highly desirable to evaluate the characteristics, such as onstate resistance, during device measurements, especially under realistic power electronics conditions
[15

17]
.
The traditional method to characterize onstate resistance is the pulse IV step measurement, which is shown in
Fig. 1
. This technique requires special equipment and cannot mimic the actual applications. However, few research papers have been produces to measure dynamic onstate resistance of the new devices over the past years
[18

20]
. In
[18]
a VIENNA boost converter to character the GaN transistors under operating condition is developed using a Wilson current mirror based circuit to measure dynamic draintosource voltage of the devices. The converter can be used to measure dynamic onstate resistance, gate charge, miller charge, and switching time, etc. But the clamp voltage contains a spike at the transition to the offstate of the switching device. In
[20]
a voltage clamp circuit using power MOSFET and zener diode is presented. This technique can test GaN transistors in softswitching and hardswitching conditions. However, the measured dynamic draintosource voltage can be influenced by the auxiliary MOSFET body diode and its application is limited.
The traditional method to measure onstate resistance.
In addition, to evaluate a power switch under actual switching operation
[5
,
20
,
21]
, the extreme conditions (e.g., high voltage and high current) should be implemented. Unfortunately, simultaneously high voltage and current power supply (e.g., 400V/50A) in a test laboratory are difficult due to the limited capacity of power installation. Furthermore, reproduction of high voltage and current stresses by means of direct testing should be confronted with huge equipment.
In this paper, a novel and effective measurement technique for SiC transistors has been presented which involves typical equipment. This proposed technique could reproduce the voltage and current stresses equal to or greater than those which meet in real applications by employing common power supplies. This is one of the merits of the proposed test circuit. To avoid the measurement saturation of oscilloscope, a new and simple voltage clamp circuit is developed with achieving accurate measurement of onstate resistance, which is another merit of the circuit. The proposed circuit gives a good insight of devices performance in real applications. Simulation and experimental results under extreme conditions confirm the validity of the proposed circuit.
This paper is organized as follows. Section II describes the operation principle and detailed analysis of the circuit. Section III discusses the design procedure of the proposed circuit. Section IV explains the measurement method of the onstate resistance. Section V features the simulation and experimental results. Finally, conclusions are presented in Section VI.
2. Circuit Configuration and Operation
 2.1 Circuit configuration
The configuration of the proposed circuit is shown in
Fig. 2
. The main structure of the circuit is based on a synchronized buck converter which is designed to operate in discontinuous inductor current mode (DCM).
The proposed test circuit.
The test system consists of a voltage source
V_{H}
, an upper side Si power MOSFET
Q_{H}
, a current source
V_{L}
, an ultrafast diode
D
, an
LC
filter, an active voltage clamp circuit, and DUT (device under test), where
Q_{H}
,
D
,
LC
filter and the DUT compose the basic synchronized buck converter.
In the configuration,
C_{Qaux}
and
C_{DUT}
are denoted as the equivalent output capacitances of
Q_{aux}
and
Q_{DUT}
, respectively, which consist of the draintosource and snubber capacitance of each switch. The high side MOSFET,
Q_{H}
, and the DUT operate complementarily with a variable deadtime. The auxiliary Si MOSFET,
Q_{aux}
, operates synchronously with the DUT. The series
LC
filter together with a damping power resistor
R_{L}
is connected to the positive terminal of the low voltage high current power supply
V_{L}
directly.
As the same with conventional synchronized buck converter, the main function of
Q_{H}
is to provide high voltage stress during the offstate of the DUT. The diode
D
is used to provide a freewheeling path for the inductance current
i_{Lr}
, to impede high voltage stress from
V_{H}
, and the most important, to supply high current stress to the DUT. The main function of the inductor
L_{r}
is to absorb the energy stored in the output capacitance of
Q_{DUT}
,
Q_{aux}
, and
D
to realize soft switching by resonance during transitions. The capacitor
C_{R}
is used to store the energy delivered by
L_{r}
and prevent any potential DC voltage from
V_{H}
to
V_{L}
.
As shown in
Fig. 2
,
R_{1}
is denoted as a thermally protected fusing resistor for overcurrent protection of
V_{H}
.
R_{2}
is a low value power resistor to limit the current stress of DUT. In the conventional synchronized buck converter,
R_{L}
is the load of the converter, consuming a lot of power. However, it should be noted that in this proposed circuit, as the inductor is designed much smaller than the critical conduction mode value, the power consumed by
R_{L}
can be considerable small. Therefore, the extra voltage and current stresses incurred by the
LC
filter and
R_{L}
can be neglected.
The voltage clamp circuit consists of the auxiliary switch
Q_{aux}
and the blocking capacitor
C_{clamp}
, which are parallel with the DUT. The measurement principle of the circuit will later be illustrated in Section III.
 2.2 Circuit operation principles
To understand the voltage and current stresses of the DUT and to analyze the switching characteristic in detail, it is necessary to explain the operation principles of the circuit and some important equations during transitions.
To simplify the analysis, it is assumed that all the switching devices are ideal except the above illustration. The capacitance of
C_{R}
is assumed large enough so that the voltage on it, denoted as
V_{CR}
, stays constant approximately. As the inductor is operated in DCM, the inductance current
i_{Lr}
would change direction before the next switching cycle.
The operation of the circuit can be divided into eight main stages in one switching period. The signal control sequence of the switches and the corresponding key waveforms of the operation are illustrated in
Fig. 3
.
Fig. 4
shows the conduction path and current direction in every transition. The detailed analysis of this converter will be thoroughly examined in the following.
Theoretical waveforms of the proposed circuit.
Equivalent circuits for each operation mode: (a) Stage 1 [t_{0}  t_{1}]; (b) Stage 2 [t_{1}  t_{2}]; (c) Stage 3 [t_{2}  t_{3}]; (d) Stage 4 [t_{3}  t_{4}]; (e) Stage 5 [t_{4}  t_{5}]; (f) Stage 6 [t_{5}  t_{6}]; (g) Stage 7 [t_{6 } t_{7}]; (h) Stage 8 [t_{7}  t_{8}].
Stage 1 [
t_{0}  t_{1}
] [see
Fig. 4(a)
]: This stage begins at
t_{0}
when the high side switch,
Q_{H}
, is in on state and the high voltage is applied to
L_{r}
and
C_{R}
. The inductance current
i_{Lr}
increases linearly from zero with the ramp rate controlled by the
V_{H}
and
L_{r}
, ending at a peak current value
i_{L}(t_{1})
. The inductance value is designed big enough that
i_{Lr}
increases slowly with a very small average value. The DUT and
Q_{aux}
are in off state so that high voltage stress is applied to DUT. The voltage across
C_{clamp}
is clamped at a low level value as there is no current circulation through
Q_{aux}
, which is the main function of the voltage clamp circuit.
V_{CR}
is charged up by the inductor current. The inductance current
i_{L}(t)
and the draintosource voltage of DUT
v
_{DS_DUT}
(
t
) are given by
In this stage, the current stress of the DUT is zero.
Stage 2 [
t_{1}  t_{2}
] [see
Fig. 4(b)
]: This stage starts by turning
Q_{H}
off, and thus,
v_{DS_H}
begins to increase. Because of the deadtime between gate driver signals, DUT and
Q_{aux}
are still in off state. As shown in
Fig. 4(b)
,
V_{L}
is lower than the voltage across the DUT. The diode current
i_{Diode}
cannot flow and
D
is reverse biased. A resonance starts among
L_{r}
,
C_{clamp}
,
C_{Qaux}
,
C_{DUT}
, and
C_{QH}
. Due to the resonant nature, when
v_{DS_DUT}
decreases to
V_{L}+V_{CR}
at time
t_{a}
, the inductance current
i_{Lr}
reaches to its maximum value
i_{LMax}
. As a result,
i_{Lr}
first increases and then decreases in a very short period. In addition, the DUT current
i_{DUT}
continues to flow through its output capacitance
C_{DUT}
until
v_{DS_DUT}
is equal to
V_{L}
. Along with the decreasing of
v_{DS_DUT}
, the clamped voltage
v_{clamp}
also decreases. During the interval [
t_{1}  t_{a}
],
i_{Lr}
and
v_{DS_DUT}
are expressed as
where
i_{LMax}
is the resonant peak value of
i_{Lr}
,
Z_{0}
is the equivalent impedance of the resonant circuit,
As for the interval time [
t_{a}  t_{2}
], the voltage applied to DUT decreases from
V_{L}+V_{CR}
. This stage period
t_{12}
is
Stage 3 [
t_{2}  t_{3}
] [see
Fig. 4(c)
]: Once
v_{DS_DUT}
reaches
V_{L}
at time
t_{2}
, diode
D
is forward biased and provides a freewheeling path for the inductance current and the resonance process is stopped. During this stage, the voltage applied to
Q_{H}, v_{DS_H}
, is kept at
V_{H}−V_{L}
+
V_{D}
. Meanwhile, the energy associated with
L_{r}
is drawn to the “load” resistor
R_{L}
. As a result, the inductance current
i_{Lr}
decreases at a slow rate. The time of this stage is prescribed by the deadtime control. The voltage stress of
Q_{DUT}
is
where
V_{D}
is the forward voltage of the diode
D
. The current stress of
Q_{DUT}
is zero within this period.
Stage 4 [
t_{3}  t_{4}
] [see
Fig. 4(d)
]: At time
t_{3}
, the DUT and
Q_{aux}
are turned on synchronously. Since the voltage
V_{L}–V_{D}
is much lower than
V_{H}
, the switches are operated under ZVS approximately. The high current stress supplied by
V_{L}
are applied to the DUT. By proper design of auxiliary circuit and gate driver timing, as discussed in the next section, the clamped voltage applied to
C_{clamp}
,
v_{clamp}
, goes closely approximate to
v_{DS_DUT}
in a high precision. Within this period, the inductance current
i_{Lr}
continues flowing through the diode and decreasing linearly. The draintosource voltage of
Q_{H}
increases to
V_{H}–v_{DS_DUT}
. At the end of this interval,
i_{Lr}
falls down to zero. During this stage, the voltage and current stresses across to DUT can be expressed as:
and
respectively, where
r_{DS(on)}
is the dynamic on resistance of the DUT.
Stage 5 [
t_{4}  t_{5}
] [see
Fig. 4(e)
]: At time
t_{4}
, the inductance current
i_{Lr}
reverse its polarity and starts to increase from zero. As the DUT and
Q_{aux}
are still in on state during this period, the diode
D
continues conducting with a very low impedance, indicating that the inductance current
i_{Lr}
will mainly flow through
D
rather than DUT. Therefore, the influence of
i_{Lr}
to
i_{DS_DUT}
can be neglected, especially when
i_{DS_DUT}
is much bigger than
i_{Lr}
. In this interval, the voltage and current stresses to the DUT are the same with Stage 4. The inductance current
i_{Lr}
is given by
Stage 6 [
t_{5}  t_{6}
] [see
Fig. 4(f)
]: This stage starts by turning the DUT and
Q_{aux}
off. Due to the existence of
C_{Qaux}
and
C_{DUT}
, the switches are turned off under ZVS. As there is a deadtime,
Q_{H}
keeps off in this stage. Once DUT is turned off, the diode
D
starts the reverse recovery process in a very short interval, after which a resonance occurs among
L_{r}
,
C_{clamp}, C_{Qaux}, C_{DUT}
, and
C_{QH}
. Thus,
C_{clamp}, C_{Qaux}
and
C_{DUT}
are charged while
C_{QH}
is discharged. At time
t_{b}
,
v_{DS_DUT}
increases to
V_{L}+V_{CR}
, and the inductance current
i_{Lr}
reaches to its maximum value
i’_{LMax}
in the opposite direction. Therefore, the inductance current
i_{Lr}
first increases and then decreases after a very short period. Meanwhile, as the capacitance
C_{clamp}
is much bigger than
C_{Qaux}
, the clamped voltage
v_{clamp}
are kept in a very low level comparing with
v_{DS_DUT}
. The voltage stress applied to the DUT equals to the capacitance voltage of
C_{DUT}
, which is given by
As the resonant circuit constitution in this stage is the same with in Stage 2, we can get that
i_{LMax}
=
i’_{LMax}
. Comparing with
V_{H}
and
V_{CR}, V_{L}
is significantly small, thus, the parasitic capacitors’ charging time from 0 to
V_{L}
is very short and can be neglected. In addition, since
i_{Lr}
is considerable small, current stress of the DUT in this stage can be neglected. This stage period
t_{56}
can be expressed as
The inductance current
i_{Lr}
is given by
Stage 7 [
t_{6}  t_{7}
] [see
Fig. 4(g)
]: At time
t_{6}
, the voltage of
C_{DUT}
is charged up to
V_{H}
and the draintosource voltage of
Q_{H}
falls down to zero. Thus, the body diode of
Q_{H}
starts to conduct and provides a freewheeling path to the inductance current
i_{Lr}
. The resonance process ends at
t_{6}
, and therefore,
i_{Lr}
decreases linearly with a small average value
As a result, during this period, the voltage stress of the DUT is given by
and the current stress is zero. In addition, the clamped voltage
v_{clamp}
is kept at its maximum value.
Stage 8 [
t_{7}  t_{8}
] [see
Fig. 4(h)
]:
Q_{H}
is turned on at time
t_{7}
. Since the body diode is in on state, the switch is operated under ZVS. The high voltage stress
V_{H}+i_{L}(t)R_{1}
is still applied to the DUT and the voltage clamp circuit. The freewheeling path of the inductance current
i_{Lr}
changes to
Q_{H}
from the body diode.
This stage ends when the inductance current
i_{Lr}
reaches zero and begins to increase in the opposite direction. Therefore, at the moment
t=t_{8}
, one switching cycle is completed and a new switching cycle starts.
3. Analysis of the Measuring Stage
In order to improve the reliability and performance of new power devices, the characteristics measurement should be discussed under practical operations. From the principle analysis in the previous section, the proposed circuit can represent real operating circumstances, and gives a good insight into the performance of the devices in practical applications. The proposed system, which is a combination of a regular synchronous buck topology, a low voltage high current power supply, and an active clamp circuit comprising an additional switch and a capacitor, makes it possible to measure various characteristics under real power applications, such as high voltage and high current conditions.
The main circuit can be designed like a regular synchronized buck converter which works in DCM. However, unlike the conventional synchronous buck converter, the main concept of the proposed system is to perform the characteristics measurement of SiC transistors. Therefore, the design considerations have a lot of differences, which are important during measurements, such as operation mode, power capacity, and deadtime of control signals.
To achieve ZVS of the DUT, it is necessary that the energy stored in
L_{r}
at the moment
Q_{H}
turning off should be larger than or equal to the energy required to discharge the output capacitance of
Q_{H}, Q_{aux}
and
Q_{DUT}
down to zero.
Furthermore, reduction of the peak voltage and current stresses of the DUT can be achieved by adjusting the inductance current and the deadtime of driving signals. The deadtime is needed to avoid cross conduction between the switches and to realize softswitching.
From the analysis in Section II, the ZVS conditions can be expressed as:
Therefore, we have
and
During the deadtime the voltage over DUT cannot decrease below input voltage
V_{L}
. Therefore, the maximum reasonable deadtime is the one that is needed to lower the voltage over the switch to
V_{L}
level. A longer deadtime would be unnecessary. A certain amount of magnetizing current is required in order to reduce the voltage level over the DUT switch prior to its turnon.
Based on the superposition theorem and boundary conditions of operation mode of the converter, when operating in criticalconductionmode (CrM), we can get that
where
D
is the duty ratio of the CrM converter.
From (21) and (23), the ZVS conditions (18) and (19) can be simplified as:
From the conventional critical inductance design, the maximum value of
L_{r}
can be designed as:
where
f_{s}
is the switching frequency.
In actual applications, waveforms contain spikes and oscillations. In this proposed circuit, it is possible to turn on the main switch at a relatively low voltage level with the help of the series
LC
filter, and therefore, the influence of peak voltage stress can be reduced.
The electrical performance of the device represents its viability in power applications. SiC transistors are still in a development stage, therefore, there is a good opportunity to study, design, and test not only a device but also the processes involved. This test circuit provides a very helpful tool to get an optimal design.
4. Dynamic Onresistance Measurement Method
The measurement method of DUT dynamic onresistance operating in switching mode is based on the Ohms law, being calculated by dividing
v_{DSon}
by
i_{DS}
In real applications, the draintosource voltage of the DUT usually swings in a large range such as hundreds of volts in the offstate and several millivolts in the onstate. Direct measurement using oscilloscope voltage probes either gives poor accuracy or causes saturation of the oscilloscope channel. To avoid of these problems, an active clamp circuit is employed in the proposed system to avoid the oscilloscope saturation in offstate.
Fig. 5
presents the equivalent configuration of the active clamp circuit. The operation principle is discussed in Section II and shown in
Fig. 3
. The output voltage waveform
v_{DS} (t)
of the DUT is measured between the nodes A and B using a differential probe.
R_{probe}
denotes the impedance of the oscilloscope probe, which is about 1㏁ generally.
r_{Qaux}
and
r_{DSon}
denote the onstate resistance of
Q_{aux}
and DUT, respectively.
Equivalent circuits for for r_{DS_on} measurement: (a) off state; (b) on state.
As shown in
Fig. 5(a)
, when DUT and
Q_{aux}
are turned off, high voltage stress
v_{DSoff}
is applied to the DUT and the active clamp circuit. The measured value of the probe can be expressed as follows:
where
Z_{clamp}
and
Z_{Qaux}
are the equivalent impedance of
C_{clamp}
and
C_{Qaux}
, respectively. In the system design, it is easy to achieved that
Therefore, the measured voltage
v_{clampoff}
can be clamped and approximated as
indicating that the measured result is “clamped” at a considerable small value comparing with
v_{DSoff}
.
During the onstate of the DUT, as shown in
Fig. 5(b)
, a high current stress is applied to the DUT along with a very small draintosource voltage. The measured voltage across
C_{clamp}
can be calculated by
where
r_{Qaux}
is very small with only tens of milliohm generally. As
Z_{clamp}
≫
r_{Qaux}
, the measured
v_{clampon}
can be simplified as
which means the measured voltage is extremely close to the real value
v_{DSon}
.
Assuming that
r_{DSon}
of the DUT and
Q_{H}
are 90mΩ and 45mΩ, respectively, the output capacitances of
Q_{aux}
and the DUT are 500pF,
C_{clamp}
is 0.1µF, the switching frequency is 50 kHz, and the onstate DUT current is 1A. We can get that during off state,
while during on state
According to the example result, the active clamp circuit can measure the onstate voltage
v_{DSon}
with a high precision. Meanwhile, because of the clamp capacitor and the synchronous operation with the DUT, the proposed circuit can measure the onstate
v_{DSon}
dynamically without the influence of high voltage swing. The value of the offstate clamped voltage
v_{clampoff}
can be adjusted by using different clamp capacitors. Based on (26), the dynamic onstate resistance of the DUT can be calculated with a high precision.
5. Simulation and Experimental Results
 5.1 Simulation results
Based on the operation analysis, a PSIM model of the proposed system has been developed. A comprehensive simulation was conducted to verify the performance of the test circuit.
In order to examine the proper performance of the rectifier in practical applications, actual semiconductor models of the power devices were employed.
The experimental waveforms are shown in
Figs. 6
and
Fig. 7
. The driver signals, draintosource voltages of DUT and
Q_{H}
, and the current waveforms of DUT and
L_{r}
are shown in
Fig. 6
. According to the waveforms, softswitching is achieved for both of the DUT and
Q_{H}
. It can be observed that the inductance current is small enough that the influence on the DUT current can be insignificant.
Simulation switching results.
Simulation results of the onstate resistance measurement circuit.
The simulation waveforms of the voltage clamp circuit are shown in
Fig. 7
. While the draintosource voltage
V_{ds}
DUT swings between onstate voltages to up to 400V, the clamped voltage
V_{clamp}
changes from onstate voltage to around 2.5V. The clamped onstate voltage is 0.770143V which is very close with the real voltage 0.770427V. Therefore, using the voltage clamp circuit, onstate resistance can be circulated in a high precision.
 5.2 Experimental results
A prototype of 400V/10A capacity circuit was performed to verify the theoretical analysis of the proposed circuit. The photograph related to the experimental circuit is given in
Fig. 8
. Some parameters of the prototype circuit are listed in
Table 1
. A SiC transistor manufactured by ROHM, SCH2090KE, is chosen as the DUT. The key parameters of the device are shown in
Table 2
with reference to the device datasheet. To avoid the temperature influence, a big heatsink and two high power fans were employed during experiments, making sure that the device temperature was kept in 28℃ ~ 30℃.
The prototype of the proposed test circuit.
Parameters of the prototype circuit
Parameters of the prototype circuit
Parameters of DUT in the prototype circuit
Parameters of DUT in the prototype circuit
Experiments have been carried out to verify the analysis. The switching waveforms of DUT and
Q_{H}
are shown in
Figs. 9
and
Fig. 10
. In
Fig. 9
, the voltage, current, and control waveforms of the DUT are illustrated. As the same with simulation results, the switches DUT and
Q_{H}
are operated under softswitching at both turnon and turnoff.
Experimental switching waveforms of the proposed circuit. V_{GS}: driver signal of DUT, V_{DS}: draintosource voltage of DUT, V_{DS_H} : draintosource voltage of Q_{H} , I_{DS}: draintosource current of DUT.
Experimental waveforms of the proposed circuit. V_{GS}: driver signal of DUT, V_{DS}: draintosource voltage of DUT, V_{Cr}: voltage across C_{R}, I_{L}: inductance current.
The measured waveforms of active clamp circuit are given in
Fig. 11
. To measure the onstate voltage and current accurately and steadily, the switching frequency was set at 50 kHz. And to eliminate the device temperature increasing, the maximum draintosource current was set at 6A. According to the waveforms, the auxiliary switch
Q_{aux}
was activated synchronously with the DUT. During off state of the switches, the clamped voltage
v_{clamp}
was clamped at lower than 3V, while the actual draintosource voltage of the DUT was up to 400 V. During the on state,
v_{clamp}
can indicate the real value of the DUT voltage.
Experimental waveforms of active clamped circuit with V_{GS} =18V. V_{DS}: draintosource voltage of DUT, V_{clamp}: clamped voltage across C_{aux}, I_{DS}: draintosource current of DUT.
These results were quite similar to those in the previous study where switching waveforms were simulated.
Figs. 12
to
Fig. 17
described the experimental results on the
r_{DSon}
measurement using oscilloscope probe directly and the active clamp circuit. To evaluate the onstate performance of the DUT under different conditions, the gate driver voltages of the DUT were set as 10V, 14V, and 18V, respectively. The voltage range for comparison was set as 0 ~ 100V in the experiments. Because of the measurement resolution problems, the onstate resistance could not be measured in a high accuracy for conventional circuits. Especially, as the draintosource voltage increases, the oscilloscope should be set from 0.1V/div to 10V/div. As onstate resistance is usually less than 1Ω, direct oscilloscope measurement leads a big problem of measurement error.
The comparison results of onstate resistance with V_{GS} = 10V.
The experimental result measured by the clamp circuit under full range with V_{GS} = 18V.
Fig. 12
,
Figs. 14
, and
Fig. 16
compared the measured results through oscilloscope probe and the active clamp circuit. It can be observed that as the draintosource voltage increased, the
r_{DSon}
which was calculated based on using the probe directly drifted significantly. However, the experimental results via the active clamp circuit kept stable with a high resolution. The measurement errors of the oscilloscope probes were up to 30％, 94％, and 150％ under 10V, 14V, and 18V driving voltages, respectively, comparing with the active clamp circuit.
The experimental results under full voltage range of 0 ~ 400V based on the active clamp circuit are shown in
Fig. 13
,
Figs. 15
, and
Fig. 17
. It is shown that under 10V gate voltage, the onstate resistance of DUT varies a little from 0.419Ω to 0.436Ω, while under 14V gate voltage, the resistance varies from 0.1462Ω to 0.1518Ω. Comparing with the value in datasheet, 0.09Ω, under 18V gate voltage, the onstate resistance changes from 0.0942Ω to 0.0979Ω, illustrating that the DUT has a stable onresistance performance under large voltage range.
The experimental result measured by the clamp circuit under full range with V_{GS} = 10V.
The comparison results of onstate resistance with V_{GS} = 14V.
The experimental result measured by the clamp circuit under full range with V_{GS} = 14V.
The comparison results of onstate resistance with V_{GS} = 18V.
Consequently, in terms of the onstate resistance measurement, the active clamp circuit is considered as a reasonable and accurate method.
According to the results above, the calculated results are almost identical to those simulated and measured. As a result, it can be clearly seen that the predicted theoretical analysis and operation principles of the proposed circuit are experimentally verified.
6. Conclusion
In this study, a novel circuit for SiC transistors characterization measurement has been analyzed in detail. The proposed circuit is based on the conventional synchronous buck converter operating in DCM. By employing two separated normal power supplies, the test system can mimic practical application conditions to test the reliability and performance of the DUT. To overcome the resolution problems when measuring onstate resistance under realistic switching operation, an active clamp circuit is developed. It is observed that the operation principles and the theoretical analysis of the novel circuit are exactly verified by experimental results. It should be noted that the proposed method of this paper could be extended to Gallium Nitride (GaN) devices for current collapse characteristics measurement.
Acknowledgements
This work was supported by the Energy Efficiency ＆ Resources of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korea government Ministry of Knowledge Economy. (No. 2012T100100651)
BIO
Guoen Cao received the B.S degree in electrical engineering from Shandong University of science and technology, Qingdao, China, in 2009 and the M.S. degree in electrical engineering from Beihang University, Beijing, China in 2012. He is currently working toward the Ph.D. degree in electrical engineering with Hanyang University, Ansan, Korea. His research interests are DC / DC converters and soft switching techniques.
HeeJun Kim received the B.S and M.S. degree in electronics engineering from Hanyang University, Seoul, Korea, in 1976 and 1978, respectively, and the Ph.D. degree in electronics engineering from Kyushu University, Fukuoka, Japan, in 1986. Since 1987, he has been with the department of Electronic Systems Engineering, Hanyang University, Ansan, Korea, where he is currently a professor. His current interests include switching power converters, electronic ballasts, soft switching techniques, and analog signal processing. Dr. Kim is the presidentelect of the Korean Institute of Electrical Engineers (KIEE) and is a senior member of IEEE.
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