This paper presents a new zero voltage switching (ZVS) converter for medium power and high input voltage applications. Three threelevel pulsewidth modulation (PWM) circuits with the same power switches are adopted to clamp the voltage stress of MOSFETs at
V_{in}
/2 and to achieve load current sharing. Thus, the current stresses and power ratings of transformers and power semiconductors at the secondary side are reduced. The resonant inductance and resonant capacitance are resonant at the transition interval such that active switches are turned on at ZVS within a wide range of input voltage and load condition. The seriesconnected transformers are adopted in each threelevel circuit. Each transformer can work as an inductor to smooth the output current or a transformer to achieve the electric isolation and power transfer. Thus, no output inductor is needed at the secondary side. Three centertapped rectifiers connected in parallel are used at the secondary side to achieve load current sharing. Compared with the conventional parallel threelevel converters, the proposed converter has less switch counts. Finally, experiments based on a 1.44kW prototype are provided to verify the operation principle of proposed converter.
1. Introduction
Recently, high efficiency power converters have been developed for the cloud server power units and telecommunication power units. For medium power applications, twostage power conversions (AC/DC+DC/DC) are usually adopted to achieve high power quality and stable DC output voltage. Threephase (380
V_{rms}
or 480
V_{rms}
) AC / DC converters with power factor correction (PFC) are generally used in the front stage to supply a stable and constant DC bus voltage for the rear stage DC/DC converter. Usually, the DC bus voltage of a threephase PFC circuit (380
V_{rms}
or 480
V_{rms}
) is greater than 600V or 800V. Thus, MOSFETs with 500V or 600V voltage stress cannot be adopted in the second stage such as halfbridge and fullbridge circuit topologies. Although high frequency MOSFETs with 900V voltage stress can be used in the rear DC/DC converters to overcome this problem, the high cost and large turnon resistance are the main drawbacks of the high voltage MOSFETs. Threelevel converters/inverters
[1

6]
have been proposed to use low voltage stress of power switches for high voltage applications. The neutral point diode clamp converters, flying clamp converters or series fullbridge converters have been presented to limit the voltage stress of power switches at onehalf of DC bus voltage. In order to increase the circuit efficiency and reduce the power losses, soft switching techniques
[7

15]
such as active clamp technique, asymmetric pulsewidth modulation (PWM) scheme and series resonant technique have been proposed and used in the twolevel PWM converters. For medium power and high input voltage applications, threelevel zero voltage switching (ZVS) converters
[16

19]
have been proposed to have the features of low voltage stress of power semiconductors and high circuit efficiency. In these techniques, the leakage inductance of the transformer (or external inductance) and the output capacitance of power switches are resonant at the transition interval. The drain voltage of MOSFETs can be decreased to zero voltage before the MOSFETs are turned on. For high load current applications such as high power battery charger, parallel threelevel converters are usually used. However, parallel converters require too many power switches and passive components.
A new soft switching threelevel converter with three PWM circuits is presented in this paper. The main features of the proposed converter are ZVS turnon for all switches, and low current stress of rectifier diodes and transformer windings and less power switches to achieve parallel operation. Three PWM circuits with the same power switches are adopted in the proposed converter to achieve parallel operation. The flying capacitor and clamped diodes can limit the voltage stress of power switches at
V_{in}
/2. Three centertapped rectifiers connected in parallel are used at the secondary side to reduce the current rating of rectifier diodes. The seriesconnected two transformers are used in each PWM circuit. One transformer works as a forwardtype transformer to transfer the input power to output load, and the other transformer works as an inductor to smooth the load current. Thus, no output inductor is needed at the secondary side. Compared with the conventional parallel converter with three threelevel PWM circuits, the proposed converter has less switch counts and the current stress of the transformer windings are also decreased. Finally, experiments are provided to demonstrate the performance of the proposed converter.
2. Circuit Configuration
Fig. 1 (a)
gives the conventional parallel threelevel PWM converter for high input voltage and high load current applications. There are twelve power switches, three flying capacitors, six clamped diodes and three power transformers in the primary side. In the secondary side, there are six rectifier diodes and three filter inductors. The drawback of this circuit is too many power components.
Fig. 1(b)
shows the circuit configuration of the proposed ZVS converter.
C_{in1}
and
C_{in2}
are equal and large enough to share the input voltage
v_{Cin1}
=
v_{Cin2}
=
V_{in}
/2. Active switches
S_{1}S_{4}
are MOSFETs with the voltage stresses of
S_{1}S_{4}
are clamped at
V_{in}
/2.
C_{r1}C_{r4}
are output capacitances of
S_{1}S_{4}
, respectively.
C_{f}
is the flying capacitor and its voltage equals
V_{in}
/2.
C_{1}C_{3}
are the DC blocking capacitances with the average voltages
V_{C1,av}
=
V_{C2,av}
=
V_{in}
/2 and
V_{C3,av}
= 0.
L_{r1}L_{r3}
are the resonant inductances.
L_{m1}L_{m6}
are the magnetizing inductances of the transformers
T_{1}T_{6}
, respectively.
D_{a}
and
D_{b}
are the clamped diodes.
D_{1}D_{6}
are the rectifier diodes.
R_{o}
and
C_{o}
denote the load resistance and output capacitance. Phaseshift PWM scheme is adopted to regulate the output voltage.
S_{1}
and
S_{4}
are the leading switches, and
S_{2}
and
S_{3}
are the lagging switches. The PWM signals of
S_{1}
and
S_{4}
are complementary each other with a dead time to allow ZVS operation. Similarly, the PWM signals of
S_{2}
and
S_{3}
are complementary each other. There are three threelevel PWM circuits with the same MOSFETs
S_{1}S_{4}
, the flying capacitor
C_{f}
and the clamped diodes
D_{a}
and
D_{b}
in the proposed converter. The first threelevel ZVS circuit is shown in
Fig. 1(c)
. The components of circuit 1 include
C_{in1}, C_{in2}, D_{a}, D_{b}, C_{f}, S_{1}S_{4}, C_{r1}C_{r4}, C_{1}, L_{r1}, T_{1}, T_{2}, D_{1}
and
D_{2}
. The circuit 2 shown in
Fig. 1(d)
includes the components of
C_{in1}, C_{in2}, D_{a}, D_{b}, C_{f}, S_{1}S_{4}, C_{r1}C_{r4}, C_{2}, L_{r2}, T_{3}, T_{4}, D_{3}
and
D_{4}
and the circuit 3 shown in
Fig. 1(e)
includes
C_{in1}, C_{in2}, D_{a}, D_{b}, C_{f}, S_{1}S_{4}, C_{r1}C_{r4}, C_{3}, L_{r3}, T_{5}, T_{6}, D_{5}
and
D_{6}
. Circuit 1 and circuit 2 are operated by the phase shift of onehalf of switching cycle. Three voltage levels
V_{in}
,
V_{in}
/2 and 0 are generated on the terminal voltages
v_{ab}
and
v_{bc}
. However, another three voltage levels
V_{in}
/2, 0 and 
V_{in}
/2 are generated on the terminal voltage vbd. Since the average capacitor voltages
V_{C1,av}
=
V_{C2,av}
=
V_{in}
/2 and
V_{C3,av}
=0, the voltage levels
V_{in}
/2, 0 and 
V_{in}
/2 are shown on the primary side voltages
v_{p1}v_{p3}
. Two series transformers are used in each circuit to smooth the secondary side current of transformer. Each transformer can work as a transformer to achieve electric isolation and power transfer or as an inductor to smooth output current. Thus, no inductor is needed in the output side. The centertapped rectifier is adopted in the secondary side to obtain a stable output voltage
V_{o}
with one diode conduction loss. For high load current applications, each circuit supplies onethird of the load power such that the current stresses of the transformer secondary windings, rectifier diodes and inductors are reduced.
Circuit topology: (a) conventional parallel threelevel converter; (b) proposed new ZVS threelevel converter; (c) circuit 1; (d) circuit 2; (e) circuit 3.
3. Operation Principle
The key PWM waveforms of the proposed converter are shown in
Fig. 2
. Some assumptions are made to simplify the system analysis of the proposed converter.

(1) Power semiconductors,S1S4, D1D6andDaDb, are ideal.

(2) Transformers are identical (Lm1=..=Lm6=Lm).

(3) Resonant inductances are identicalLr1=Lr2=Lr3=Lr.

(4)Lr＜＜Lm

(5) Input capacitancesCin1andCin2are equal and large enough to be considered as two voltage sourcesVCin1=VCin2=Vin/2.

(6) Switch output capacitancesCr1=Cr2=Cr3=Cr4=Cr.

(7) DC blocking capacitancesC1C3and flying capacitanceCfare large enough to be treated as constant voltagesVC1=VC2=VCf=Vin/2 andVC3=0.

(8) The output voltageVois constant.
Key waveforms of the proposed converter.
Based on the on/off states of active switches
S_{1}S_{4}
and diodes
D_{a}D_{b}
and
D_{1}D_{6}
, there are ten operation modes in the proposed converter in a switching period. The duty cycle of
S_{1}S_{4}
is equal to 0.5. The PWM signals of
S_{2}
and
S_{3}
are phaseshifted with respective to the PWM signals of
S_{1}
and
S_{4}
. The equivalent circuits of ten operation modes of the proposed converter are shown in
Fig. 3
. Prior to time
t_{0}, S_{1}, S_{2}, D_{2}, D_{3}
and
D_{5}
are conducting.
Operation modes of the proposed converter in a switching cycle: (a) mode 1; (b) mode 2; (c) mode 3; (d) mode 4; (e) mode 5; (f) mode 6; (g) mode 7; (h) mode 8; (i) mode 9; (j) mode 10.
Mode 1
[t_{0}≤t＜t_{1}]:
At time
t_{0}
, switch
S_{1}
is turned off. Since
i_{Lr1}
(
t_{0}
)＜0,
i_{Lr2}
(
t_{0}
)＞0 and
i_{Lr3}(t_{0})
＞0, capacitor
C_{r1}
rises from zero voltage and
C_{r4}
decays from
V_{in}
/2 via the flying capacitor
C_{f}
. The rising slope of the draintosource voltage of
S_{1}
(or
v_{Cr1}
) is limited by
C_{r1}
and
C_{r4}
. Thus,
S_{1}
is turned off at ZVS. If the energy stored in
L_{m1}, L_{m4}
and
L_{m6}
is greater than the energy stored in
C_{r1}
and
C_{r4}
, then
C_{r4}
can be discharged to zero voltage. Thus, the ZVS turnon condition of
S_{4}
is expressed as:
At
t_{1}
,
v_{Cr1}
=
V_{in}
/2 and
v_{Cr4}
declines to zero voltage. The time interval of mode 1 is obtained as:
In order to achieve ZVS turnon of
S_{4}
, the time delay
t_{d}
between
S_{1}
and
S_{4}
must be greater than Δ
t_{01}
.
Mode 2 [t_{1}≤t＜t_{2}]:
At time
t_{1}
,
v_{Cr1}
=
V_{in}
/2 and
v_{Cr4}
=0 such that the clamped diode
D_{a}
is conducting. Since
i_{Lr1}
(
t_{1}
) is negative and
i_{Lr2}
(
t_{1}
) and
i_{Lr3}
(
t_{1}
) are positive, the switch current
i_{S4}
is negative and the antiparallel diode of
S_{4}
is conducting. Therefore,
S_{4}
can be turned on at this moment to achieve ZVS. The terminal voltages
v_{ab}
=
v_{bc}
=
V_{in}
/2 and
v_{bd}
=0. Since
V_{C1}
=
V_{C2}
=
V_{in}
/2 and
V_{C3}
=0, the primary side voltages
v_{p1}
=
v_{p2}
=
v_{p3}
=0. Thus, rectifier diodes
D_{1}D_{6}
are all conducting in this mode. The magnetizing voltages are
v_{Lm1 }= v_{Lm3} = v_{Lm5} = nV_{o}
and
v_{Lm2}= v_{Lm4} = v_{Lm6} =nV_{o}
. Diode currents
i_{D1}, i_{D4}
and
i_{D6}
increase, and
i_{D2}, i_{D3}
and
i_{D5}
decrease. If the voltage drop on diode
D_{a}
and switch
S_{2}
are considered in this mode, the slopes of the primary side currents
i_{Lr1}i_{Lr3}
are expressed as:
where
V_{S2,drop}
and
V_{Da,drop}
are the voltage drop on switch
S_{2}
and diode
D_{a}
, respectively. The slopes of the diode currents are given as:
where
n
=
n_{p}
/
n_{s}
is the turns ratio of
T_{1}T_{6}
. If the voltage drop on
S_{2}
and diode
D_{a}
can be neglected, then the primary currents
i_{Lr1}i_{Lr3}
and diode currents
i_{D1}i_{D6}
are unchanged in this mode.
Mode 3 [t_{2}≤t＜t_{3}]:
At time
t_{2}, S_{2}
is turned off. Since
i_{Lr1}
(
t_{2}
) is negative and
i_{Lr2}
(
t_{2}
) and
i_{Lr3}
(
t_{2}
) are positive,
C_{r2}
rises from zero voltage and
C_{r3}
decays from
V_{in}
/2 via
C_{f}.
The rising slope of
v_{Cr2}
is limited by
C_{r2}
and
C_{r3}
. Thus,
S_{2}
is turned off at ZVS. Since the rectifier diodes
D_{1}D_{6}
are still conducting, the magnetizing voltages
v_{Lm1}=v_{Lm3}=v_{Lm5}=nV_{o}
and
v_{Lm2}=v_{Lm4}=v_{Lm6}=−nV_{o}
. If the energy stored in
L_{r1}L_{r3}
is greater than the energy stored in
C_{r2}
and
C_{r3}
, then
C_{r3}
can be discharged to zero voltage. Thus, the ZVS turnon condition of
S_{3}
is given as:
At time
t_{3}
,
v_{Cr3}
declines to zero voltage. The time interval in mode 3 is expressed as:
The time delay
t_{d}
between
S_{2}
and
S_{3}
must be greater than Δ
t_{23}
in order to achieve ZVS turnon of
S_{3}
.
Mode 4 [t_{3}≤t＜t_{4}]:
At time
t_{3}, C_{r3}
is discharged to zero voltage. Since
i_{S3}
(
t_{3}
)=
i_{Lr1}
(
t_{3}
)
−i_{Lr2}
(
t_{3}
)
i_{Lr3}
(
t_{3}
) is negative, the antiparallel diode of
S_{3}
is conducting. Thus,
S_{3}
can be turned on at this moment to achieve ZVS. In this mode, the voltages
v_{ab}=V_{in}
,
v_{bc}
=0,
v_{bd}=−V_{in}
/2,
v_{p1}=V_{in}
/2 and
v_{p2}=v_{p3}=−V_{in}
/2. Since the rectifier diodes
D_{1}D_{6}
are still conducting, the primary side voltages
v_{Lm1}+v_{Lm2}=v_{Lm3}+v_{Lm4}=v_{Lm5}+v_{Lm6}
=0. Thus, the inductor voltages
v_{Lr1}=V_{in}
/2 and
v_{Lr2}=v_{Lr3}=−V_{in}
/2. The slopes of the inductor currents and the diode currents in this mode are given as:
At time
t_{4}
, diode currents
i_{D2}, i_{D3}
and
i_{D5}
are decreased to zero. In this mode, no power is transferred from input voltage source
V_{in}
to output load
R_{o}
. Thus, the duty loss in mode 4 is expressed as:
where
T_{s}
and
f_{s}
are the switching period and switching frequency, respectively.
Mode 5 [t_{4}≤t＜t_{5}]:
At time
t_{4}
, diode currents
i_{D2}
,
i_{D3}
and
i_{D5}
are decreased to zero.
T_{1}, T_{4}
and
T_{6}
are working as the forward type transformers and
T_{2}, T_{3}
and
T_{5}
are working as the inductors to smooth the load current. The voltages
v_{p1}=V_{in}
/2 and
v_{p2}=v_{p3}=−V_{in}
/2 in this mode. Therefore, the primary current
i_{Lr1}
increases with the applied
V_{in}
/2 and
i_{Lr2}
and
i_{Lr3}
decrease with the applied voltage −
V_{in}
/2 in this mode.
Power is delivered from input voltage source
V_{in}
to output load
R_{o}
through
D_{1}, D_{4}
and
D_{6}
in this mode.
Mode 6 [t_{5}≤t＜t_{6}]:
At time
t_{5}
, switch
S_{4}
is turned off. Since
i_{Lr1}
(
t_{5}
) is positive and
i_{Lr2}
(
t_{5}
) and
i_{Lr3}
(
t_{5}
) are negative,
C_{r1}
is discharged and
C_{r4}
is charged via capacitor
C_{f}
. The rising slope of the draintosource voltage of
S_{4}
is limited by
C_{r1}
and
C_{r4}
such that
S_{4}
is turned off at ZVS. If the energy stored in
L_{m2}, L_{m3}
and
L_{m5}
is greater than the energy stored in
C_{r1}
and
C_{r4}
, then
C_{r1}
can be discharged to zero voltage. Thus, the ZVS turnon condition of
S_{1}
is expressed as:
At time
t_{6}
,
v_{Cr1}
=0 and
v_{Cr4}=V_{in}
/2. The time interval in mode 6 is obtained as:
The time delay
t_{d}
between
S_{1}
and
S_{4}
should be greater than time interval Δ
t_{56}
in order to turn on
S_{1}
at ZVS.
Mode 7 [t_{6}≤t＜t_{7}]:
At time
t_{6}
,
v_{Cr1}
=0 and
v_{Cr4}=V_{in}
/2 such that the clamped diode
D_{b}
is conducting. Since
i_{Lr1}
(
t_{6}
) is positive and
i_{Lr2}
(
t_{6}
) and
i_{Lr3}
(
t_{6}
) are negative, the switch current
i_{S1}
is negative and the antiparallel diode of
S_{1}
is conducting. Switch
S_{1}
can be turned on at this moment to achieve ZVS. The AC terminal voltages
v_{ab}=v_{bc}=V_{in}
/2,
v_{bd}
=0 and
v_{Lm1}+v_{Lm2}=v_{Lm3}+v_{Lm4}=v_{Lm5}+v_{Lm6}
=0. Thus, the rectifier diodes
D_{1}D_{6}
are conducting. The slopes of the primary side currents are expressed as:
where
V_{S3,drop}
and
V_{Db,drop}
are the voltage drop on switch
S_{3}
and diode
D_{b}
, respectively. The slopes of the diode currents are given as:
Diode currents
i_{D1}
,
i_{D4}
and
i_{D6}
decrease, and
i_{D2}
,
i_{D3}
and
i_{D5}
increase in this mode.
Mode 8 [t_{7}≤t＜t_{8}]:
At time
t_{7}
, switch
S_{3}
is turned off. In this mode,
C_{r2}
is discharged and
C_{r3}
is charged. Since the rising slope of
v_{Cr3}
is limited by
C_{r2}
and
C_{r3}
,
S_{3}
is turned off at ZVS. Rectifier diodes
D_{1}D_{6}
are still conducting, the magnetizing voltages
v_{Lm1} = v_{Lm3} = v_{Lm5} = nVo
and v
_{Lm2}
= v
_{Lm4}
= v
_{Lm6}
= −nV
_{o}
. If the energy stored in
L_{r1}L_{r3}
is greater than the energy stored in
C_{r2}
and
C_{r3}
, then
C_{r2}
can be discharged to zero voltage. Thus, the ZVS turnon condition of
S_{2}
is given as:
At time
t_{8}
,
v_{Cr2}
=0 and
v_{Cr3}
=
V_{in}
/2. The time interval of mode 8 is expressed as:
The time delay
t_{d}
between
S_{2}
and
S_{3}
must be greater than time interval Δ
t_{78}
in order to turn on
S_{2}
at ZVS.
Mode 9 [t_{8}≤t＜t_{9}]:
At time
t_{8}, C_{r2}
is discharged to zero voltage. Since
i_{S2}
(
t_{8}
)=
i_{Lr2}
(
t_{8}
)+
i_{Lr3}
(
t_{8}
)
i_{Lr1}
(
t_{8}
)＜0, the antiparallel diode of
S_{2}
is conducting.
S_{2}
can be turned on at this moment to achieve ZVS. The AC side voltages
v_{ab}=0
,
v_{bc}=V_{in}
,
v_{bd}=V_{in}
/2,
v_{p1}=−V_{in}
/2 and
v_{p2}=v_{p3}=V_{in}
/2. Since
D_{1}D_{6}
are still conducting and
v_{Lm1}+v_{Lm2}=v_{Lm3}+v_{Lm4}=v_{Lm5}+v_{Lm6}
=0, the inductor voltages
v_{Lr1}=−V_{in}
/2 and
v_{Lr2}=v_{Lr3}=V_{in}
/2. The slopes of the inductor currents and the diode currents in this mode are given as:
At time
t_{9}
, the diode currents
i_{D1}
,
i_{D4}
and
i_{D6}
are decreased to zero. The duty loss of mode 9 is expressed as:
Mode 10 [t_{9}≤t＜t_{0}+T_{s}]:
At time
t_{9}, i_{D1}=i_{D4}=i_{D6}
=0.
T_{2}, T_{3}
and
T_{5}
are working as the forward type transformers and
T_{1}
,
T_{4}
and
T_{6}
are working as the inductors to smooth the load current. The voltages
v_{p1}=−V_{in}
/2 and
v_{p2}=v_{p3}=V_{in}
/2 in this mode. The primary current
i_{Lr1}
decreases and
i_{Lr2}
and
i_{Lr3}
increase in this mode.
This mode ends at
t_{0}+T_{s}
when
S_{1}
is turned off. The circuit operations of the proposed converter in a switching period are completed.
4. Circuit Characteristics
The time intervals in modes 1, 3, 6 and 8 are much less than the time intervals in the other modes. Thus, only modes 2, 4, 5, 7, 9 and 10 are considered in the following discussions. In modes 2 and 7, the average flying capacitor voltage
V_{Cf}
can be obtained as
V_{in}
/2. Based on the voltsecond balance on the primary side of
T_{1}T_{6}
, the average capacitor voltages
V_{C1,av}=V_{C2,av}=V_{in}
/2 and
V_{C3,av}
=0. Applying the voltsecond balance on
L_{m1}
, the output voltage can be expressed as:
where
V_{D}
is the voltage drop on diodes
D_{1}D_{6}
, and
δ
is the duty ratio of the proposed converter when
S_{1}
and
S_{2}
are both in the onstate. If the circuit components are given, then the duty ratio
δ
is related to the input voltage
V_{in}
and the load current
I_{o}
. In steady state, the average diode currents of
D_{1}D_{6}
are equal to
I_{o}
/6. The ripple inductor current
Δi_{Lr1}
in mode 10 can be expressed as:
where
r
is the ripple current ratio of load current. From (19) and (20), the magnetizing inductance
L_{m}
of
T_{1}T_{6}
is given as:
The maximum diode currents
i_{D1,max}i_{D6,max}
are expressed as:
Since the average currents on capacitances
C_{1}C_{3}
are zero, the average magnetizing currents
I_{Lm1}I_{Lm6}
equal zero. In modes 5 and 10, the voltage stresses of
D_{1}D_{6}
are expressed as:
The peak currents, rootmeansquare (rms) currents and voltage stresses of switches
S_{1}S_{4}
are given as:
In mode 10, the inductor currents
i_{Lr1}
(
t_{0}
)
i_{Lr3}
(
t_{0}
) (or
i_{Lr1}
(
T_{s}
+
t_{0}
)
i_{Lr3}
(
T_{s}
+
t_{0}
)) are expressed as:
In mode 2, the inductor currents
i_{Lr1}
(
t_{2}
)
i_{Lr3}
(
t_{2}
) are given as:
Based on (1) and (10), the necessary resonant inductance
L_{r}
to achieve ZVS turnon of
S_{1}
and
S_{4}
is given as:
From (5) and (14), the necessary inductance
L_{r}
to achieve ZVS turnon of
S_{2}
and
S_{3}
is given as:
5. Design Example and Experimental Results
A prototype circuit with the design procedure is provided in this section. The specifications of the prototype circuit are
V_{in}
=550600V,
V_{o}
=24V, and
I_{o}
=60A. The circuit efficiency is assumed to be 90％. The switching frequency is
f_{s}
=100kHz. The maximum duty cycle of
v_{p1}v_{p3}
is equal to 0.5 at the minimum input voltage
V_{in}=550V
and the full load condition. The maximum duty cycle loss in mode 4 or 9 is assumed 10％ under a full load with a duty cycle
δ=0.5
.
From (29), the resonant inductance of
L_{r}
can be obtained as :
Thus, the resonant inductances
L_{r1}L_{r3}
are selected as 40𝜇H in the prototype circuit. If the voltage drop
V_{D}
on diodes
D_{1}D_{6}
can be neglected, the turns ratio of
T_{1}T_{6}
can be given as:
A TDK EER42 magnetic core with
A_{e}
=1.94cm
^{2}
was used to design the transformers
T_{1}T_{6}
. The primary turns of
T_{1}T_{6}
with Δ
B
=0.2T are given as:
The actual primary and secondary winding turns are
n_{p}
=37 and
n_{s}
=9, respectively and the magnetizing inductances of
T_{1}T_{6}
are 520𝜇H. Based on (24), the
rms
currents and voltage stresses of
S_{1}S_{4}
are given as:
The IRFP460 MOSFETs with
V_{DS}
=500V,
I_{D,rms}
=20A,
R_{DS,on}
=0.27Ω and
C_{oss}
=480pF at 25V are used for switches
S_{1}S_{4}
. The average currents and voltage stresses of
D_{1}D_{6}
are given as:
The KCU30A30 fast recovery diode with
V_{RRM}
=300V and
I_{F}
=30A are used as the rectifier diodes
D_{1}D_{6}
. The selected clamped diodes
D_{a}
and
D_{b}
are 30ETH06. The selected DC blocking capacitances, flying capacitance and output capacitance are
C_{a}=C_{b}
=470𝜇F,
C_{f}
=0.2𝜇F,
C_{1}=C_{2}=C_{3}
=0.1𝜇F and
C_{o}
=3000𝜇F. The equivalent output capacitance
C_{r}
at
V_{in}
=600V is given as:
From (27) and (28), it is clear that ZVS load range of
S_{1}
and
S_{4}
is wider than the ZVS range of
S_{2}
and
S_{3}
. Thus, only ZVS load range of
S_{2}
and
S_{3}
is considered in the circuit design. The resonant inductance
L_{r}
is obtained in (30). From (28), the minimum inductance current to achieve ZVS turnon of
S_{2}
and
S_{3}
is given as:
If the riple currents on primary side and voltage drops on switches and rectifier diodes in (26) are neglected to simplfy the system analysis, then the minimum load current to achieve ZVS can be approximately obtained as :
It means that the power switches
S_{1}S_{4}
can be turned on under ZVS from 6.53A load (about 10％ load) to 60A load (100％ load) in the theoretical analysis. However, there are some riple currents on primary sides and voltage drops on switches and rectifier diodes. Thus, the actual ZVS load range is less than the theoretical ZVS load range in this prototype circuit based on
L_{r}
=40𝜇H. If the less resonant inductance is used, i.e.
L_{r}
＜40𝜇H, then there is a less duty loss in modes 4 and 9 in this prototype. Thus, the large turns ratio of
T_{1}T_{6}
is obtained and the primary side rms current is decreased. The conduction loss on power MOSFETs is decreased. However, the ZVS load range is also decreased.
Experimental Results based on a laboratory prototype with the circuit parameters derived in the previous section are provided to verify the theoretical analysis of the proposed converter. The measured waveforms of gate voltages of
S_{1}S_{4}
, primary side voltages
v_{ab}v_{bd}
and primary side currents
i_{Lr1}i_{Lr3}
at low input voltage
V_{in}
=550V and different load conditions are shown in
Fig. 4
. Three voltage levels are generated on
v_{ab}, v_{bc}
and
v_{bd}
. If
S_{1}
and
S_{2}
are in the onstate, the primary side current
i_{Lr1}
decreases and
i_{Lr2}
and
i_{Lr3}
increase. On the other hand,
i_{Lr1}
increases and
i_{Lr2}
and
i_{Lr3}
decrease if
S_{1}
and
S_{2}
are in the offstate. In the same manner,
Fig. 5
gives the measured waveforms of gate voltages, primary side voltages and currents at high input voltage
V_{in}
=600V and different load conditions. From
Figs. 4
and
5
, the phase shift between
S_{1}
and
S_{2}
at
V_{in}
=600V is greater than the phase shift at
V_{in}
=550V. Therefore, primary side voltages
v_{ab}, v_{bc}
and vbd at
V_{in}
=600V have less duty cycle to transfer power from input voltage
V_{in}
to output load
R_{o}
. The measured waveforms of the gate voltage and drain voltage of the leading switch
S_{1}
and the lagging switch
S_{2}
at 25％ load and 100％ load for different input voltages are shown in
Figs. 6
and
7
. It is clear that the leading and lagging switches
S_{1}
and
S_{2}
are both turned on at ZVS from 25％ load to full load. The voltage stress of
S_{1}
and
S_{2}
is equal to
V_{in}
/2. Since the operation behaviors of
S_{3}
and
S_{4}
are identical with respective to
S_{2}
and
S_{1}
, it is clear that
S_{3}
and
S_{4}
realize ZVS turnon from 25％ load to 100％ load.
Figs. 8
and
9
illustrate the experimental waveforms of the DC blocking voltages
v_{C1}v_{C3}
and the flying capacitor voltage
v_{Cf}
at 25％ load and 100％ load for different input voltages. The average capacitor voltages of
v_{C1}
,
v_{C2}
and
v_{Cf}
are equal to
V_{in}
/2 and the average capacitor voltage
v_{C3}
is equal to zero.
Figs. 10
and
11
give the test results of the diode currents at the secondary side for different loads and different input voltage cases. The output currents
i_{D1}+i_{D2}
,
i_{D3}+i_{D4}
and
i_{D5}+i_{D6}
from three PWM circuits are balanced.
Fig. 12
gives the measured circuit efficiencies of the proposed converter and conventional parallel threelevel converter at different input voltages and load conditions. At high input voltage case, there are less conduction losses on power semiconductors such that the measured circuit efficiency at Vin =600V is higher than the efficiency at Vin = 550V case. The proposed converter has less power components compared to the conventional parallel converter such that the measured circuit efficiency in the proposed converter is better than the circuit efficiency in conventional parallel threelevel converter.
Measured results of the gate voltages of S_{1}S_{4}, the primary side voltages and currents at V_{in}=550V full load and (a) 25％ load; (b) full load.
Measured results of the gate voltages of S_{1}S_{4}, the primary side voltages and currents at V_{in}=600V full load and (a) 25％ load; (b) full load.
Measured waveforms of the gate voltage and drain voltage of switches S_{1} and S_{2} at V_{in}=550V and (a) 25％ load (b) full load.
Measured waveforms of the gate voltage and drain voltage of switches S_{1} and S_{2} at V_{in}=600V and (a) 25％ load (b) full load.
Measured waveforms of the DC blocking voltages v_{C1}v_{C3} and the flying capacitor voltage v_{Cf} at V_{in}= 550V and (a) 25％ load (b) full load.
Measured waveforms of the DC blocking voltages v_{C1}v_{C3} and the flying capacitor voltage v_{Cf} at V_{in}=600V and (a) 25％ load; (b) full load.
Measured waveforms of the rectifier diode currents at V_{in}=550V and (a) 25％ load; (b) full load.
Measured waveforms of the rectifier diode currents at V_{in}=600V and (a) 25％ load; (b) full load.
Measured circuit efficiencies of the proposed converter at different input voltages and load conditions.
6. Conclusion
A new threelevel ZVS converter with three PWM circuits sharing the same power switches is presented in this paper. The main advantages of the proposed converter are 1) ZVS turnon for all active switches from 25％ to 100％ load, 2) low voltage stress of MOSFETs with onehalf of input voltage, 3) no output filter inductors using seriesconnected transformers, and 4) low current stress of transformer windings and rectifier diodes using three centertapped circuit topologies. The output voltage is regulated with the phaseshift PWM scheme. The energy stored in the resonant inductance and magnetizing inductance is used to turn on the leading switches at ZVS. However, only the energy stored in the resonant inductance is used to turn on the lagging switches at ZVS. Compared with the conventional parallel threelevel converter, the proposed converter has less switch counts and output filter inductors. The system analysis, operation mode and design considerations of the proposed converter are discussed in detail. Finally, experiments with 1.44
k
W prototype are provided to demonstrate the effectiveness of the proposed converter.
Acknowledgements
This project is supported by the National Science Council of Taiwan under Grant NSC1022221E224022MY3
BIO
BorRen Lin received the B.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and the M.S. and Ph.D. degrees in electrical engineering from the University of Missouri Columbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings  Power Electronics and the Journal of Power Electronics. His main research interests include powerfactor correction, multilevel converters, active power filters, and softswitching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of the Research Excellence Awards in 2004, 2005, 2007 and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, and the IEEEPower Electronics and Drive Systems 2009 Conference.
TungYuan Shiau received his M.S. in Electrical Engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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