This paper presents a simple modified unipolar carrierbased pulsewidth modulation (CBPWM) strategy for the threelevel neutralpointclamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the threelevel NPC VSI includes the maximum and minimum of the threephase sinusoidal reference voltages with zerosequence voltage injection concept. The proposed modified CBPWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in threelevel NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multicarrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CBPWM technique has been verified though computer simulation and experimental results.
1. Introduction
Multilevel converter topologies has recently been increasingly applied in medium and highvoltage, and medium and highpower industrial applications, such as active power filters, static reactive power compensation, adjustablespeed drive, and renewable energy generation, due to advantages of high power rating, high quality output waveforms associated with reduced voltage/current harmonic distortions, low electromagnetic compatibility (EMC) concerns, lower commonmode voltage, lower switching losses, and higher efficiencies when compared to the conventional twolevel voltage source converters
[1

3]
.
Nowadays, there are three generally commercial classified topologies of multilevel converters in the literature as diodeclamped converters
[4
,
5]
, cascaded Hbridge converters
[6

8]
, and flyingcapacitor converters
[9]
,
[10]
. Among the various multilevel converter topologies, the most popular topology in high power industrial applications is the threelevel neutral point clamped (NPC) voltage source inverter (VSI), which was proposed in 1981 by Nabae et al.
[4]
, as shown in
Fig. 1
. One advantage of the threelevel NPC VSI topology is that the power switches and the dclink capacitors have to endure only onehalf of the dclink voltage. As a result, the converter can deal with double voltage and power value than in a standard twolevel VSI with the same switching frequency. However, the drawbacks of this topology are the higher number of power switches, which adds complexity to the modulation method. In addition the voltage balance of the dclink neutral point is required
[5
,
32]
.
In recent year, several modulation strategies for a threelevel NPC VSI have been developed
[11

30]
. They could be mainly classified into carrierbased pulsewidth modulation (CBPWM)
[11

18]
, space vector modulation (SVM)
[19

26]
, and selective harmonic elimination (SHE)
[27

30]
. Among these PWM strategies, the CBPWM has probably been the most popular due to its simplicity of implementation, which based on the comparison between the modulation reference signals and two triangular carriers.
Also, several CBPWM strategies for the threelevel NPC VSI have been extensively researches. The traditional modulation technique for CBPWM is sinusoidal pulsewidth modulation (SPWM). The use of injected zerosequence signals for threephase sinusoidal reference voltages initiated the research on nonsinusoidal CBPWM
[14

16]
. Compared with SPWM, the nonsinusoidal CBPWM strategies can extend the linear modulation ranges make it possible to increase the fundamental of the output voltages. Reference
[12]
presented the CBPWM strategies, which are essentially two modulation modes (unipolar mode and dipolar mode). The application of both modulation modes to threelevel NPC VSI has been equated output voltages. The unipolar mode is the most widely used at threelevel NPC VSI due to the low ripple output voltages and currents. The voltage balancing control capability was improved. In
[15]
, an optimal CBPWM strategy of threelevel NPC VSI was proposed, which analyzed continuous and discontinuous pulsewidth modulation strategies. However, this conventional modified method requires two triangular carriers to generate the gating pulses. A PWM strategy based on carrierbased concept, capable of controlling the locally averaged neutralpoint current to be equal to zero, was presented and analyzed
[17]
, which presented a modified modulation strategy for a threelevel NPC VSI. The minimum and maximum of the sinusoidal threephase reference voltages were added to the output reference voltages obtained from the modified modulation signals. The proposed modulation strategy completely removes the lowfrequency voltage oscillations that appear in the neutralpoint voltage. In addition, this technique can be implemented with a very simple algorithm and processed very fast. Nevertheless, this technique is somewhat complicated for two triangular carriers are required to generate the gating pulses.
An even simple modified CBPWM strategy is proposed. In this paper, the only one triangular carrier is employed for the modulation of threelevel NPC VSI. The practical implementation method of the modified unipolar CBPWM with a triangular carrier wave was proposed strategy in conjunction with a zerosequence voltage injection concept. The switch states of each leg are determined by comparing the modified modulation signals and a triangular carrier wave. The proposed CBPWM strategy has the following advantages:

1) It does not need to know the parameters of the reference voltages;

2) Simplifying the algorithm with no need of complex two/multi triangular carrier or SVM;

3) The fundamental of output voltages are maintain equal dclink voltage due to extend the linear modulation ranges;

4) Ideal for closed loop and during dynamic operation.
The proposed method has been verified by simulation and experimental results for threelevel NPC VSI.
This paper is organized as follows. Section II presents principle of threelevel NPC VSI. Section III details the proposed of the CBPWM strategy. Simulation results are provided in Section IV to verify the good performance of the proposed strategy. Section V describes the experimental results, demonstrating the validity of the proposed method. Finally, conclusions are presented in Section VI.
2. ThreeLevel NeutralPointClamped Voltage Source Inverter and Basic Theory
 2.1 Threelevel NPCVSI configuration
Fig. 1
shows the simplified schematic of the power circuit of the threelevel NPC VSI. It consists of twelve active switches, twelve antiparallelconnected freewheeling diodes, six clamp diodes, and a split dclink with series connected capacitors. For example, the inverter leg
A
is composed of four active switches
S
_{A1}
to
S
_{A4}
with four antiparallelconnected freewheeling diodes
D
_{A1}
to
D
_{A4}
. The diodes connected to the neutral point
Z
,
D
_{ZA1}
to
D
_{ZA2}
, are the clamping diodes. On the dclink side of the inverter, the dclink voltage capacitor is split into two, providing a neutral point.
Simplified schematic of the power circuit of the threelevel neutralpointclamped voltage source inverter.
Switching states and pole voltages of a threelevel neutralpointclamped voltage source inverter
Switching states and pole voltages of a threelevel neutralpointclamped voltage source inverter
 2.2 Switching states
The operating status of the switches in the threelevel NPC VSI can be represented by switching states shown in
Table 1
, where
k
denotes one of the threephase
A, B
, or
C
, and
v_{kZ}
denotes the each output pole voltage. This voltage has possible values, namely
V_{d}
/ 2, 0, and 
V_{d}
/ 2 . The switching state ‘P’ denotes that the each phase two switches,
S
_{k1}
and
S
_{k2}
, are on and the output pole voltage
v_{kZ}
, which is the voltage terminal with respect to the neutral point
Z
, is
V_{d}
/ 2 . The switching state ‘N’ implies that the lower two switches (
S
_{k3}
and
S
_{k4}
) conduct and lead to
v_{kZ}
= 
V_{d}
/2 . The switching state ‘O’ signifies that the inside two switches
S
_{k2}
to
S
_{k3}
are on. The output voltage is clamped to zero through the clamping diodes,
D
_{ZA1}
to
D
_{ZA2}
. It can be observed from
Table I
that two switches of each phase are closed whilst the other two are opened. In other words, switches
S
_{k1}
and
S
_{k3}
operate in a complementary manner. With one switched on, the other must be off. Similarly,
S
_{k2}
and
S
_{k4}
are a complementary pair as well. In each leg, three valid switching states are available to generate three voltage levels on the output pole voltage.
3. Modulation Strategy
The objective of this section is to present the proposed CBPWM strategy, which evaluates performance of the threelevel NPC VSI of
Fig. 1
.
 3.1 Conventional CBPWM strategy
Numerous studies about the CBPWM strategy for the threelevel NPC VSI have been published
[12]
, which assists to understand the proposed method in this paper. From their results, it is widely known that the addition of a zerosequence voltage
selected as (1) to the threephase sinusoidal reference voltages
,
,
in (2) locates the nonzero voltage vectors in the center of a sampling period
[14]

[16]
. It provides an optimum switching sequence by which it has some advantages, such as lower harmonic distortion and higher available modulation index
m_{a}
, compared with the SPWM technique. The zerosequence voltage
can be generated as,
In the traditional modulation method, the threephase reference voltages including the zerosequence voltage
for generated the nonsinusoidal threephase reference voltages
,
,
can be described by,
where the sinusoidal threephase reference voltages,
,
,
, are given by,
where the normalized modulation index
m_{a}
controls the voltage magnitude and has range of 0 to 1.0.
In (3),
ω_{s}
t
is the inverter electrical position which may be related to a desired fundamental frequency
f
_{1}
of output voltages by,
The traditional CBPWM strategy takes the instantaneous average of the maximum and minimum of the threephase reference voltages and adds this value from each of the sinusoidal threephase reference voltages to obtain the modulation waveforms. The addition of this zerosequence voltage continuously centers all of the three reference waveforms in the carrier band, which is like to the CBPWM conventional twolevel VSI. The CBPWM technique can only be used for threephase threewire system, and it enables the modulation index to be increased by 15.5% before overmodulation.
 3.2 Principle of the proposed CBPWM strategy
In the traditional CBPWM strategy, the threephase sinusoidal reference voltages including the zerosequence voltage
for generated the reference voltages of phase leg voltages. The proposed CBPWM strategy is a generalized method that uses the effective threephase sinusoidal reference voltage and the maximum and minimum of the three reference voltages.
The new two variables of modified reference voltage in the proposed CBPWM strategy are obtained through double reference voltages
and
(
k
∈
A, B,C
) for each phase. The modified reference voltages
,
,
are derived as follows:
where
,
,
, are the positive reference voltages and
,
,
are the negative reference voltages of the modified reference voltage
, respectively.
The positive reference voltages take the minimum of the threereference voltages and subtract this value from each of the threephase sinusoidal reference voltages, which can be expressed as,
Similar to (6), the negative reference voltages takes the maximum of the threereference voltages and subtract this value from each of the threephase sinusoidal reference voltages is given as,
where sign function (sgn) is defined by +1 or 1, and δ ∈ {0,1}.
Combining (6) and (7), the modified reference voltages,
,
,
within the maximum and minimum of the three reference voltages, is calculated as,
 3.3 Output voltages synthesis
The main proposes of a CBPWMs strategy of a threelevel NPC VSI are to synthesize the desired output voltages and to verify the modified duty cycles. The output pole voltages
v_{kZ}
, which is the voltage at terminal
k
with respect to the neutral point Z of
Fig. 1
, can be expressed as,
where
V_{d}
is the dclink voltage.
Form the above equation, these output pole voltages
v_{AZ}
,
v_{BZ}
,
v_{CZ}
are determined by the modified reference voltages
,
,
, directly. In the linear modulation index range, if the peak value of the linetoline voltage is
. Therefore, the instantaneous value of the output linetoline voltages
v_{AB}
,
v_{BC}
,
v_{CA}
can be expressed as,
In the linear modulation range in (10), the output linetoline voltages are equal to or less than dclink voltage
V_{d}
. Therefore, if a threephase balanced voltage is to be synthesized using CBPWM scheme describe above. The modulation index is defined as,
where
the fundamental of output pole voltage (peak value), and the possible the modulation index in the linear range can be increased beyond
m_{a}
= 1 the maximum modulation
m_{a}
= 1.15 before overmodulating.
Considering the inverter circuit shown in
Fig.1
, it can be seen that if the load is starconnected, the linetoline voltages do not clearly define the respective output phase voltages
v_{An}
,
v_{Bn}
,
v_{Cn}
may be expressed in terms of the phasetoground voltages by,
where
v_{nZ}
is the voltage between the neutral point of the load
n
and the neutral point of the dclink capacitor
Z
, which can be calculated as,
 3.4 Calculation of duty cycles
basic idea of this proposed CBPWM strategy only requires the calculation of the independent duty cycles, which is to consider the output phase voltage in terms of the modified duty cycles
d_{A}
,
d_{B}
,
d_{C}
may be described by,
Proposed modified CBPWM scheme for threelevel neutralpointclamped voltage source inverter.
where
d_{AP}
,
d_{BP},
d_{CP}
are positive duty cycles, and
d_{AN}
,
d_{BN}
,
d_{CN}
are negative duty cycles of the modified duty cycles.
From above expressions, the equations show the relationships between effective duty cycles and output pole voltages. Commanded voltages are obtained by first defining a threephase set of duty cycles which will be offset so that they range from 0100%. By solving (14), the modified duty cycles for output pole voltage, that is to divide the dclink voltage, can be described as,
where
d_{kP}
,
d_{kN}
are the modified upper and lower duty cycles, respectively.
The modified duty cycles defined by (15) can be compared to a set of single triangular carrier wave in order to produce a generalized switching state for the additional leg. Therefore, the algorithm can be simply implemented with a triangular carrier and the duty cycles calculation as shown in block diagram of
Fig. 2
.
The modified duty cycles of the proposed CBPWM strategy are given in
Fig. 3
. In
Fig. 3 (a)
, the original sinusoidal modulation signals
,
,
are used to generate the modified duty cycles in the proposed method.
Fig. 3 (b)
shows the modified duty cycle waveforms
d_{AP}
and
d_{AN}
for leg
A
obtained from application of (6) and (7) to a sinusoidal set of balanced modulation signals, which a line period,
m_{a}
= 1.0, sgn = +1, and
δ
= +1. The duty cycles for phase
B
and
C
are the same but phase shifted by ± 2
π
/ 3 . From these figures, it can be shown that the waveforms of the modified duty cycles in phase
A
comparative with single triangular wave, which are in the range 0 to 1. The expression for modified duty cycle
d_{AN}
is the same as
d_{AP}
but inverted and phase shifted of
π
radian.
The modified duty cycles for leg A of the proposed CBPWM strategy under the condition of m_{a} = 1.0, sgn = +1, and δ = +1.
The modified duty cycles for leg A of the conventional CBPWM strategies (a) Conventional CBPWM 1: m_{a} = 1.0, sgn = +1, and δ = 0 (b) Conventional CBPWM 2: m_{a} = 1.0, sgn = 1, and δ = 0.
For comparative purposes, the simulated duty cycles of conventional CBPWM strategies for threelevel NPC VSI are illustrated in
Figs. 4 (a)
and
(b)
, which developed in
[17]
and
[18]
, respectively.
Fig. 4 (a)
shows the simulation duty cycles of conventional CBPWM 1 for leg
A
in the case that
m_{a}
= 1.0, sgn = +1, and
δ
= 0 From this result, it can be seen that the comparison of the duty cycles with two carriers, which consist of the upper and lower carriers (
v_{cr1}
and
v_{cr2}
). The positive signals will be compared to the upper carrier wave
v_{cr1}
, while the negative signal will be compared with the lower carrier wave
v_{cr2}
. In the same way, the upper duty cycles for double signals of conventional CBPWM 2 with
m_{a}
= 1.0, sgn = 1, and
δ
= 0 are illustrated in
Fig. 4 (b)
. The results indicate that the duty cycle
d_{AP}
is the same
d_{AN}
but phase shifted of π radian. This method can also be implemented by using upper duty cycles but two phase shift carrier waves (
v_{cr1}
and
v_{cr2}
). The two carrier waves are the same amplitude and frequency, but out of phase.
From the simulation duty cycles in
Figs. 3 (b)
and
Fig. 4
, all CBPWM strategies give the same results for the output voltages, which are good performance. However, the proposed method is simple and easy to implementation due to the modified duty cycles utilized only single of the triangular carrier wave for generates the gating pulse in threelevel NPC VSI.
Block diagram of the neutralpoint voltage control for proposed modified CBPWM scheme.
The neutralpoint voltage control algorithm for proposed modified CBPWM scheme,k∈ {A, B,C}
The neutralpoint voltage control algorithm for proposed modified CBPWM scheme, k ∈ {A, B,C}
One of the essential problems of the threelevel NPC VSI is the neutralpoint voltage balancing. The improved neutralpoint voltage unbalance by neutralpoint voltage control algorithm is used to solve a problem associated in
[24]
. The block diagram of the controller is given in
Fig. 5
. The neutralpoint voltage unbalanced can be controlled by changing the offset voltage (
d_{offset}
) which is generated by the PI controller
[31]
. The neutralpoint voltage control algorithm for proposed modified CBPWM can be formulated as shown in
Table 2.
The control algorithm is achieved by applying the magnitude of the offset voltage to the modified duty cycles of each phase (
d_{kP,} d_{kN}
), which is generated the duty cycles (
d'_{kP} ,d'_{kN}
).
4. Simulation Results
In this section, some simulation results of the proposed method are presented. The modeling of the threelevel NPC VSI using the proposed CBPWM strategy has been implemented in Matlab/Simulink. The general conditions for the simulations are given as follows: the dclink voltage
V_{d}
= 550 V and the dclink capacitors
C
_{d1}
,
C
_{d2}
=4700
μ
F, and the fundamental frequency
f
_{1}
=50 Hz. The threelevel NPC VSI feeds a 4pole wyeconnected induction motor, with nominal values of 1 kW, 1500 r/min, 220/380 V, 50 Hz.
Simulation waveforms for leg A (a) the modified duty cycles d_{AP} and d_{AN} (b) gating pulses v_{SA1} − v_{SA4} .
Simulation waveforms of dynamic response operation for a ramp modulation index reference (a) linetoline voltage v_{AB} (b) modulation index m_{a}.
For example,
Fig. 6
shows the proposed CBPWM strategy for the application of a threelevel NPC VSI.
Fig. 6 (a)
shows the simulated waveforms in leg
A
with modified duty cycles under the condition of the modulation index
m_{a}
= 1.0 and the low switching frequency
f_{s}
= 550 Hz. In the proposed CBPWM strategy, only one of triangular carrier wave
v_{cr}
is used to generate the gating pulses
v
_{SA1}
−
v
_{SA4}
, for power switches
S
_{A1}
and
S
_{A4}
, which are generated by comparing the modified duty cycle waveforms
d_{AP}
and
d_{AN}
with the triangular carrier wave
v_{cr}
. The logic of gating pulses for power switches is very simple as follows: if
d_{AP}
>
v_{cr}
⇒
S
_{A1}
=
ON
,
S
_{A3}
=
OFF
and if
d_{AN}
>
v_{cr}
⇒
S
_{A2}
=
ON
,
S
_{A4}
=
OFF
. Since the inner gating pulses
S
_{A3}
and
S
_{A4}
operate are complementary with
S
_{A1}
and
S
_{A2}
, respectively.
The proposed CBPWM strategy, operating in dynamic response, the output voltages of the threelevel NPC VSI system are controlled by adjusting the modulation index
m_{a}
.
Fig. 7 (a)
illustrates the dynamic response for a ramp output linetoline voltage
v_{AB}
. The modulation index reference increases starting from zero to maximum value (0 to 1.15) for the linear operation mode in 500 ms, with a switching frequency of 2.5 kHz, as shown in
Fig. 7 (b)
. As can be seen from simulated waveform, the linetoline voltage has five voltage levels at high modulation index and three voltage levels at low modulation index and the result proves that smooth output voltage can be obtained over the whole range of operation.
The output voltage and current waveforms are given in
Fig. 8
and
Fig. 9
with both high (
m_{a}
= 0.8) and low modulation and low modulation (
m_{a}
= 0.5) indexes in steadystate conditions. Fig. 8 shows the simulated output voltage and current waveforms of the threelevel NPC VSI in high modulation index, at a switching frequency of 2.5 kHz. The pole voltage, linetoline voltage and phase currents
i_{A}, i_{B}, i_{C}
of the inverter are illustrated in
Fig. 8 (a)

(c)
, respectively. This is three voltage levels on the pole voltage
v_{AZ}
and the five voltage levels on the linetoline voltage
v_{AB}
at high modulation indexes. The simulated waveforms agree with the theoretical analysis. The feasibility of the proposed CBPWM method and the good quality of the voltage and control signals are verified. It can be seen that the voltages are well balanced in the steadystate operation, while the output phase currents are balanced and almost sinusoidal even fundamental frequency switching under high modulation indexes.
Simulation waveforms at high modulation index, m_{a} =0.8 (a) pole voltage v_{AZ} , (b) linetoline voltage v_{AB} (c) phase currents i_{A} i_{B} i_{C} .
Simulation waveforms at high modulation index, m_{a} =0.5 (a) pole voltage v_{AZ} , (b) linetoline voltage v_{AB} (c) phase currents i_{A} i_{B} i_{C} .
As the low modulation index, the output voltages and currents of the threelevel NPC VSI are illustrated in
Fig. 8
. Three voltage levels are generated on the output pole voltage
v_{AZ}
, and three voltage levels are achieved on the linetoline voltage
v_{AB}
, as shown in
Figs. 9 (a)
and
(b)
, respectively. In
Fig. 9 (c)
, the phase currents shown are high quality sinusoids and are well balanced despite the openloop nature of the proposed method algorithm.
The total harmonic distortion (THD) for linetoline voltages of threelevel NPC VSI with both high and low modulation indices are about 43.40% and 58.09%, respectively, as simulated by MATLAB/Simulink. In
Fig. 10 (a)
and
(b)
, the output linetoline voltage harmonics around the switching frequency for the threelevel NPC VSI are 379.6 V and 237.6 V at high and low modulation indexes, respectively. As all simulation results, it can be seen that the proposed CBPWM is good of a threelevel NPC VSI and the voltage balance of the dclink is controlled fairly well in the whole modulation index range of the steadystate operation, even though the proposed CBPWM method is simple in its structure.
Simulation harmonic spectrum of linetoline voltage v_{AB} with proposed CBPWM strategy (a) m_{a} = 0.8 (b) m_{a} = 0.5.
5. Experimental Results
The experimental setup of the proposed CBPWM strategy for the threelevel NPC VSI is represented by the block diagram shown in
Fig. 11
. It consists of a dSPACE DS1104 controller board with TMS320F240 slave processor, I/O interface board CP1104, a 1 kW fourpole induction motor. A prototype induction motor drive with a frontend threephase diode bridge rectifier and threelevel NPC VSI was built in the laboratory. The setup parameters are the same as those used for the simulation. The inverter output is connected to an induction motor using a standard constant openloop control method. The machine was unloaded, operating at 50 Hz.
Fig. 12
shows measured waveforms of duty cycles and gating pulse for power switches.
Fig. 12 (a)
shows the duty cycles
d_{AP}
and
d_{AN}
of the conventional CBPWM 2 at the modulation index
m_{a}
= 0.8. It can be seen that the upper duty cycles for double signals, which indicate that the duty cycle
d_{AP}
is the same as
d_{AN}
but the phase is shifted of
π
radian. This conventional method requires two triangular carriers to generate the gating pulses.
Fig. 12 (b)
shows the proposed modified duty cycles
d_{AP}
and
d_{AN}
for leg
A
at the modulation index
m_{a}
= 0.8, which use only one of triangular carrier wave for generate the gating pulses. It can be seen that the experiments resemble the simulation results. The gating pulses of the power switches for leg
A
in the threelevel NPC VSI can be represented in
Fig. 12 (c)
, which generated by the proposed CBPWM strategy. It shows an example of gating pulse arrangements, where
v
_{SA1}
to
v
_{SA4}
be the gating pulses for power switches
S
_{A1}
to
S
_{A4}
, respectively.
Fig. 13
shows the experimental waveforms of the dynamic response operation for a ramp modulation index reference, which increases from zero to the maximum modulation index (
m_{a}
= 1.15). It can be seen that the output linetoline voltage waveform proves that smooth output voltage for the linear operation. Therefore, the low modulation index becomes limited to a value which is equal to 0.57.
Experimental setup.
The inverter voltage and current waveforms in steadystate are shown in
Fig. 14
for high and low modulation indices. It can be seen that from both figures there is good agreement between simulations and experiments, which obtained in the conditions of
Figs. 8
and
Fig. 9
.
Fig. 14 (a)
shows the steadystate waveforms of the pole voltage
v_{AZ}
, linetoline voltage
v_{AB}
, and output phase currents ,
i_{A}, i_{C}
when the inverter operates at the modulation index
m_{a}
= 0.8. The linetoline voltage of the inverter under steadystate operation generated by the fivelevel inverter can be clearly appreciated in the voltage waveform.
Experiment waveforms for leg A : (a) the conventional CBPWM 2 duty cycles d_{AP} and d_{AN} (Scale: 2 V/div), (b) the proposed modified CBPWM duty cycles d_{AP} and d_{AN} (Scale: 2 V/div), and (c) the proposed modified CBPWM gating pulses for power switches v_{SA1} , v_{SA2} , v_{SA3} , and v_{SA4} (Scale: 20 V/div).
Similarly,
Fig. 14 (b)
also show voltage and current waveforms of the proposed method can be applied for low modulation index,
m_{a}
= 0.5. From these results, it can be shown that the linetoline voltage
v_{AB}
of the inverter under steadystate operation is generated by the threelevel voltage and has a amplitude of
V_{d}
/ 2 . The linetoline voltage is identical to that of a conventional twolevel inverter. The closely match of simulation and experimental results well verify the feasibility and validity of the proposed strategy. In addition, from both simulation and experimental results, it can be seen that the voltage waveforms generated by the proposed CBPWM strategy are stable in the steadystate condition.
Experimental waveforms of dynamic response operation for a ramp modulation index reference (a) linetoline voltage v_{AB} (Scale: 250 V/div), (b) modulation index m_{a} (Scale: 5 V/div).
Experiment waveforms of the proposed modified CBPWM: pole voltage v_{AZ} (Scale: 500 V/div), linetoline voltage v_{AB} (Scale: 250 V/div), and output phase currents i_{A}, i_{C} at no load (Scale: 1.5 A/div) (a) modulation index m_{a} = 0.8 (b) modulation index m_{a} = 0.5.
Fig. 15
shows the steadystate voltage and current waveforms of the conventional CBPWM 2 for high and low modulation indices. It can be seen from both figures that there is good agreement and the experimental results of the proposed method in
Fig. 14
are close to conventional CBPWM 2. Again, the conventional method requires two triangular carriers for generate the gating pulses, which is a complex implementation.
Fig. 16
shows the harmonic spectrum of the linetoline voltages of threelevel NPC VSI using the proposed CBPWM strategy with a switching frequency
f_{s}
= 2.5 kHz. The fundamental output linetoline voltage under the condition of
m_{a}
= 0.8 and 0.5 had a value of 384.5 V and 238.9 V, respectively. The THD was showed from 46.13% in the high modulation index and 58.88% in the low modulation index. Experimental results and simulated ones presented in
Fig.16
and
Fig. 10
are in close agreement. Furthermore, in order to verify the proposed CBPWM strategy for threelevel NPC VSI by the simulation results and compared with experimental results, as shown in
Table 3
. It can be observed that the differences of the output voltage and THD for linetoline voltages between simulation and experimental are a very good agreement the whole modulation index ranges (0.11.15) and their corresponding the graph in
Fig. 17
.
Experiment waveforms of the conventional CBPWM 2: pole voltage v_{AZ} (Scale: 500 V/div), lineto line voltage v_{AB} (Scale: 250 V/div), and output phase currents i_{A}, i_{C} at no load (Scale: 1.5 A/div) (a) modulation index m_{a} = 0.8 (b) modulation index m_{a} = 0.5.
Experimental harmonic spectrum of linetoline voltage with proposed CBPWM strategy (a) m_{a} = 0.8 (b) m_{a} = 0.5.
The output voltage and THD for linetoline voltages between simulation and experimental results under various modulation index.
The output voltage and THD for linetoline voltages between simulation and experimental results under various modulation index.
Fig. 17
summarizes the comparison results of the linetoline voltage total harmonic distortion for the conventional and proposed CBPWM strategies. The THD is evaluated in the whole linear modulation index ranges (0.11.15) with incremental step size of 0.1 under 2.5 kHz switching frequency condition. It can be seen that the experimental results of the proposed method are close to conventional CBPWM strategies (CBPWM 1 and CBPWM 2). In the all experimental, the output linetoline voltages THD between the proposed and other conventional CBPWM strategies are almost no difference values. However, the advantage of the proposed method can be implemented easily than other conventional strategies because it is used only one of the triangular carrier wave for generating the gating pulses in the threelevel NPC VSI.
THD for the output linetoline voltages with modulation index of the threelevel NPC VSI for different CBPWM strategies.
6. Conclusion
This paper presented a novel CBPWM strategy for the threelevel NPC VSI. The novelty of the proposed CBPWM strategy is that only single of the triangular carrier wave is employed to for generate the gating pulses in the threelevel NPC VSI and significantly simplify the modulation strategy. Experimental results confirmed the good performance with quality to the output voltages and the almost sinusoidal output phase currents in the dynamic and steadystate operations under high and low modulation indices. The feasibility and reliability of the proposed modulation strategy has been verified by both computer simulation and experimental results on an induction motor drive system. Finally, the main advantages associated were simple PWM algorithm, reduce capacitor voltage ripple, lower switching frequencies, and easily hardware implemented.
Acknowledgements
The work was supported by the Thailand Research Fund (TRF) through the Royal Golden Jubilee Ph.D. Program and National Research University (NRU) Project from Office of the Higher Education Commission of Thailand.
BIO
Watcharin Srirattanawichaikul received the B.Eng degree in electrical engineering (First class honors) from King Mongkut’s Institute of Technology Ladkrabang, Bangkok, Thailand, in 2006 and the M.Eng. degree in Electrical Engineering from Chiang Mai University, Chiang Mai, Thailand, in 2008. He is currently working toward his Ph.D. at Chiang Mai University. His research interests include power electronics, energy conversion systems, and electric drives.
Suttichai Premrudeepreechacharn received the B.Eng. degree in electrical engineering from Chiang Mai University, Chiang Mai, Thailand, in 1988 and the M.S. and Ph.D. degrees in electric power engineering from Rensselaer Polytechnic Institute, Troy, New York, USA, in 1992 and 1997, respectively. Since 2002, he has been an Associate Professor with the Department of Electrical Engineering, Faculty of Engineering, Chiang Mai University. His research interests include power quality, highquality utility interfaces, power electronics, and artificialintelligenceapplied power systems.
Yuttana Kumsuwan received the M.Eng. degree in electrical engineering from King Mongkut’s Institute of Technology Ladkrabang, Bangkok, Thailand, in 2000 and the Ph.D. degrees in electrical engineering from Chiang Mai University, Chiang Mai, Thailand, in 2007. Since 2011, he has been an Assistant Professor in the Department of Electrical Engineering, Faculty of Engineering, Chiang Mai University. He was a visiting professor at the Texas A&M University, College Station, United States, from October 2007 to May 2008, and at Ryerson University, Toronto, ON, Canada in March to May 2010. His research interests include power electronics, energy conversion systems, and electric drives.
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