2
): By the control signal, the switch S
1
and S
2
is turned off, and then resonance current by the energy accumulated in the resonance tank charges C
1
and C
2
, discharging C
3
and C
4
with freewheeling. This time, the voltage across the switches gradually increases as shown in the following Eq. 6.
Where,
In this mode, unless the lossless snubber capacitor is completely discharged, the turn on loss occurs in the subsequent switching period. Thus, MODE 3 should be maintained in order for the lossless snubber capacitor to be completely discharged, The time period is calculated by using the following Eq. 7.
If the lossless snubber capacitor has quite a large value, the voltage across the switch in the turn off period approaches to zero, and the turn off loss of the switch is reduced.
In this mode, resonance current as shown in the Eq. 8. is delivered to load, gradually reducing. After this, the series resonant capacitor voltage is calculated by the following Eq. 9.
Where,
,
B
=
C
1,2
(
Cr
−
C
1,2
)
CrLr
,
iLr
(
t
1
) =
I
Lr2
,
Vcr
(
t
1
) =
V
cr2
MODE 4
(M4, t
2
≤ t < t
3
): Once the lossless snubber capacitor C
1
and C
2
are fully charged, resonance current flows through body diode D
3
and D
4
. The voltage and the current across the switch S
3
and S
4
are almost zero, possible for S
3
and S
4
to ZVZC turn on. The resonance current and the series resonant capacitor voltage are the following Eq. 10. and 11.
Where,
There is the same analysis for MODE 5 to MODE 8, the equation can be elicited by the aforementioned procedure.
3. Design of the Proposed Converter for EV Fast Charger
To examine whether the proposed converter appropriate for EV fast charger, designing EV fast charger with the high efficiency of 60kW rating is encouraged. The intended EV fast charger enables charging voltage to change from 50V to 500V so that a variety of batteries aimed at full speed EV and NEV (Neighborhood Electric Vehicle) can be charged up to SOC (State of Charge) 80% within 30 minutes. In this section, the considerations for designing the proposed converter with the highly effective EV fast charger, and the proposal of PSpice model for the validity of designing the proposed converter will be discussed.
Fig. 5
. illustrates the whole structure of 60kW EV fast charger, comprised of circuit breaker, the soft start part to prevent inrush current, rectifying section, the PFC part for power factor correction and reducing the ripple of DC voltage, the converter module part which connects the six proposed 10kW converter in parallel, and the control part for stable output and converter protection
Overall structure of 60kW EV fast charger
The design rules for proposed converter can be summarized as follows.
-
1) The EV Fast Charger is mostly operated at rated charging current to reduce the charging time. Therefore, the efficiency at rated operation is the most important thumb of design rules for designing the proposed converter.
-
2) For the battery charging, both of charging current control and charging voltage control should be considered. The converter topology such as seriesparallel resonant converter which has both voltage and current source characteristics is suitable for the EV Fast Charger.
-
3) The EV Fast Charger should be operated for charging various types of batteries which were installed at various EV with different charging voltage. From the above reason, it is needed for converter design to consider the wide range of output voltage for various kinds of EV battery charging.
- 3.1 Design of 10kW LCC-SRC
The procedures for designing the parameter of the 10kW proposed converter are as follows. First, depending on frequency tolerance of switching elements, switching frequency is determined, and then resonance frequency is decided. After that, based on the energy accumulated in the resonant inductor, the value of parallel resonant capacitor is chosen and the value of series resonant capacitor and resonant inductor is calculated. Finally, through the parameter that is determined in the previous procedure, the value of lossless snubber capacitor is decided. The following is under consideration of designing.
Switching Frequency and Resonant Frequency: To avoid audible noise, the minimum of switching frequency should be beyond the range of audio frequency, and the maximum of switching frequency should not exceed the maximum frequency tolerance of switching device as well as the frequency of the converter’s minimum operating point. Since the proposed converter operates in the range of CCM, resonance frequency should be decided below the range of switching frequency, and the range of switching frequency should be designed to operate within the linear interval of character impedance so that the control of output voltage can be facilitated.
Parallel Resonant Capacitor: To reduce conduction loss with enhanced Crest factors, parallel resonant capacitor should be designed with the value as small as possible. However, due to decreasing parallel resonant capacitor, flowing current of resonant inductor decreases, and in turn energy stored in the inductor is decreased. In this way, since it is impossible to discharge lossless snubber capacitor, the conditions of ZVZCS cannot be met. Therefore, the value of parallel resonant capacitor should be minimized within the ZVZCS range.
To determine the optimal value of parallel resonance capacitor,
Fig. 6(a)
. is the waveform of resonance current simulation that analyzes a variety of values by changing the value of parallel capacitor for the proposed converter based on the criteria of the conventional CCM SRC. Each comparative converter is designed to equalize the output condition (500V 20A) and turn-off loss to each other.
Fig. 6(b)
. is the waveform that compares each converter’s conduction loss, showing that conduction loss is decreased as the value of parallel resonant capacitor decreases.
Comparison of waveform based on the parallel resonant capacitor changes
From the simulated IGBT loss comparison depicted in
Fig.6.(b)
, it is clear that the proposed converter has less loss compared to the conventional resonant converter. Also, the efficiency of the proposed converter was measured as 98.5%. Compare to 96.5% of the conventional CCM SRC which was designed to have maximum efficiency at rated operation, the advantage of the proposed converter was verified and the strength of the proposed converter as the EV Fast Charger was confirmed. However, it should be noted that the proposed converter has less efficiency at light load condition due to the relative circulating energy.
Series Resonant tank: Once parallel resonant capacitor is determined, series resonant capacitor should be designed not to change the characteristics of SRC current source. The value of series resonant capacitor should be designed 10 to 15 times more than the value of parallel resonant capacitor. After deciding the value of resonance frequency, character impedance, and series and parallel resonance capacitor, the value of resonant inductor can be calculated. At this point, the value of character impedance is calculated based on the capacity of the converter and the maximum value of load current.
Lossless snubber capacitor: The value of lossless snubber capacitor should be designed as the maximum value that allows lossless snubber capacitor to be fully discharged within the freewheeling time of resonant current after switch is turned off.
Fig. 7
. compares switching loss by changing the value of lossless snubber capacitor from the maximum value for the conventional CCM SRC with the same output condition to the maximum value for the proposed converter. In
Fig. 7
, turn off loss can be decreased to almost zero.
Comparison of switch loss based on the lossless snubber capacitor changes (Time : 1us/div. Switch loss, 0.1W/div.)
- 3.2 Design of the gate driver circuit for proposed converter
The conventional gate driver that has fixed dead time is difficult to apply to the proposed converter because the proposed converter operates with soft switching within wide load range. This paper proposes the gate driver that has variable dead time and simple structures by detecting the voltage across switching devices and determining when to turn on. The proposed gate driver does not need two opposite control signal with dead time, while it uses a single control signal with half duty that only has operating frequency. As the control signal is simplified, it facilitates the use of a transformer for isolation and photoelectric elements, having a competitive advantage in digitalization. To analyze the operating principle of the proposed gate driver, four different modes will be explained as shown in
Fig. 8
. In case of the gate driver circuit which has variable dead time for detecting zero voltage, there is a problem in which the main switch fails to turn on since the voltage across main switches does not meet the condition of zero voltage under light loading or at soft start. To solve this problem, the normal operation of the converter should be guaranteed by setting the maximum dead time and forcefully turning on, even if this could not fulfill the requirement for zero voltage on time. In the Dead Time Mode, when turn on control signal is applied in the input of the gate driver circuit, capacitor C
1
starts to be charged while the main switch does not turn on because current flows through C
1
, R
1
, and R
4
(more resistance compared to R2) of the secondary transformer. If the electric potential of the main switch IGBT Collector-Emitter approaches zero before C
1
voltage being charged to V
th
(turn on threshold Voltage of P-Channel MOSFET), current flows through C
1
, R
1
, R
2
(less resistance compared to R
4
), and the voltage of capacitor C1 is rapidly charged up to V
th
, turning on the main switch as Zero Voltage Detection Mode in
Fig. 9
. Finally, if the zero voltage condition is met before the determined maximum dead time ends, the main switch turns on in operation. During C
1
is being charged in Dead Time Mode, although zero voltage is not detected, the charging voltage of C
1
becomes V
th
. At this time, the current of the gate driver circuit turns on IGBT, the element of the main switch, through MOSFET and R
3
. Capacitor C
1
can set the time of being charged to V
th
as the maximum dead time of the main switch (IGBT), determining the value of the gate driver circuit R
1
, R
4
, and C
1
to meet the following equation.
Mode analysis of proposed gate driver circuit
PSpice model of proposed 10kW converter module
Where,
Vth
: Gate-source turn on voltage of MOSFET,
Vin
: Gate-driver input voltage
In the Turn Off Mode, the turn off control signal is applied in the gate driver input in order to turn off the main switch. In turn, current flows through R
6
of the secondary transformer and the body diode of MOSFET, and the main switch turns off. Also, the current flowing through R
5
and D2 discharges C
1
, resetting the Dead Time Mode operation for the next period.
- 3.3 Simulation of proposed converter
To identify the operation of the proposed converter and the validity of designing the proposed converter, the simulation for 10kW enhanced CCM SRC using PSpice was performed. The converter used for the simulation was designed by the procedures mentioned before, and the parameter of the designed converter is shown as
Tab.1
. The utilized PSpice model was simulated under consideration of the forward voltage drop and on-state resistance of the switch and the diode device, saturation and loss of the transformer for the converter circuit including the proposed gate drive as shown in
Fig. 9
.
Fig. 10(a)
. is the waveform of output voltage, output current, resonant current and switching signal under 10kW maximum output with 400V, 25A condition, which the validity of the designed converter parameter can be analyzed. In this figure, the waveform of resonant current in rated current, as discussed earlier, has a trapezoidal form, which significantly reduces conduction loss.
Fig. 10(b)
. is the waveform showing switching device current and voltage, and meeting turn on ZVZCS condition. Also, turn off loss becomes almost zero influenced by the lossless snubber capacitor.
Fig. 11
. shows the change of output current depending on switching frequency in order to analyze the converter’s control performance under different loading conditions. As shown in
Fig. 11
., where the relation between output current and switching frequency is linear, controlling the output of the converter is facilitated.
Summary of Design Parameters for the 10kW Converter Module
Summary of Design Parameters for the 10kW Converter Module
Simulation results of 10kW proposed converter module
Simulation result of output current vs. switching frequency for load change
4. Experimental Results
Applying the converter design parameter examined through the simulation, 60kW EV Fast Charger was implemented with six 10kW converter modules.
Tab. 2
. and
Fig. 12
. are the specification and the actual outer shape of 20kW block comprised of two 10kW converter modules.
Fig. 13(a)
. is the experiment scene in which 320V 20kWh LiFePo4 battery is charged with 60kW EV Fast Charger that was implemented with three 20kW converter blocks in parallel.
Fig. 13(b)
. is the experimental setup with variable resistive load for simulating the battery of 400V and 500V condition. To test the operation character and performance, experiments for maximum output, output variation, actual loading, and efficiency measure were performed with regard to 10kW converter module and 60kW fast charger by utilizing simulated test resistive load and a various kinds of batteries.
Fig. 14
. is the experiment waveform that shows output voltage, output current, resonant current, and switching signal when 10kW converter modules operate in the maximum rated output. The efficiency was measured as 98.5%, and as shown in
Fig. 15
. The high efficiency was maintained under various output conditions. To prove that it is possible to install the massive capacity EV fast charger in the form of parallel combination of the converter module, six converter modules connected in parallel with 60kW fast charger were experimented.
Fig. 16
is the experiment waveform that confirms steady state operation under 60kW maximum output when it comes to output voltage, output current, and resonant current. At that time, measured maximum efficiency was 97% under the condition of 454V, 139A. The experiment result of charging current depending on the variation of switching frequency under various kinds of load condition in order to verity its performance with real battery charging condition is shown as
Fig. 17
. When it operates with 48V, 3.8kWh Lead-Acid, 96V 12kWh LiFePO4 battery, 320V 19.2kWh LiFePO4 battery, and variable resistive load for simulating higher voltage battery charging condition of 400V and 500V, the experiment was performed to test the common use of fast chargers varying from output charging voltage of 50V to 500V. Currently used for the full speed EV, 320V and 19.2kWh LiFePO4 batteries were experimented to measure charging time and charging function.
Fig. 18(a)
. shows charging voltage based on charging time. As
Fig. 18(a)
. shows, the charging time from SOC 10% to 90% was about 17 minutes, valid for the EV fast charger. The waveform of the resonant current, the charging voltage, and the charging current are shown in
Fig. 18(b)
.
Specification of 20kW Converter Block
Specification of 20kW Converter Block
Picture of 20kW converter block consisted of two 10kW modules
Experiment setup for 60kW fast charger
Experimental results of 10kW converter module (Time scale: 10us/div. Gating Signal, 10V/div. Resonant Current, 20A/div. Output Voltage, 100V/div. Output Current, 20A/div.)
Efficiency measurement depending on the load
Experimental results of 60kW EV fast charger (Time Scale: 5us/div. Resonant Current, 20A/div. Output Current, 50A/div. Output Voltage, 100V/div)
Experiment result of output current vs. switching frequency for load change for different load
Experimental results for 320V 60Ah LiFePO2 charging test
5. Conclusion
In this paper, the enhanced converter topology based on series loaded resonant converter was proposed for EV fast charger. Adding small parallel resonant capacitor at output rectifier circuits and increasing the lossless snubber capacitance, the proposed converter has the advantage of enhancing the system efficiency especially at the rated load condition because it can reduce the conduction loss by improving the resonance current shape and minimize turn off losses. The design and implementation of the proposed converter have been described and distinctive features of the proposed converter were analyzed. Also, the simple gate drive circuit which can minimize the turn on loss by active detecting zero voltage condition of the IGBT was developed for the proposed converter. The 60kW EV fast charger having an output voltage range of 50V~500V was developed using proposed converter topology and various kinds of test were performed to verify that the proposed resonant converter is suitable for EV Fast charger. The basic tests of the developed EV fast charger were performed using resistive load bank which can simulate the various types of battery with different charging conditions. And real battery charging tests also performed by using three kinds different type of high capacity batteries. From the experiments, maximum efficiency was measured as 98.5% for 10kW DC-DC module, and 97% for a 60kw AC to DC EV fast charger including rectifying circuits. For the fast charging of 320V, 19.2kWh LiFePO4 battery, the charging time from 10% to 90% SOC was measured as 17 minutes. It was verified from various kinds of tests that proposed converter is suitable for the high efficiency EV fast charger which is usually operated at maximum rated charging current condition.
The developed EV fast charger was installed at Korean EV test infrastructure and practical charging test with various kinds of EVs has been now performing.
BIO
Suk-Ho Ahn received the B.S. degree in electrical engineering from Incheon National University, Incheon, Republic of Korea, in 2009 and is currently pursuing both his M.S. and Ph.D. degrees at the University of Science & Technology (UST) in Daejeon, Republic of Korea. His research interests include the soft switched resonant converter applications and battery charger systems.
Ji-woong Gong received the B.S. in electrical engineering from Chonnam National University, Gwangju, Republic of Korea, in 2012 and is currently pursuing the M.S. degree at the University of Science & Technology (UST) in Daejeon, Republic of Korea. His research interests include the soft switched resonant converter applications and High Voltage Pulsed Power Supply Systems.
Sung-Roc Jang was born in Daegu, Korea, in 1983. He received his B.S. from Kyungpook National University, Daegu, Korea, in 2008, and the M.S. and Ph.D. in Electronic Engineering from the University of Science & Technology (UST), Deajeon, Korea, in 2011. Since 2011, he has been with the Korea Electro-technology Research Institute as a senior researcher of electric propulsion research center. His current research interests include high-voltage resonant converters and solid-state pulsed power modulators and their industrial applications. Dr. Jang received the Young Scientist Award at 3rd Euro- Asian Pulsed Power Conference in 2010, and the IEEE Nuclear Plasma Science Society (NPSS) Best Student Paper Award at IEEE International Pulsed Power Conference in 2011.
Hong-Je Ryoo received the B.S., M.S., and Ph.D. degrees in electrical engineeering from SungKyunkwan University, Seoul, Korea in 1991, 1995, and 2001, respectively. From 2004 to 2005, he was with WEMPEC at the University of Wisconsin-Madison, as a Visiting Scholar for his postdoctoral study. Since 1996, he has been with the Korea Electrotechnology Research Institute in Changwon, Korea. He is currently a Principal Research Engineer in the Electric Propulsion Research Division and a Leader of the Pulsed Power World Class Laboratory at that institute. Also, he has been a Professor in the Department of Energy Conversion Technology, University of Science & Technology, Deajeon, Korea, since 2005. His current research interests include pulsed power systems and their applications, as well as high power and high voltage conversions. He has published numerous papers at IEEE transactions and has obtained more than 20 Korean and industrial patents. Also he made 8 contracts with industrial firm based on his patents and succeeded to commercialize his high voltage solid state modulators. He received many awards due to industry applied technical contribution including ISTK Chairman Award from Korea Research Council for Industrial Science & Technology in 2009, Technical Award from Ministry of Science and Technology of Korea in 2010 and Dasan Technology Award from The Korea Economic Daily in 2011. Dr. Ryoo is a member of the Korean Institute of Power Electronics (KIPE), and the Korean Institute of Electrical Engineers (KIEE).
Duk-Heon Kim was born in Daegu, Korea, in 1964. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from SungKyunkwan University in Seoul, Korea in 1990, 1992, and 2002, respectively. Since 1994, he has been an associate professor in the department of electric railway, college of catholic sangji, Korea. His research interests mainly focused on power system & applications. He is a member of the Korean Institute of Power Electronics (KIPE), and the Korean Institute of Electrical Engineers (KIEE).
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