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Design Optimization of Silicon-based Junctionless Fin-type Field-Effect Transistors for Low Standby Power Technology
Design Optimization of Silicon-based Junctionless Fin-type Field-Effect Transistors for Low Standby Power Technology
Journal of Electrical Engineering and Technology. 2013. Nov, 8(6): 1497-1502
Copyright © 2013, The Korean Institute of Electrical Engineers
  • Received : May 21, 2013
  • Accepted : June 27, 2013
  • Published : November 01, 2013
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About the Authors
Jae Hwa Seo
School of Electronics Engineering, Kyungpook National University, Korea. (jhseo@ee.knu.ac.kr)
Heng Yuan
School of Instrumentation Science and Optoelectronics Engineering, Beihang University, China. (yuanheng1981@hotmail.com)
In Man Kang
Corresponding Author: School of Electronics Engineering, Kyungpook National University, Korea. (imkang@ee.knu.ac.kr)

Abstract
Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET’s problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ( W fin ), fin height ( H fin ), and doping concentration ( D ch ). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.
Keywords
1. Introduction
These days, semiconductor devices based on a silicon substrate are being developed for better electrical characteristics and cost-efficiency. However, conventional silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET) technologies are faced with their scaling limit as transistor size continues to decrease [1 - 4] . Thus, instead of traditional n/p/n or p/n/p MOSFET, many studies for the junctionless (JL) MOSFET have been reported. The JL MOSFET was originally proposed and demonstrated by Colinge et al [5 - 6] . This transistor, which has no pn junctions, operates in accumulation mode (AM) and a degenerate p-type polysilicon gate is used for adjusting threshold voltage to be positive so that its operations are same as the conventional n-type MOSFET. But unlike the conventional short-channel MOSFET need to make highly precise junctions, the JL MOSFETs do not need to form junctions. Thus, the JL MOSFET can overcome many fabrication issues in view of doping techniques and thermal budget without short-channel effects (SCEs) [7 - 11] .
In this paper, design optimization of the JL MOSFET which have a fin-type structure (JL FinFET) is performed in view of threshold voltage ( V th ), higher gate controllability, enhanced current drivability, and better subthreshold swing ( SS ). The device was designed with a Silvaco three-dimensional (3D) technology computer-aided design (TCAD) simulation program [12] and the optimization reference of this work is the low standby power technology (LSPT) performances of international technology roadmap for semiconductors (ITRS) roadmap [13] . Also, to obtain accurate results for simulations, electron concentration model, electron-field model, gate current assignment model, and 3D-structure mobility model is considered [12] . Finally, the important parameters such as transconductance ( g m ), cut-off frequency ( f T ), and maximum oscillation frequency ( f max ) are extracted after an optimization process for DC performances.
2. Simulation Results
Fig. 1 shows the structure of JL FinFET with 20 nm channel length ( L ch ) simulated by the 3D TCAD program. To avoid polysilicon gate depletion, a degenerately doped polysilicon gate was adopted. The gate dielectric material is hafnium oxide (HfO 2 ) with 2 nm thickness ( t ox ).
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The structure of JL FinFET with 20 nm channel length (Lch) simulated by the 3D TCAD program.
The on-state current ( I on ) was defined as a drain current ( I DS ) at V GS = V DS = 1 V and the off-state current ( I off ) was defined as an point of V GS where I DS begins to burst. The V th was defined as V GS at I DS = 10 -7 A/μm.
The current of JL MOSFET is dominated by body current instead of surface current between gate oxide and inversion channel layer. Therefore, the channel doping concentration ( D ch ), fin height ( H fin ), and fin width ( W fin ) which are important variables for device optimization process are designated as the simulation variables. Fig. 2 shows the I DS - V GS transfer curves for JL FinFET with various channel doping concentration. Dch was changed ntype 1×1018 cm −3 to 4×1019 cm −3 . Both Hfin and Wfin are fixed at 10 nm. When the D ch increases, V th goes decrease and I on as well as I off is increases. The Vth is changed by depletion layer of channel region. The relationship between D ch and depletion layer for MOS structure is presented by (1) [14] .
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IDS-VGS transfer curves for JL FinFET with various channel doping concentration.
where ε s is the semiconductor permittivity, Ф bi is the built in potential and q is the electric potential.
The width of depletion region ( W d ) is reduced by increase of D ch . JL devices are dominated not by surface current but by body current. Therefore, the high N ch makes it difficult to fully deplete under the gate and V th is decreased. The characteristics of V th according to D ch are summarized in Fig. 3 .
Fig. 3 shows V th as a function of D ch . It is confirmed that V th appears to be a negative linear function of D ch . The horizontal slashed area is the section of V th due to the LSPT operation reference suggested by the ITRS Roadmap, and its vicinity with ±0.1 V. The vertical slashed area represents the range of D ch satisfying V th reference range. The corresponding D ch range to the V th is 2.3×10 19 cm −3 to 3×10 19 cm −3 .
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Vth curves as a function of Dch.
Fig. 4 demonstrates the detailed graph for on- and offstate current for the range of the optimized D ch range of Fig. 3 . The current level of JL FinFET has lower limit of I on (500 μA/μm) and upper limit of I off (10 pA/μm) for dependable LSPT operations. The I on and I off increased by changes of bulk driving current and leakage current that was caused by decrease of W d , respectively. It turns out that the permissible D ch satisfied with V th , I on , and I off level is vicinity of 2.7×10 19 cm −3.
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On-state current and off-state current at the optimized Dch range.
Fig. 5 depicts the subthreshold swing ( SS ) as a function Dch. 69 mV/dec to 71 mV/dec SS characteristics are observed over D ch region and the vicinity of 2.7×10 19 cm −3 where the point of SS reflection should be desirable at channel doping concentration. The values of SS has the minimum variation near D ch = 2.7×10 19 cm -3 . Fig. 6 demonstrates the I DS - V GS transfer curves for JL FinFET according to various W fin . As Wfin increases, the channel region where electrons flow is distends and Ion increases. However, the large W fin makes hard to fully deplete channel region at an off-state. Accordingly, the Ioff increases dramatically. The difference of electron concentration under the off-state with W fin of 5 nm and Wfin of 20 nm is depicts at Fig. 7. The maximum electron concentration of channel region was obtained 1.61 cm −3 and 12.9 cm −3 , respectively, at W fin of 5 nm and W fin of 20 nm. It indicates that the increase of W fin makes difficult to control the I off .
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Subthreshold swing (SS) as a function of Dch.
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IDS-VGS transfer curves for JL FinFET according to various Wfin.
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Electron concentration under the off-state for JL FinFETs with (a) Wfin of 5 nm and (b) Wfin of 20 nm. (Dch = 2.7×1019 cm−3, VDS = −1 V)
Fig. 8 shows the changes of SS and V th with different W fin . When Wfin increases, transistor needs less gate voltages to achieve turn-on condition and consequentially, Vth decreases. On the other hand, SS shows increasing results because a variation of I off is much higher than variation of I on . By the LSPT operation range of V th , the Wfin of 6 nm to 10 nm is suggested as an optimized parameter.
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SS and Vth curves with different Wfin.
Fig. 9 is the I DS - V GS transfer curves for JL FinFet according to various H fin . The increase of H fin also increases the channel region that current flows. However, the changes of H fin are less vulnerable to I off than that of Wfin. Although the increase of H fi n increases I off, the Finside depletion area is fastened by fixed Wfin. It can be observed at Fig. 10 which shows electron concentration of high W fin and high H fin under the off-state. In this figure, it is confirmed that low H fin of JL FinFET is easier to deplete all channel area and I off should be much lower. Fig. 11 depicts the changes of SS and V th with different H fin . The V th and SS are in inverse proportion to the H fin . And by the LSPT operation range of V th , the H fin of under 10 nm are an optimized regions. In this region, the H fin of 10 nm where has an minimum value of SS is the optimized result of H fin .
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IDS-VGS transfer curves for JL FinFET according to various Hfin.
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Electron concentration at (a) high Wfin=20 nm and (b) high Hfin=20 nm under the off-state. (Dch = 2.7×1019 cm-3,VDS = -1 V)
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SS and Vth curves with different Hfin.
Fig. 12 show the main conductance characteristics of optimized JL FinFET with D ch of 2.7×10 19 cm −3 , W fin of 10 nm, and H fin of 10 nm. The transconductance ( g m ) and source-drain conductance ( g ds ) determine the cut-off frequency ( f T ) and maximum oscillation frequency ( f max ) by following equations (2) and (3) [15] .
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The transconductance (gm) and source-drain conductance (gds) characteristics of an optimized JL FinFET with Dch of 2.7×1019 cm−3, Wfin of 10 nm, and Hfin of 10 nm.
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where g m is the transconductance, C gg is the gate input capacitance, R g,eff is the effective gate resistance comprising gate electrode resistance and distributed channel resistance, and C gd is the gate-to-drain capacitance. quation 2, it is known that to achieve high fT, the large value of g m should be needed. In Fig. 12 , both g m and g ds increases and saturations near V GS = 0.5 V. Thus, a desirable operation conditions to guarantee high f T should be V GS > 0.5 V.
Figs. 13 (a) and (b) shows the capacitance and resistance of optimized JL FinFET. These characteristics are related with f T and fmax which expressed by equations (2) and (b). Fig. 13 (c) depicts the f T and fmax as a function of V GS . In both f T and f max are monotonically increases with voltages. The f T and fmax was obtained 213.3 GHz and 366.6 GHz respectively at V GS = V DS = 1 V where an operation point.
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(a) Capacitance and (b) resistance of optimized JL FinFET. (c) fT and fmax as a function of VGS. In both fT and fmax are monotonically increases with voltages.
Fig. 14 demonstrates the drain-induced barrier lowering (DIBL) characteristics of optimized JL FinFET. In terms of suppress SCEs (SS ≤ 100 mV/dec, DIBL ≤ 100 mV/V) [16] , the optimized JL FinFET is efficiently satisfying these conditions.
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IDS-VGS transfer curves for optimized JL FinFET and characteristics of DIBL.
Optimized device performances and conditions summary
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Optimized device performances and conditions summary
5. Conclusion
this paper, we have been performed 3D TCAD simulation of JL FinFET and confirmed the device performances. The JL FinFET is suitable semiconductor devices with LSPT applications and the optimum design of transistor was satisfying the requirement of ITRS roadmap. To optimize the JL FinFET, various DC parameters including V th , I on , I off , SS , and g m was considered. Through the simulation result, the optimum design conditions of JL FinFET with L ch of 20 nm and tox of 2nm were as follows: D ch of 2.7×10 19 cm −3 , Wfin of 6 ∼ 10 nm, and H fin of under 10 nm. Finally, under the condition which D ch of 2.7×10 19 cm −3 , Wfin of 10 nm, and H fin of 10 nm, the f T and f max were obtained as 213.3 GHz and 366.6 GHz respectively. Consequently, the optimized JL FinFET can be a promising structure of next-generation silicon-based LSPT transistors.
Acknowledgements
This work was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (MEST) (No. 2013- 011522).
BIO
Jae Hwa Seo He received the B.S. degree in electrical engineering from the School of Electronics Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2012. He is currently working toward the M.S. degree in electrical engineering with the School of Electronics Engineering (SEE), Kyungpook National University (KNU). His research interests include design, fabrication, and characterization of nanoscale CMOS, tunneling FET, III-V compound transistors, and junctionless silicon devices.
Heng Yuan He received his B.S. degree in College of Information and Electrical Engineering, Shandong University of Science and Technology, China, in 2003. And the Ph.D. degree in School of Electrical Engineering and Computer Science (EECS), Kyungpook National University (KNU), Daegu, Korea, in 2013. In 2013, he joined Beihang University (BUAA) as a associate professor. His research activities include nanodevice, inertial sensors, magnetic sensors, and atomic spin effect.
In Man Kang He received the B.S. degree in electronic and electrical engineering from School of Electronics and Electrical Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2001, and the Ph.D. degree in electrical engineering from School of Electrical Engineering and Computer Science (EECS), Seoul National University (SNU), Seoul, Korea, in 2007. He worked as a teaching assistant for semiconductor process education from 2001 to 2006 at Inter-university Semiconductor Research Center (ISRC) in SNU. From 2007 to 2010, he worked as a senior engineer at Design Technology Team of Samsung Electronics Company. In 2010, he joined KNU as a full-time lecturer of the School of Electronics Engineering (SEE). Now, he has worked as an assistant professor. His current research interests include CMOS RF modeling, silicon nanowire devices, tunneling transistor, low-power nano CMOS, and III-V compound semiconductors. He is a member of IEEE EDSc
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